xref: /rk3399_rockchip-uboot/arch/sandbox/include/asm/test.h (revision 9569c40668290408eac447f9be99dab603c8e34c)
16ec1b753SSimon Glass /*
26ec1b753SSimon Glass  * Test-related constants for sandbox
36ec1b753SSimon Glass  *
46ec1b753SSimon Glass  * Copyright (c) 2014 Google, Inc
56ec1b753SSimon Glass  *
66ec1b753SSimon Glass  * SPDX-License-Identifier:	GPL-2.0+
76ec1b753SSimon Glass  */
86ec1b753SSimon Glass 
96ec1b753SSimon Glass #ifndef __ASM_TEST_H
106ec1b753SSimon Glass #define __ASM_TEST_H
116ec1b753SSimon Glass 
126ec1b753SSimon Glass /* The sandbox driver always permits an I2C device with this address */
136ec1b753SSimon Glass #define SANDBOX_I2C_TEST_ADDR		0x59
14*9569c406SSimon Glass 
15*9569c406SSimon Glass #define SANDBOX_PCI_VENDOR_ID		0x1234
16*9569c406SSimon Glass #define SANDBOX_PCI_DEVICE_ID		0x5678
17*9569c406SSimon Glass #define SANDBOX_PCI_CLASS_CODE		PCI_CLASS_CODE_COMM
18*9569c406SSimon Glass #define SANDBOX_PCI_CLASS_SUB_CODE	PCI_CLASS_SUB_CODE_COMM_SERIAL
196ec1b753SSimon Glass 
206ec1b753SSimon Glass enum sandbox_i2c_eeprom_test_mode {
216ec1b753SSimon Glass 	SIE_TEST_MODE_NONE,
226ec1b753SSimon Glass 	/* Permits read/write of only one byte per I2C transaction */
236ec1b753SSimon Glass 	SIE_TEST_MODE_SINGLE_BYTE,
246ec1b753SSimon Glass };
256ec1b753SSimon Glass 
266ec1b753SSimon Glass void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
276ec1b753SSimon Glass 				      enum sandbox_i2c_eeprom_test_mode mode);
286ec1b753SSimon Glass 
296ec1b753SSimon Glass void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
306ec1b753SSimon Glass 
316ec1b753SSimon Glass #endif
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