1a47a12beSStefan Roese/* 2a47a12beSStefan Roese * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3a47a12beSStefan Roese * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4a47a12beSStefan Roese * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5a47a12beSStefan Roese * Copyright Freescale Semiconductor, Inc. 2004, 2006. 6a47a12beSStefan Roese * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8a47a12beSStefan Roese */ 9a47a12beSStefan Roese 10a47a12beSStefan Roese#include <config.h> 11a47a12beSStefan Roese#include <ppc_asm.tmpl> 12*ac337168SValentin Longchamp#include <ppc_defs.h> 13*ac337168SValentin Longchamp 14*ac337168SValentin Longchamp#include <asm/cache.h> 15a47a12beSStefan Roese 16a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 17a47a12beSStefan Roese/* Function: ppcDcbf */ 18a47a12beSStefan Roese/* Description: Data Cache block flush */ 19a47a12beSStefan Roese/* Input: r3 = effective address */ 20a47a12beSStefan Roese/* Output: none. */ 21a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 22a47a12beSStefan Roese .globl ppcDcbf 23a47a12beSStefan RoeseppcDcbf: 24a47a12beSStefan Roese dcbf r0,r3 25a47a12beSStefan Roese blr 26a47a12beSStefan Roese 27a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 28a47a12beSStefan Roese/* Function: ppcDcbi */ 29a47a12beSStefan Roese/* Description: Data Cache block Invalidate */ 30a47a12beSStefan Roese/* Input: r3 = effective address */ 31a47a12beSStefan Roese/* Output: none. */ 32a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 33a47a12beSStefan Roese .globl ppcDcbi 34a47a12beSStefan RoeseppcDcbi: 35a47a12beSStefan Roese dcbi r0,r3 36a47a12beSStefan Roese blr 37a47a12beSStefan Roese 38a47a12beSStefan Roese/*-------------------------------------------------------------------------- 39a47a12beSStefan Roese * Function: ppcDcbz 40a47a12beSStefan Roese * Description: Data Cache block zero. 41a47a12beSStefan Roese * Input: r3 = effective address 42a47a12beSStefan Roese * Output: none. 43a47a12beSStefan Roese *-------------------------------------------------------------------------- */ 44a47a12beSStefan Roese 45a47a12beSStefan Roese .globl ppcDcbz 46a47a12beSStefan RoeseppcDcbz: 47a47a12beSStefan Roese dcbz r0,r3 48a47a12beSStefan Roese blr 49a47a12beSStefan Roese 50a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 51a47a12beSStefan Roese/* Function: ppcSync */ 52a47a12beSStefan Roese/* Description: Processor Synchronize */ 53a47a12beSStefan Roese/* Input: none. */ 54a47a12beSStefan Roese/* Output: none. */ 55a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 56a47a12beSStefan Roese .globl ppcSync 57a47a12beSStefan RoeseppcSync: 58a47a12beSStefan Roese sync 59a47a12beSStefan Roese blr 60*ac337168SValentin Longchamp 61*ac337168SValentin Longchamp/* 62*ac337168SValentin Longchamp * Write any modified data cache blocks out to memory and invalidate them. 63*ac337168SValentin Longchamp * Does not invalidate the corresponding instruction cache blocks. 64*ac337168SValentin Longchamp * 65*ac337168SValentin Longchamp * flush_dcache_range(unsigned long start, unsigned long stop) 66*ac337168SValentin Longchamp */ 67*ac337168SValentin Longchamp_GLOBAL(flush_dcache_range) 68*ac337168SValentin Longchamp li r5,L1_CACHE_BYTES-1 69*ac337168SValentin Longchamp andc r3,r3,r5 70*ac337168SValentin Longchamp subf r4,r3,r4 71*ac337168SValentin Longchamp add r4,r4,r5 72*ac337168SValentin Longchamp srwi. r4,r4,L1_CACHE_SHIFT 73*ac337168SValentin Longchamp beqlr 74*ac337168SValentin Longchamp mtctr r4 75*ac337168SValentin Longchamp 76*ac337168SValentin Longchamp1: dcbf 0,r3 77*ac337168SValentin Longchamp addi r3,r3,L1_CACHE_BYTES 78*ac337168SValentin Longchamp bdnz 1b 79*ac337168SValentin Longchamp sync /* wait for dcbst's to get to ram */ 80*ac337168SValentin Longchamp blr 81*ac337168SValentin Longchamp 82*ac337168SValentin Longchamp/* 83*ac337168SValentin Longchamp * Like above, but invalidate the D-cache. This is used by the 8xx 84*ac337168SValentin Longchamp * to invalidate the cache so the PPC core doesn't get stale data 85*ac337168SValentin Longchamp * from the CPM (no cache snooping here :-). 86*ac337168SValentin Longchamp * 87*ac337168SValentin Longchamp * invalidate_dcache_range(unsigned long start, unsigned long stop) 88*ac337168SValentin Longchamp */ 89*ac337168SValentin Longchamp_GLOBAL(invalidate_dcache_range) 90*ac337168SValentin Longchamp li r5,L1_CACHE_BYTES-1 91*ac337168SValentin Longchamp andc r3,r3,r5 92*ac337168SValentin Longchamp subf r4,r3,r4 93*ac337168SValentin Longchamp add r4,r4,r5 94*ac337168SValentin Longchamp srwi. r4,r4,L1_CACHE_SHIFT 95*ac337168SValentin Longchamp beqlr 96*ac337168SValentin Longchamp mtctr r4 97*ac337168SValentin Longchamp 98*ac337168SValentin Longchamp sync 99*ac337168SValentin Longchamp1: dcbi 0,r3 100*ac337168SValentin Longchamp addi r3,r3,L1_CACHE_BYTES 101*ac337168SValentin Longchamp bdnz 1b 102*ac337168SValentin Longchamp sync /* wait for dcbi's to get to ram */ 103*ac337168SValentin Longchamp blr 104*ac337168SValentin Longchamp 105