1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2002 3*a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6*a47a12beSStefan Roese * project. 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11*a47a12beSStefan Roese * the License, or (at your option) any later version. 12*a47a12beSStefan Roese * 13*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*a47a12beSStefan Roese * GNU General Public License for more details. 17*a47a12beSStefan Roese * 18*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*a47a12beSStefan Roese * MA 02111-1307 USA 22*a47a12beSStefan Roese */ 23*a47a12beSStefan Roese 24*a47a12beSStefan Roese #include <common.h> 25*a47a12beSStefan Roese #include <asm/cache.h> 26*a47a12beSStefan Roese #include <watchdog.h> 27*a47a12beSStefan Roese 28*a47a12beSStefan Roese void flush_cache(ulong start_addr, ulong size) 29*a47a12beSStefan Roese { 30*a47a12beSStefan Roese #ifndef CONFIG_5xx 31*a47a12beSStefan Roese ulong addr, start, end; 32*a47a12beSStefan Roese 33*a47a12beSStefan Roese start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); 34*a47a12beSStefan Roese end = start_addr + size - 1; 35*a47a12beSStefan Roese 36*a47a12beSStefan Roese for (addr = start; (addr <= end) && (addr >= start); 37*a47a12beSStefan Roese addr += CONFIG_SYS_CACHELINE_SIZE) { 38*a47a12beSStefan Roese asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); 39*a47a12beSStefan Roese WATCHDOG_RESET(); 40*a47a12beSStefan Roese } 41*a47a12beSStefan Roese /* wait for all dcbst to complete on bus */ 42*a47a12beSStefan Roese asm volatile("sync" : : : "memory"); 43*a47a12beSStefan Roese 44*a47a12beSStefan Roese for (addr = start; (addr <= end) && (addr >= start); 45*a47a12beSStefan Roese addr += CONFIG_SYS_CACHELINE_SIZE) { 46*a47a12beSStefan Roese asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); 47*a47a12beSStefan Roese WATCHDOG_RESET(); 48*a47a12beSStefan Roese } 49*a47a12beSStefan Roese asm volatile("sync" : : : "memory"); 50*a47a12beSStefan Roese /* flush prefetch queue */ 51*a47a12beSStefan Roese asm volatile("isync" : : : "memory"); 52*a47a12beSStefan Roese #endif 53*a47a12beSStefan Roese } 54