1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * (C) Copyright 2002 3a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4a47a12beSStefan Roese * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6a47a12beSStefan Roese */ 7a47a12beSStefan Roese 8a47a12beSStefan Roese #include <common.h> 9a47a12beSStefan Roese #include <asm/cache.h> 10a47a12beSStefan Roese #include <watchdog.h> 11a47a12beSStefan Roese flush_cache(ulong start_addr,ulong size)12a47a12beSStefan Roesevoid flush_cache(ulong start_addr, ulong size) 13a47a12beSStefan Roese { 14a47a12beSStefan Roese #ifndef CONFIG_5xx 15a47a12beSStefan Roese ulong addr, start, end; 16a47a12beSStefan Roese 17a47a12beSStefan Roese start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); 18a47a12beSStefan Roese end = start_addr + size - 1; 19a47a12beSStefan Roese 20a47a12beSStefan Roese for (addr = start; (addr <= end) && (addr >= start); 21a47a12beSStefan Roese addr += CONFIG_SYS_CACHELINE_SIZE) { 22a47a12beSStefan Roese asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); 23a47a12beSStefan Roese WATCHDOG_RESET(); 24a47a12beSStefan Roese } 25a47a12beSStefan Roese /* wait for all dcbst to complete on bus */ 26a47a12beSStefan Roese asm volatile("sync" : : : "memory"); 27a47a12beSStefan Roese 28a47a12beSStefan Roese for (addr = start; (addr <= end) && (addr >= start); 29a47a12beSStefan Roese addr += CONFIG_SYS_CACHELINE_SIZE) { 30a47a12beSStefan Roese asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); 31a47a12beSStefan Roese WATCHDOG_RESET(); 32a47a12beSStefan Roese } 33a47a12beSStefan Roese asm volatile("sync" : : : "memory"); 34a47a12beSStefan Roese /* flush prefetch queue */ 35a47a12beSStefan Roese asm volatile("isync" : : : "memory"); 36a47a12beSStefan Roese #endif 37a47a12beSStefan Roese } 38