1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2008 3*a47a12beSStefan Roese * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es 4*a47a12beSStefan Roese * This work has been supported by: QTechnology http://qtec.com/ 5*a47a12beSStefan Roese * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de 6*a47a12beSStefan Roese * This program is free software: you can redistribute it and/or modify 7*a47a12beSStefan Roese * it under the terms of the GNU General Public License as published by 8*a47a12beSStefan Roese * the Free Software Foundation, either version 2 of the License, or 9*a47a12beSStefan Roese * (at your option) any later version. 10*a47a12beSStefan Roese * 11*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 12*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*a47a12beSStefan Roese * GNU General Public License for more details. 15*a47a12beSStefan Roese * 16*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 17*a47a12beSStefan Roese * along with this program. If not, see <http://www.gnu.org/licenses/>. 18*a47a12beSStefan Roese */ 19*a47a12beSStefan Roese #ifndef XILINX_IRQ_H 20*a47a12beSStefan Roese #define XILINX_IRQ_H 21*a47a12beSStefan Roese 22*a47a12beSStefan Roese #define intc XPAR_INTC_0_BASEADDR 23*a47a12beSStefan Roese #define ISR (intc + (0 * 4)) /* Interrupt Status Register */ 24*a47a12beSStefan Roese #define IPR (intc + (1 * 4)) /* Interrupt Pending Register */ 25*a47a12beSStefan Roese #define IER (intc + (2 * 4)) /* Interrupt Enable Register */ 26*a47a12beSStefan Roese #define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */ 27*a47a12beSStefan Roese #define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */ 28*a47a12beSStefan Roese #define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */ 29*a47a12beSStefan Roese #define IVR (intc + (6 * 4)) /* Interrupt Vector Register */ 30*a47a12beSStefan Roese #define MER (intc + (7 * 4)) /* Master Enable Register */ 31*a47a12beSStefan Roese 32*a47a12beSStefan Roese #define IRQ_MASK(irq) (1 << (irq & 0x1f)) 33*a47a12beSStefan Roese 34*a47a12beSStefan Roese #define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS 35*a47a12beSStefan Roese 36*a47a12beSStefan Roese #endif 37