1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2000 - 2002 3*a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 6*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 7*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 8*a47a12beSStefan Roese * the License, or (at your option) any later version. 9*a47a12beSStefan Roese * 10*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 11*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 12*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*a47a12beSStefan Roese * GNU General Public License for more details. 14*a47a12beSStefan Roese * 15*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 16*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 17*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18*a47a12beSStefan Roese * MA 02111-1307 USA 19*a47a12beSStefan Roese * 20*a47a12beSStefan Roese ******************************************************************** 21*a47a12beSStefan Roese * NOTE: This header file defines an interface to U-Boot. Including 22*a47a12beSStefan Roese * this (unmodified) header file in another file is considered normal 23*a47a12beSStefan Roese * use of U-Boot, and does *not* fall under the heading of "derived 24*a47a12beSStefan Roese * work". 25*a47a12beSStefan Roese ******************************************************************** 26*a47a12beSStefan Roese */ 27*a47a12beSStefan Roese 28*a47a12beSStefan Roese #ifndef __U_BOOT_H__ 29*a47a12beSStefan Roese #define __U_BOOT_H__ 30*a47a12beSStefan Roese 31*a47a12beSStefan Roese /* 32*a47a12beSStefan Roese * Board information passed to Linux kernel from U-Boot 33*a47a12beSStefan Roese * 34*a47a12beSStefan Roese * include/asm-ppc/u-boot.h 35*a47a12beSStefan Roese */ 36*a47a12beSStefan Roese 37*a47a12beSStefan Roese #ifndef __ASSEMBLY__ 38*a47a12beSStefan Roese 39*a47a12beSStefan Roese typedef struct bd_info { 40*a47a12beSStefan Roese unsigned long bi_memstart; /* start of DRAM memory */ 41*a47a12beSStefan Roese phys_size_t bi_memsize; /* size of DRAM memory in bytes */ 42*a47a12beSStefan Roese unsigned long bi_flashstart; /* start of FLASH memory */ 43*a47a12beSStefan Roese unsigned long bi_flashsize; /* size of FLASH memory */ 44*a47a12beSStefan Roese unsigned long bi_flashoffset; /* reserved area for startup monitor */ 45*a47a12beSStefan Roese unsigned long bi_sramstart; /* start of SRAM memory */ 46*a47a12beSStefan Roese unsigned long bi_sramsize; /* size of SRAM memory */ 47*a47a12beSStefan Roese #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ 48*a47a12beSStefan Roese || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 49*a47a12beSStefan Roese unsigned long bi_immr_base; /* base of IMMR register */ 50*a47a12beSStefan Roese #endif 51*a47a12beSStefan Roese #if defined(CONFIG_MPC5xxx) 52*a47a12beSStefan Roese unsigned long bi_mbar_base; /* base of internal registers */ 53*a47a12beSStefan Roese #endif 54*a47a12beSStefan Roese #if defined(CONFIG_MPC83xx) 55*a47a12beSStefan Roese unsigned long bi_immrbar; 56*a47a12beSStefan Roese #endif 57*a47a12beSStefan Roese #if defined(CONFIG_MPC8220) 58*a47a12beSStefan Roese unsigned long bi_mbar_base; /* base of internal registers */ 59*a47a12beSStefan Roese unsigned long bi_inpfreq; /* Input Freq, In MHz */ 60*a47a12beSStefan Roese unsigned long bi_pcifreq; /* PCI Freq, in MHz */ 61*a47a12beSStefan Roese unsigned long bi_pevfreq; /* PEV Freq, in MHz */ 62*a47a12beSStefan Roese unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */ 63*a47a12beSStefan Roese unsigned long bi_vcofreq; /* VCO Freq, in MHz */ 64*a47a12beSStefan Roese #endif 65*a47a12beSStefan Roese unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ 66*a47a12beSStefan Roese unsigned long bi_ip_addr; /* IP Address */ 67*a47a12beSStefan Roese unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ 68*a47a12beSStefan Roese unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ 69*a47a12beSStefan Roese unsigned long bi_intfreq; /* Internal Freq, in MHz */ 70*a47a12beSStefan Roese unsigned long bi_busfreq; /* Bus Freq, in MHz */ 71*a47a12beSStefan Roese #if defined(CONFIG_CPM2) 72*a47a12beSStefan Roese unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ 73*a47a12beSStefan Roese unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ 74*a47a12beSStefan Roese unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ 75*a47a12beSStefan Roese unsigned long bi_vco; /* VCO Out from PLL, in MHz */ 76*a47a12beSStefan Roese #endif 77*a47a12beSStefan Roese #if defined(CONFIG_MPC512X) 78*a47a12beSStefan Roese unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ 79*a47a12beSStefan Roese #endif /* CONFIG_MPC512X */ 80*a47a12beSStefan Roese #if defined(CONFIG_MPC5xxx) 81*a47a12beSStefan Roese unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ 82*a47a12beSStefan Roese unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ 83*a47a12beSStefan Roese #endif 84*a47a12beSStefan Roese unsigned long bi_baudrate; /* Console Baudrate */ 85*a47a12beSStefan Roese #if defined(CONFIG_405) || \ 86*a47a12beSStefan Roese defined(CONFIG_405GP) || \ 87*a47a12beSStefan Roese defined(CONFIG_405CR) || \ 88*a47a12beSStefan Roese defined(CONFIG_405EP) || \ 89*a47a12beSStefan Roese defined(CONFIG_405EZ) || \ 90*a47a12beSStefan Roese defined(CONFIG_405EX) || \ 91*a47a12beSStefan Roese defined(CONFIG_440) 92*a47a12beSStefan Roese unsigned char bi_s_version[4]; /* Version of this structure */ 93*a47a12beSStefan Roese unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ 94*a47a12beSStefan Roese unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ 95*a47a12beSStefan Roese unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ 96*a47a12beSStefan Roese unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ 97*a47a12beSStefan Roese unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ 98*a47a12beSStefan Roese #endif 99*a47a12beSStefan Roese #if defined(CONFIG_HYMOD) 100*a47a12beSStefan Roese hymod_conf_t bi_hymod_conf; /* hymod configuration information */ 101*a47a12beSStefan Roese #endif 102*a47a12beSStefan Roese 103*a47a12beSStefan Roese #ifdef CONFIG_HAS_ETH1 104*a47a12beSStefan Roese unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ 105*a47a12beSStefan Roese #endif 106*a47a12beSStefan Roese #ifdef CONFIG_HAS_ETH2 107*a47a12beSStefan Roese unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ 108*a47a12beSStefan Roese #endif 109*a47a12beSStefan Roese #ifdef CONFIG_HAS_ETH3 110*a47a12beSStefan Roese unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ 111*a47a12beSStefan Roese #endif 112*a47a12beSStefan Roese #ifdef CONFIG_HAS_ETH4 113*a47a12beSStefan Roese unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ 114*a47a12beSStefan Roese #endif 115*a47a12beSStefan Roese #ifdef CONFIG_HAS_ETH5 116*a47a12beSStefan Roese unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ 117*a47a12beSStefan Roese #endif 118*a47a12beSStefan Roese 119*a47a12beSStefan Roese #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ 120*a47a12beSStefan Roese defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ 121*a47a12beSStefan Roese defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ 122*a47a12beSStefan Roese defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 123*a47a12beSStefan Roese defined(CONFIG_460EX) || defined(CONFIG_460GT) 124*a47a12beSStefan Roese unsigned int bi_opbfreq; /* OPB clock in Hz */ 125*a47a12beSStefan Roese int bi_iic_fast[2]; /* Use fast i2c mode */ 126*a47a12beSStefan Roese #endif 127*a47a12beSStefan Roese #if defined(CONFIG_NX823) 128*a47a12beSStefan Roese unsigned char bi_sernum[8]; 129*a47a12beSStefan Roese #endif 130*a47a12beSStefan Roese #if defined(CONFIG_4xx) 131*a47a12beSStefan Roese #if defined(CONFIG_440GX) || \ 132*a47a12beSStefan Roese defined(CONFIG_460EX) || defined(CONFIG_460GT) 133*a47a12beSStefan Roese int bi_phynum[4]; /* Determines phy mapping */ 134*a47a12beSStefan Roese int bi_phymode[4]; /* Determines phy mode */ 135*a47a12beSStefan Roese #elif defined(CONFIG_405EP) || defined(CONFIG_440) 136*a47a12beSStefan Roese int bi_phynum[2]; /* Determines phy mapping */ 137*a47a12beSStefan Roese int bi_phymode[2]; /* Determines phy mode */ 138*a47a12beSStefan Roese #else 139*a47a12beSStefan Roese int bi_phynum[1]; /* Determines phy mapping */ 140*a47a12beSStefan Roese int bi_phymode[1]; /* Determines phy mode */ 141*a47a12beSStefan Roese #endif 142*a47a12beSStefan Roese #endif /* defined(CONFIG_4xx) */ 143*a47a12beSStefan Roese } bd_t; 144*a47a12beSStefan Roese 145*a47a12beSStefan Roese #endif /* __ASSEMBLY__ */ 146*a47a12beSStefan Roese #endif /* __U_BOOT_H__ */ 147