1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * (C) Copyright 2000 - 2002 3a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4a47a12beSStefan Roese * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6a47a12beSStefan Roese ******************************************************************** 7a47a12beSStefan Roese * NOTE: This header file defines an interface to U-Boot. Including 8a47a12beSStefan Roese * this (unmodified) header file in another file is considered normal 9a47a12beSStefan Roese * use of U-Boot, and does *not* fall under the heading of "derived 10a47a12beSStefan Roese * work". 11a47a12beSStefan Roese ******************************************************************** 12a47a12beSStefan Roese */ 13a47a12beSStefan Roese 14a47a12beSStefan Roese #ifndef __U_BOOT_H__ 15a47a12beSStefan Roese #define __U_BOOT_H__ 16a47a12beSStefan Roese 17a47a12beSStefan Roese /* 18a47a12beSStefan Roese * Board information passed to Linux kernel from U-Boot 19a47a12beSStefan Roese * 20a47a12beSStefan Roese * include/asm-ppc/u-boot.h 21a47a12beSStefan Roese */ 22a47a12beSStefan Roese 23660c60c4SSimon Glass #ifdef CONFIG_SYS_GENERIC_BOARD 24660c60c4SSimon Glass /* Use the generic board which requires a unified bd_info */ 25660c60c4SSimon Glass #include <asm-generic/u-boot.h> 26660c60c4SSimon Glass #else 27660c60c4SSimon Glass 28a47a12beSStefan Roese #ifndef __ASSEMBLY__ 29a47a12beSStefan Roese 30a47a12beSStefan Roese typedef struct bd_info { 31a47a12beSStefan Roese unsigned long bi_memstart; /* start of DRAM memory */ 32a47a12beSStefan Roese phys_size_t bi_memsize; /* size of DRAM memory in bytes */ 33a47a12beSStefan Roese unsigned long bi_flashstart; /* start of FLASH memory */ 34a47a12beSStefan Roese unsigned long bi_flashsize; /* size of FLASH memory */ 35a47a12beSStefan Roese unsigned long bi_flashoffset; /* reserved area for startup monitor */ 36a47a12beSStefan Roese unsigned long bi_sramstart; /* start of SRAM memory */ 37a47a12beSStefan Roese unsigned long bi_sramsize; /* size of SRAM memory */ 38a47a12beSStefan Roese #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ 39a47a12beSStefan Roese || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 40a47a12beSStefan Roese unsigned long bi_immr_base; /* base of IMMR register */ 41a47a12beSStefan Roese #endif 42a47a12beSStefan Roese #if defined(CONFIG_MPC5xxx) 43a47a12beSStefan Roese unsigned long bi_mbar_base; /* base of internal registers */ 44a47a12beSStefan Roese #endif 45a47a12beSStefan Roese #if defined(CONFIG_MPC83xx) 46a47a12beSStefan Roese unsigned long bi_immrbar; 47a47a12beSStefan Roese #endif 48d98b0523SPeter Tyser unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ 49e5ab702aSAnatolij Gustschin unsigned long bi_ip_addr; /* IP Address */ 50a47a12beSStefan Roese unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ 51a47a12beSStefan Roese unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ 52a47a12beSStefan Roese unsigned long bi_intfreq; /* Internal Freq, in MHz */ 53a47a12beSStefan Roese unsigned long bi_busfreq; /* Bus Freq, in MHz */ 54a47a12beSStefan Roese #if defined(CONFIG_CPM2) 55a47a12beSStefan Roese unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ 56a47a12beSStefan Roese unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ 57a47a12beSStefan Roese unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ 58a47a12beSStefan Roese unsigned long bi_vco; /* VCO Out from PLL, in MHz */ 59a47a12beSStefan Roese #endif 60a47a12beSStefan Roese #if defined(CONFIG_MPC512X) 61a47a12beSStefan Roese unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ 62a47a12beSStefan Roese #endif /* CONFIG_MPC512X */ 63a47a12beSStefan Roese #if defined(CONFIG_MPC5xxx) 64a47a12beSStefan Roese unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ 65a47a12beSStefan Roese unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ 66a47a12beSStefan Roese #endif 67a7e5ee9eSSimon Glass unsigned int bi_baudrate; /* Console Baudrate */ 68a47a12beSStefan Roese #if defined(CONFIG_405) || \ 69a47a12beSStefan Roese defined(CONFIG_405GP) || \ 70a47a12beSStefan Roese defined(CONFIG_405CR) || \ 71a47a12beSStefan Roese defined(CONFIG_405EP) || \ 72a47a12beSStefan Roese defined(CONFIG_405EZ) || \ 73a47a12beSStefan Roese defined(CONFIG_405EX) || \ 74a47a12beSStefan Roese defined(CONFIG_440) 75a47a12beSStefan Roese unsigned char bi_s_version[4]; /* Version of this structure */ 76a47a12beSStefan Roese unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ 77a47a12beSStefan Roese unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ 78a47a12beSStefan Roese unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ 79a47a12beSStefan Roese unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ 80a47a12beSStefan Roese unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ 81a47a12beSStefan Roese #endif 82a47a12beSStefan Roese #if defined(CONFIG_HYMOD) 83a47a12beSStefan Roese hymod_conf_t bi_hymod_conf; /* hymod configuration information */ 84a47a12beSStefan Roese #endif 85a47a12beSStefan Roese 86a47a12beSStefan Roese #ifdef CONFIG_HAS_ETH1 87a47a12beSStefan Roese unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ 88a47a12beSStefan Roese #endif 89a47a12beSStefan Roese #ifdef CONFIG_HAS_ETH2 90a47a12beSStefan Roese unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ 91a47a12beSStefan Roese #endif 92a47a12beSStefan Roese #ifdef CONFIG_HAS_ETH3 93a47a12beSStefan Roese unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ 94a47a12beSStefan Roese #endif 95a47a12beSStefan Roese #ifdef CONFIG_HAS_ETH4 96a47a12beSStefan Roese unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ 97a47a12beSStefan Roese #endif 98a47a12beSStefan Roese #ifdef CONFIG_HAS_ETH5 99a47a12beSStefan Roese unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ 100a47a12beSStefan Roese #endif 101a47a12beSStefan Roese 102a47a12beSStefan Roese #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ 103a47a12beSStefan Roese defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ 104a47a12beSStefan Roese defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ 105a47a12beSStefan Roese defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 106a47a12beSStefan Roese defined(CONFIG_460EX) || defined(CONFIG_460GT) 107a47a12beSStefan Roese unsigned int bi_opbfreq; /* OPB clock in Hz */ 108a47a12beSStefan Roese int bi_iic_fast[2]; /* Use fast i2c mode */ 109a47a12beSStefan Roese #endif 110a47a12beSStefan Roese #if defined(CONFIG_NX823) 111a47a12beSStefan Roese unsigned char bi_sernum[8]; 112a47a12beSStefan Roese #endif 113a47a12beSStefan Roese #if defined(CONFIG_4xx) 114a47a12beSStefan Roese #if defined(CONFIG_440GX) || \ 115a47a12beSStefan Roese defined(CONFIG_460EX) || defined(CONFIG_460GT) 116a47a12beSStefan Roese int bi_phynum[4]; /* Determines phy mapping */ 117a47a12beSStefan Roese int bi_phymode[4]; /* Determines phy mode */ 11825fb02abSWeirich, Bernhard #elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440) 119a47a12beSStefan Roese int bi_phynum[2]; /* Determines phy mapping */ 120a47a12beSStefan Roese int bi_phymode[2]; /* Determines phy mode */ 121a47a12beSStefan Roese #else 122a47a12beSStefan Roese int bi_phynum[1]; /* Determines phy mapping */ 123a47a12beSStefan Roese int bi_phymode[1]; /* Determines phy mode */ 124a47a12beSStefan Roese #endif 125a47a12beSStefan Roese #endif /* defined(CONFIG_4xx) */ 126a47a12beSStefan Roese } bd_t; 127a47a12beSStefan Roese 128a47a12beSStefan Roese #endif /* __ASSEMBLY__ */ 129476af299SMike Frysinger 130660c60c4SSimon Glass #endif /* !CONFIG_SYS_GENERIC_BOARD */ 131660c60c4SSimon Glass 132476af299SMike Frysinger /* For image.h:image_check_target_arch() */ 133476af299SMike Frysinger #define IH_ARCH_DEFAULT IH_ARCH_PPC 134476af299SMike Frysinger 135a47a12beSStefan Roese #endif /* __U_BOOT_H__ */ 136