1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * Freescale non-CPM SPI Controller 3*a47a12beSStefan Roese * 4*a47a12beSStefan Roese * Copyright 2008 Qstreams Networks, Inc. 5*a47a12beSStefan Roese * 6*a47a12beSStefan Roese * This software may be used and distributed according to the 7*a47a12beSStefan Roese * terms of the GNU Public License, Version 2, incorporated 8*a47a12beSStefan Roese * herein by reference. 9*a47a12beSStefan Roese * 10*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 11*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License 12*a47a12beSStefan Roese * Version 2 as published by the Free Software Foundation. 13*a47a12beSStefan Roese * 14*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 15*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*a47a12beSStefan Roese * GNU General Public License for more details. 18*a47a12beSStefan Roese * 19*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 20*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 21*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22*a47a12beSStefan Roese * MA 02111-1307 USA 23*a47a12beSStefan Roese */ 24*a47a12beSStefan Roese 25*a47a12beSStefan Roese #ifndef _ASM_MPC8XXX_SPI_H_ 26*a47a12beSStefan Roese #define _ASM_MPC8XXX_SPI_H_ 27*a47a12beSStefan Roese 28*a47a12beSStefan Roese #include <asm/types.h> 29*a47a12beSStefan Roese 30*a47a12beSStefan Roese #if defined(CONFIG_MPC834x) || \ 31*a47a12beSStefan Roese defined(CONFIG_MPC8313) || \ 32*a47a12beSStefan Roese defined(CONFIG_MPC8315) || \ 33*a47a12beSStefan Roese defined(CONFIG_MPC837x) 34*a47a12beSStefan Roese 35*a47a12beSStefan Roese typedef struct spi8xxx { 36*a47a12beSStefan Roese u8 res0[0x20]; /* 0x0-0x01f reserved */ 37*a47a12beSStefan Roese u32 mode; /* mode register */ 38*a47a12beSStefan Roese u32 event; /* event register */ 39*a47a12beSStefan Roese u32 mask; /* mask register */ 40*a47a12beSStefan Roese u32 com; /* command register */ 41*a47a12beSStefan Roese u32 tx; /* transmit register */ 42*a47a12beSStefan Roese u32 rx; /* receive register */ 43*a47a12beSStefan Roese u8 res1[0xFC8]; /* fill up to 0x1000 */ 44*a47a12beSStefan Roese } spi8xxx_t; 45*a47a12beSStefan Roese 46*a47a12beSStefan Roese #endif 47*a47a12beSStefan Roese 48*a47a12beSStefan Roese #endif /* _ASM_MPC8XXX_SPI_H_ */ 49