1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * Freescale non-CPM SPI Controller 3a47a12beSStefan Roese * 4a47a12beSStefan Roese * Copyright 2008 Qstreams Networks, Inc. 5a47a12beSStefan Roese * 6*5b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0 7a47a12beSStefan Roese */ 8a47a12beSStefan Roese 9a47a12beSStefan Roese #ifndef _ASM_MPC8XXX_SPI_H_ 10a47a12beSStefan Roese #define _ASM_MPC8XXX_SPI_H_ 11a47a12beSStefan Roese 12a47a12beSStefan Roese #include <asm/types.h> 13a47a12beSStefan Roese 147c619ddcSIlya Yanok #if defined(CONFIG_MPC8308) || \ 15a47a12beSStefan Roese defined(CONFIG_MPC8313) || \ 16a47a12beSStefan Roese defined(CONFIG_MPC8315) || \ 177c619ddcSIlya Yanok defined(CONFIG_MPC834x) || \ 18a47a12beSStefan Roese defined(CONFIG_MPC837x) 19a47a12beSStefan Roese 20a47a12beSStefan Roese typedef struct spi8xxx { 21a47a12beSStefan Roese u8 res0[0x20]; /* 0x0-0x01f reserved */ 22a47a12beSStefan Roese u32 mode; /* mode register */ 23a47a12beSStefan Roese u32 event; /* event register */ 24a47a12beSStefan Roese u32 mask; /* mask register */ 25a47a12beSStefan Roese u32 com; /* command register */ 26a47a12beSStefan Roese u32 tx; /* transmit register */ 27a47a12beSStefan Roese u32 rx; /* receive register */ 28a47a12beSStefan Roese u8 res1[0xFC8]; /* fill up to 0x1000 */ 29a47a12beSStefan Roese } spi8xxx_t; 30a47a12beSStefan Roese 31a47a12beSStefan Roese #endif 32a47a12beSStefan Roese 33a47a12beSStefan Roese #endif /* _ASM_MPC8XXX_SPI_H_ */ 34