16ab4011bSKumar Gala /* 26ab4011bSKumar Gala * Copyright 2010 Freescale Semiconductor, Inc. 36ab4011bSKumar Gala * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 56ab4011bSKumar Gala */ 66ab4011bSKumar Gala 7a47a12beSStefan Roese #ifndef __FSL_SERDES_H 8a47a12beSStefan Roese #define __FSL_SERDES_H 9a47a12beSStefan Roese 10a47a12beSStefan Roese #include <config.h> 11a47a12beSStefan Roese 126ab4011bSKumar Gala enum srds_prtcl { 136ab4011bSKumar Gala NONE = 0, 146ab4011bSKumar Gala PCIE1, 156ab4011bSKumar Gala PCIE2, 166ab4011bSKumar Gala PCIE3, 176ab4011bSKumar Gala PCIE4, 186ab4011bSKumar Gala SATA1, 196ab4011bSKumar Gala SATA2, 206ab4011bSKumar Gala SRIO1, 216ab4011bSKumar Gala SRIO2, 2234a8258fSKumar Gala SGMII_FM1_DTSEC1, 2334a8258fSKumar Gala SGMII_FM1_DTSEC2, 2434a8258fSKumar Gala SGMII_FM1_DTSEC3, 2534a8258fSKumar Gala SGMII_FM1_DTSEC4, 2634a8258fSKumar Gala SGMII_FM1_DTSEC5, 27d1001e3fSYork Sun SGMII_FM1_DTSEC6, 28d1001e3fSYork Sun SGMII_FM1_DTSEC9, 29d1001e3fSYork Sun SGMII_FM1_DTSEC10, 3034a8258fSKumar Gala SGMII_FM2_DTSEC1, 3134a8258fSKumar Gala SGMII_FM2_DTSEC2, 3234a8258fSKumar Gala SGMII_FM2_DTSEC3, 3334a8258fSKumar Gala SGMII_FM2_DTSEC4, 3499abf7deSTimur Tabi SGMII_FM2_DTSEC5, 35d1001e3fSYork Sun SGMII_FM2_DTSEC6, 36d1001e3fSYork Sun SGMII_FM2_DTSEC9, 37d1001e3fSYork Sun SGMII_FM2_DTSEC10, 386ab4011bSKumar Gala SGMII_TSEC1, 396ab4011bSKumar Gala SGMII_TSEC2, 406ab4011bSKumar Gala SGMII_TSEC3, 416ab4011bSKumar Gala SGMII_TSEC4, 426ab4011bSKumar Gala XAUI_FM1, 436ab4011bSKumar Gala XAUI_FM2, 446ab4011bSKumar Gala AURORA, 45d1001e3fSYork Sun CPRI1, 46d1001e3fSYork Sun CPRI2, 47d1001e3fSYork Sun CPRI3, 48d1001e3fSYork Sun CPRI4, 49d1001e3fSYork Sun CPRI5, 50d1001e3fSYork Sun CPRI6, 51d1001e3fSYork Sun CPRI7, 52d1001e3fSYork Sun CPRI8, 53d1001e3fSYork Sun XAUI_FM1_MAC9, 54d1001e3fSYork Sun XAUI_FM1_MAC10, 55d1001e3fSYork Sun XAUI_FM2_MAC9, 56d1001e3fSYork Sun XAUI_FM2_MAC10, 57d1001e3fSYork Sun HIGIG_FM1_MAC9, 58d1001e3fSYork Sun HIGIG_FM1_MAC10, 59d1001e3fSYork Sun HIGIG_FM2_MAC9, 60d1001e3fSYork Sun HIGIG_FM2_MAC10, 61d1001e3fSYork Sun QSGMII_FM1_A, /* A indicates MACs 1-4 */ 62d1001e3fSYork Sun QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ 63d1001e3fSYork Sun QSGMII_FM2_A, 64d1001e3fSYork Sun QSGMII_FM2_B, 65*82a55c1eSShengzhou Liu XFI_FM1_MAC1, 66*82a55c1eSShengzhou Liu XFI_FM1_MAC2, 67d1001e3fSYork Sun XFI_FM1_MAC9, 68d1001e3fSYork Sun XFI_FM1_MAC10, 69d1001e3fSYork Sun XFI_FM2_MAC9, 70d1001e3fSYork Sun XFI_FM2_MAC10, 71d1001e3fSYork Sun INTERLAKEN, 725f208d11SYork Sun SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */ 735f208d11SYork Sun SGMII_SW1_DTSEC2, 745f208d11SYork Sun SGMII_SW1_DTSEC3, 755f208d11SYork Sun SGMII_SW1_DTSEC4, 765f208d11SYork Sun SGMII_SW1_DTSEC5, 775f208d11SYork Sun SGMII_SW1_DTSEC6, 785f208d11SYork Sun QSGMII_SW1_A, /* SW indicates on L2 swtich */ 795f208d11SYork Sun QSGMII_SW1_B, 80d1001e3fSYork Sun }; 81d1001e3fSYork Sun 82d1001e3fSYork Sun enum srds { 83d1001e3fSYork Sun FSL_SRDS_1 = 0, 84d1001e3fSYork Sun FSL_SRDS_2 = 1, 85d1001e3fSYork Sun FSL_SRDS_3 = 2, 86d1001e3fSYork Sun FSL_SRDS_4 = 3, 876ab4011bSKumar Gala }; 88a47a12beSStefan Roese 896ab4011bSKumar Gala int is_serdes_configured(enum srds_prtcl device); 90af025065SKumar Gala void fsl_serdes_init(void); 91935b402eSValentin Longchamp const char *serdes_clock_to_string(u32 clock); 92a47a12beSStefan Roese 933d28c5c8SEmil Medve #ifdef CONFIG_FSL_CORENET 94d1001e3fSYork Sun #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 95d1001e3fSYork Sun int serdes_get_first_lane(u32 sd, enum srds_prtcl device); 9640f398a4SShaveta Leekha enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); 97d1001e3fSYork Sun #else 983d28c5c8SEmil Medve int serdes_get_first_lane(enum srds_prtcl device); 99d1001e3fSYork Sun #endif 100df8af0b4SEmil Medve #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 101df8af0b4SEmil Medve void serdes_reset_rx(enum srds_prtcl device); 102df8af0b4SEmil Medve #endif 1033d28c5c8SEmil Medve #endif 1043d28c5c8SEmil Medve 105a47a12beSStefan Roese #endif /* __FSL_SERDES_H */ 106