16ab4011bSKumar Gala /* 26ab4011bSKumar Gala * Copyright 2010 Freescale Semiconductor, Inc. 36ab4011bSKumar Gala * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 56ab4011bSKumar Gala */ 66ab4011bSKumar Gala 7a47a12beSStefan Roese #ifndef __FSL_SERDES_H 8a47a12beSStefan Roese #define __FSL_SERDES_H 9a47a12beSStefan Roese 10a47a12beSStefan Roese #include <config.h> 11a47a12beSStefan Roese 126ab4011bSKumar Gala enum srds_prtcl { 13*71fe2225SHou Zhiqiang /* 14*71fe2225SHou Zhiqiang * Nobody will check whether the device 'NONE' has been configured, 15*71fe2225SHou Zhiqiang * So use it to indicate if the serdes_prtcl_map has been initialized. 16*71fe2225SHou Zhiqiang */ 176ab4011bSKumar Gala NONE = 0, 186ab4011bSKumar Gala PCIE1, 196ab4011bSKumar Gala PCIE2, 206ab4011bSKumar Gala PCIE3, 216ab4011bSKumar Gala PCIE4, 226ab4011bSKumar Gala SATA1, 236ab4011bSKumar Gala SATA2, 246ab4011bSKumar Gala SRIO1, 256ab4011bSKumar Gala SRIO2, 2634a8258fSKumar Gala SGMII_FM1_DTSEC1, 2734a8258fSKumar Gala SGMII_FM1_DTSEC2, 2834a8258fSKumar Gala SGMII_FM1_DTSEC3, 2934a8258fSKumar Gala SGMII_FM1_DTSEC4, 3034a8258fSKumar Gala SGMII_FM1_DTSEC5, 31d1001e3fSYork Sun SGMII_FM1_DTSEC6, 32d1001e3fSYork Sun SGMII_FM1_DTSEC9, 33d1001e3fSYork Sun SGMII_FM1_DTSEC10, 3434a8258fSKumar Gala SGMII_FM2_DTSEC1, 3534a8258fSKumar Gala SGMII_FM2_DTSEC2, 3634a8258fSKumar Gala SGMII_FM2_DTSEC3, 3734a8258fSKumar Gala SGMII_FM2_DTSEC4, 3899abf7deSTimur Tabi SGMII_FM2_DTSEC5, 39d1001e3fSYork Sun SGMII_FM2_DTSEC6, 40d1001e3fSYork Sun SGMII_FM2_DTSEC9, 41d1001e3fSYork Sun SGMII_FM2_DTSEC10, 426ab4011bSKumar Gala SGMII_TSEC1, 436ab4011bSKumar Gala SGMII_TSEC2, 446ab4011bSKumar Gala SGMII_TSEC3, 456ab4011bSKumar Gala SGMII_TSEC4, 466ab4011bSKumar Gala XAUI_FM1, 476ab4011bSKumar Gala XAUI_FM2, 486ab4011bSKumar Gala AURORA, 49d1001e3fSYork Sun CPRI1, 50d1001e3fSYork Sun CPRI2, 51d1001e3fSYork Sun CPRI3, 52d1001e3fSYork Sun CPRI4, 53d1001e3fSYork Sun CPRI5, 54d1001e3fSYork Sun CPRI6, 55d1001e3fSYork Sun CPRI7, 56d1001e3fSYork Sun CPRI8, 57d1001e3fSYork Sun XAUI_FM1_MAC9, 58d1001e3fSYork Sun XAUI_FM1_MAC10, 59d1001e3fSYork Sun XAUI_FM2_MAC9, 60d1001e3fSYork Sun XAUI_FM2_MAC10, 61d1001e3fSYork Sun HIGIG_FM1_MAC9, 62d1001e3fSYork Sun HIGIG_FM1_MAC10, 63d1001e3fSYork Sun HIGIG_FM2_MAC9, 64d1001e3fSYork Sun HIGIG_FM2_MAC10, 65d1001e3fSYork Sun QSGMII_FM1_A, /* A indicates MACs 1-4 */ 66d1001e3fSYork Sun QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ 67d1001e3fSYork Sun QSGMII_FM2_A, 68d1001e3fSYork Sun QSGMII_FM2_B, 6982a55c1eSShengzhou Liu XFI_FM1_MAC1, 7082a55c1eSShengzhou Liu XFI_FM1_MAC2, 71d1001e3fSYork Sun XFI_FM1_MAC9, 72d1001e3fSYork Sun XFI_FM1_MAC10, 73d1001e3fSYork Sun XFI_FM2_MAC9, 74d1001e3fSYork Sun XFI_FM2_MAC10, 75d1001e3fSYork Sun INTERLAKEN, 7696bda02cSPrabhakar Kushwaha QSGMII_SW1_A, /* Indicates ports on L2 Switch */ 775f208d11SYork Sun QSGMII_SW1_B, 78c35f8693SShengzhou Liu SGMII_2500_FM1_DTSEC1, 79c35f8693SShengzhou Liu SGMII_2500_FM1_DTSEC2, 80c35f8693SShengzhou Liu SGMII_2500_FM1_DTSEC3, 81c35f8693SShengzhou Liu SGMII_2500_FM1_DTSEC4, 82c35f8693SShengzhou Liu SGMII_2500_FM1_DTSEC5, 83c35f8693SShengzhou Liu SGMII_2500_FM1_DTSEC6, 84c35f8693SShengzhou Liu SGMII_2500_FM1_DTSEC9, 85c35f8693SShengzhou Liu SGMII_2500_FM1_DTSEC10, 86c35f8693SShengzhou Liu SGMII_2500_FM2_DTSEC1, 87c35f8693SShengzhou Liu SGMII_2500_FM2_DTSEC2, 88c35f8693SShengzhou Liu SGMII_2500_FM2_DTSEC3, 89c35f8693SShengzhou Liu SGMII_2500_FM2_DTSEC4, 90c35f8693SShengzhou Liu SGMII_2500_FM2_DTSEC5, 91c35f8693SShengzhou Liu SGMII_2500_FM2_DTSEC6, 92c35f8693SShengzhou Liu SGMII_2500_FM2_DTSEC9, 93c35f8693SShengzhou Liu SGMII_2500_FM2_DTSEC10, 94c2a61cd2SCodrin Ciubotariu SGMII_SW1_MAC1, 95c2a61cd2SCodrin Ciubotariu SGMII_SW1_MAC2, 96c2a61cd2SCodrin Ciubotariu SGMII_SW1_MAC3, 97c2a61cd2SCodrin Ciubotariu SGMII_SW1_MAC4, 98c2a61cd2SCodrin Ciubotariu SGMII_SW1_MAC5, 99c2a61cd2SCodrin Ciubotariu SGMII_SW1_MAC6, 1007d33a87dSCodrin Ciubotariu SERDES_PRCTL_COUNT /* Keep this item the last one */ 101d1001e3fSYork Sun }; 102d1001e3fSYork Sun 103d1001e3fSYork Sun enum srds { 104d1001e3fSYork Sun FSL_SRDS_1 = 0, 105d1001e3fSYork Sun FSL_SRDS_2 = 1, 106d1001e3fSYork Sun FSL_SRDS_3 = 2, 107d1001e3fSYork Sun FSL_SRDS_4 = 3, 1086ab4011bSKumar Gala }; 109a47a12beSStefan Roese 1106ab4011bSKumar Gala int is_serdes_configured(enum srds_prtcl device); 111af025065SKumar Gala void fsl_serdes_init(void); 112935b402eSValentin Longchamp const char *serdes_clock_to_string(u32 clock); 113a47a12beSStefan Roese 1143d28c5c8SEmil Medve #ifdef CONFIG_FSL_CORENET 115d1001e3fSYork Sun #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 116d1001e3fSYork Sun int serdes_get_first_lane(u32 sd, enum srds_prtcl device); 11740f398a4SShaveta Leekha enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); 118d1001e3fSYork Sun #else 1193d28c5c8SEmil Medve int serdes_get_first_lane(enum srds_prtcl device); 120d1001e3fSYork Sun #endif 121df8af0b4SEmil Medve #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 122df8af0b4SEmil Medve void serdes_reset_rx(enum srds_prtcl device); 123df8af0b4SEmil Medve #endif 1243d28c5c8SEmil Medve #endif 1253d28c5c8SEmil Medve 126a47a12beSStefan Roese #endif /* __FSL_SERDES_H */ 127