17065b7d4SRuchika Gupta /* 27065b7d4SRuchika Gupta * Copyright 2010-2011 Freescale Semiconductor, Inc. 37065b7d4SRuchika Gupta * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 57065b7d4SRuchika Gupta */ 67065b7d4SRuchika Gupta 77065b7d4SRuchika Gupta #ifndef __FSL_SECURE_BOOT_H 87065b7d4SRuchika Gupta #define __FSL_SECURE_BOOT_H 9e04916a7Sgaurav rana #include <asm/config_mpc85xx.h> 10e04916a7Sgaurav rana 11e04916a7Sgaurav rana #ifdef CONFIG_SECURE_BOOT 12e04916a7Sgaurav rana #define CONFIG_CMD_ESBC_VALIDATE 13e04916a7Sgaurav rana #define CONFIG_FSL_SEC_MON 14e04916a7Sgaurav rana #define CONFIG_SHA_PROG_HW_ACCEL 15e04916a7Sgaurav rana #define CONFIG_DM 16e04916a7Sgaurav rana #define CONFIG_RSA 17e04916a7Sgaurav rana #define CONFIG_RSA_FREESCALE_EXP 18e04916a7Sgaurav rana #ifndef CONFIG_FSL_CAAM 19e04916a7Sgaurav rana #define CONFIG_FSL_CAAM 20e04916a7Sgaurav rana #endif 21e04916a7Sgaurav rana #endif 227065b7d4SRuchika Gupta 230d2cff2dSPo Liu #ifdef CONFIG_SECURE_BOOT 247065b7d4SRuchika Gupta #if defined(CONFIG_FSL_CORENET) 257065b7d4SRuchika Gupta #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 26f978f7c2SAneesh Bansal #elif defined(CONFIG_BSC9132QDS) 27f978f7c2SAneesh Bansal #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 28b3f0f632SAneesh Bansal #elif defined(CONFIG_C29XPCIE) 29b3f0f632SAneesh Bansal #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 307065b7d4SRuchika Gupta #else 317065b7d4SRuchika Gupta #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 327065b7d4SRuchika Gupta #endif 337065b7d4SRuchika Gupta #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 347065b7d4SRuchika Gupta 35ca4819dfSAneesh Bansal #if defined(CONFIG_B4860QDS) || \ 36ca4819dfSAneesh Bansal defined(CONFIG_T4240QDS) || \ 372d8db6d3SAneesh Bansal defined(CONFIG_T2080QDS) || \ 38e47c2a68SAneesh Bansal defined(CONFIG_T2080RDB) || \ 392d8db6d3SAneesh Bansal defined(CONFIG_T1040QDS) || \ 40e622d9edSgaurav rana defined(CONFIG_T104xD4QDS) || \ 41f6050790SShengzhou Liu defined(CONFIG_T104xRDB) || \ 42e622d9edSgaurav rana defined(CONFIG_T104xD4RDB) || \ 43f6050790SShengzhou Liu defined(CONFIG_PPC_T1023) || \ 44f6050790SShengzhou Liu defined(CONFIG_PPC_T1024) 45fb4a2409SAneesh Bansal #define CONFIG_SYS_CPC_REINIT_F 46e04916a7Sgaurav rana #define CONFIG_KEY_REVOCATION 47fb4a2409SAneesh Bansal #undef CONFIG_SYS_INIT_L3_ADDR 48fb4a2409SAneesh Bansal #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 49fb4a2409SAneesh Bansal #endif 50fb4a2409SAneesh Bansal 51467a40dfSAneesh Bansal #if defined(CONFIG_RAMBOOT_PBL) 52467a40dfSAneesh Bansal #undef CONFIG_SYS_INIT_L3_ADDR 53467a40dfSAneesh Bansal #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 54467a40dfSAneesh Bansal #endif 55467a40dfSAneesh Bansal 56e04916a7Sgaurav rana #if defined(CONFIG_C29XPCIE) 57e04916a7Sgaurav rana #define CONFIG_KEY_REVOCATION 58e04916a7Sgaurav rana #endif 59e04916a7Sgaurav rana 60e04916a7Sgaurav rana #if defined(CONFIG_PPC_P3041) || \ 61e04916a7Sgaurav rana defined(CONFIG_PPC_P4080) || \ 62e04916a7Sgaurav rana defined(CONFIG_PPC_P5020) || \ 63e04916a7Sgaurav rana defined(CONFIG_PPC_P5040) || \ 64e04916a7Sgaurav rana defined(CONFIG_PPC_P2041) 65e04916a7Sgaurav rana #define CONFIG_FSL_TRUST_ARCH_v1 66e04916a7Sgaurav rana #endif 67e04916a7Sgaurav rana 68e04916a7Sgaurav rana #if defined(CONFIG_FSL_CORENET) 69e04916a7Sgaurav rana /* The key used for verification of next level images 70e04916a7Sgaurav rana * is picked up from an Extension Table which has 71e04916a7Sgaurav rana * been verified by the ISBC (Internal Secure boot Code) 72e04916a7Sgaurav rana * in boot ROM of the SoC 73e04916a7Sgaurav rana */ 74e04916a7Sgaurav rana #define CONFIG_FSL_ISBC_KEY_EXT 75e04916a7Sgaurav rana #endif 76e04916a7Sgaurav rana 7798cb0efdSgaurav rana #ifndef CONFIG_FIT_SIGNATURE 78*5050f6f0SAneesh Bansal /* If Boot Script is not on NOR and is required to be copied on RAM */ 79*5050f6f0SAneesh Bansal #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 80*5050f6f0SAneesh Bansal #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 81*5050f6f0SAneesh Bansal #define CONFIG_BS_HDR_ADDR_FLASH 0x00800000 82*5050f6f0SAneesh Bansal #define CONFIG_BS_HDR_SIZE 0x00002000 83*5050f6f0SAneesh Bansal #define CONFIG_BS_ADDR_RAM 0x00012000 84*5050f6f0SAneesh Bansal #define CONFIG_BS_ADDR_FLASH 0x00802000 85*5050f6f0SAneesh Bansal #define CONFIG_BS_SIZE 0x00001000 86*5050f6f0SAneesh Bansal 87*5050f6f0SAneesh Bansal #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 88*5050f6f0SAneesh Bansal #else 89*5050f6f0SAneesh Bansal 9098cb0efdSgaurav rana /* The bootscript header address is different for B4860 because the NOR 9198cb0efdSgaurav rana * mapping is different on B4 due to reduced NOR size. 9298cb0efdSgaurav rana */ 9398cb0efdSgaurav rana #if defined(CONFIG_B4860QDS) 9498cb0efdSgaurav rana #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 9598cb0efdSgaurav rana #elif defined(CONFIG_FSL_CORENET) 9698cb0efdSgaurav rana #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 9798cb0efdSgaurav rana #elif defined(CONFIG_BSC9132QDS) 9898cb0efdSgaurav rana #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 9998cb0efdSgaurav rana #elif defined(CONFIG_C29XPCIE) 10098cb0efdSgaurav rana #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 10198cb0efdSgaurav rana #else 10298cb0efdSgaurav rana #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 10398cb0efdSgaurav rana #endif 10498cb0efdSgaurav rana 105*5050f6f0SAneesh Bansal #endif 106*5050f6f0SAneesh Bansal 10798cb0efdSgaurav rana #include <config_fsl_secboot.h> 10898cb0efdSgaurav rana #endif 10998cb0efdSgaurav rana 1107065b7d4SRuchika Gupta #endif 1110d2cff2dSPo Liu #endif 112