1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 /* 13 * This macro should be removed when we no longer care about backwards 14 * compatibility with older operating systems. 15 */ 16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 17 18 #include <fsl_ddrc_version.h> 19 20 /* IP endianness */ 21 #define CONFIG_SYS_FSL_IFC_BE 22 #define CONFIG_SYS_FSL_SFP_BE 23 #define CONFIG_SYS_FSL_SEC_MON_BE 24 25 #if defined(CONFIG_ARCH_MPC8548) 26 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 27 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 28 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 29 #define CONFIG_SYS_FSL_RMU 30 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 31 32 #elif defined(CONFIG_ARCH_MPC8568) 33 #define QE_MURAM_SIZE 0x10000UL 34 #define MAX_QE_RISC 2 35 #define QE_NUM_OF_SNUM 28 36 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 37 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 38 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 39 #define CONFIG_SYS_FSL_RMU 40 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 41 42 #elif defined(CONFIG_ARCH_MPC8569) 43 #define QE_MURAM_SIZE 0x20000UL 44 #define MAX_QE_RISC 4 45 #define QE_NUM_OF_SNUM 46 46 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 47 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 48 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 49 #define CONFIG_SYS_FSL_RMU 50 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 51 52 #elif defined(CONFIG_ARCH_P1010) 53 #define CONFIG_FSL_SDHC_V2_3 54 #define CONFIG_TSECV2 55 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 56 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 57 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 58 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 59 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 60 #define CONFIG_ESDHC_HC_BLK_ADDR 61 62 /* P1011 is single core version of P1020 */ 63 #elif defined(CONFIG_ARCH_P1011) 64 #define CONFIG_TSECV2 65 #define CONFIG_FSL_PCIE_DISABLE_ASPM 66 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 67 68 #elif defined(CONFIG_ARCH_P1020) 69 #define CONFIG_TSECV2 70 #define CONFIG_FSL_PCIE_DISABLE_ASPM 71 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 72 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 73 #endif 74 75 #elif defined(CONFIG_ARCH_P1021) 76 #define CONFIG_TSECV2 77 #define CONFIG_FSL_PCIE_DISABLE_ASPM 78 #define QE_MURAM_SIZE 0x6000UL 79 #define MAX_QE_RISC 1 80 #define QE_NUM_OF_SNUM 28 81 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 82 83 #elif defined(CONFIG_ARCH_P1022) 84 #define CONFIG_TSECV2 85 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 86 87 #elif defined(CONFIG_ARCH_P1023) 88 #define CONFIG_SYS_NUM_FMAN 1 89 #define CONFIG_SYS_NUM_FM1_DTSEC 2 90 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 91 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 92 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 93 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 94 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 95 96 /* P1024 is lower end variant of P1020 */ 97 #elif defined(CONFIG_ARCH_P1024) 98 #define CONFIG_TSECV2 99 #define CONFIG_FSL_PCIE_DISABLE_ASPM 100 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 101 102 /* P1025 is lower end variant of P1021 */ 103 #elif defined(CONFIG_ARCH_P1025) 104 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 105 #define CONFIG_TSECV2 106 #define CONFIG_FSL_PCIE_DISABLE_ASPM 107 #define QE_MURAM_SIZE 0x6000UL 108 #define MAX_QE_RISC 1 109 #define QE_NUM_OF_SNUM 28 110 111 #elif defined(CONFIG_ARCH_P2020) 112 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 113 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 114 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 115 #define CONFIG_SYS_FSL_RMU 116 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 117 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 118 119 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ 120 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 121 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 122 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 123 #define CONFIG_SYS_NUM_FMAN 1 124 #define CONFIG_SYS_NUM_FM1_DTSEC 5 125 #define CONFIG_SYS_NUM_FM1_10GEC 1 126 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 127 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 128 #define CONFIG_SYS_FSL_TBCLK_DIV 32 129 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 130 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 131 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 132 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 133 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 134 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 135 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 136 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 137 138 #elif defined(CONFIG_ARCH_P3041) 139 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 140 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 141 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 142 #define CONFIG_SYS_NUM_FMAN 1 143 #define CONFIG_SYS_NUM_FM1_DTSEC 5 144 #define CONFIG_SYS_NUM_FM1_10GEC 1 145 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 146 #define CONFIG_SYS_FSL_TBCLK_DIV 32 147 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 148 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 149 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 150 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 151 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 152 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 153 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 154 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 155 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 156 157 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ 158 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 159 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 160 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 161 #define CONFIG_SYS_NUM_FMAN 2 162 #define CONFIG_SYS_NUM_FM1_DTSEC 4 163 #define CONFIG_SYS_NUM_FM2_DTSEC 4 164 #define CONFIG_SYS_NUM_FM1_10GEC 1 165 #define CONFIG_SYS_NUM_FM2_10GEC 1 166 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 167 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 168 #define CONFIG_SYS_FSL_TBCLK_DIV 16 169 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 170 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 171 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 172 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 173 #define CONFIG_SYS_FSL_RMU 174 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 175 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 176 177 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ 178 #define CONFIG_SYS_PPC64 /* 64-bit core */ 179 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 180 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 181 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 182 #define CONFIG_SYS_NUM_FMAN 1 183 #define CONFIG_SYS_NUM_FM1_DTSEC 5 184 #define CONFIG_SYS_NUM_FM1_10GEC 1 185 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 186 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 187 #define CONFIG_SYS_FSL_TBCLK_DIV 32 188 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 189 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 190 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 191 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 192 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 193 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 194 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 195 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 196 197 #elif defined(CONFIG_ARCH_P5040) 198 #define CONFIG_SYS_PPC64 199 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 200 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 201 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 202 #define CONFIG_SYS_NUM_FMAN 2 203 #define CONFIG_SYS_NUM_FM1_DTSEC 5 204 #define CONFIG_SYS_NUM_FM1_10GEC 1 205 #define CONFIG_SYS_NUM_FM2_DTSEC 5 206 #define CONFIG_SYS_NUM_FM2_10GEC 1 207 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 208 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 209 #define CONFIG_SYS_FSL_TBCLK_DIV 16 210 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 211 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 212 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 213 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 214 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 215 216 #elif defined(CONFIG_ARCH_BSC9131) 217 #define CONFIG_FSL_SDHC_V2_3 218 #define CONFIG_TSECV2 219 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 220 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 221 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 222 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 223 #define CONFIG_NAND_FSL_IFC 224 #define CONFIG_ESDHC_HC_BLK_ADDR 225 226 #elif defined(CONFIG_ARCH_BSC9132) 227 #define CONFIG_FSL_SDHC_V2_3 228 #define CONFIG_TSECV2 229 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 230 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 231 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 232 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 233 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 234 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 235 #define CONFIG_NAND_FSL_IFC 236 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 237 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 238 #define CONFIG_ESDHC_HC_BLK_ADDR 239 240 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) 241 #define CONFIG_E6500 242 #define CONFIG_SYS_PPC64 /* 64-bit core */ 243 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 244 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 245 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 246 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 247 #ifdef CONFIG_ARCH_T4240 248 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 249 #define CONFIG_SYS_NUM_FM1_DTSEC 8 250 #define CONFIG_SYS_NUM_FM1_10GEC 2 251 #define CONFIG_SYS_NUM_FM2_DTSEC 8 252 #define CONFIG_SYS_NUM_FM2_10GEC 2 253 #else 254 #define CONFIG_SYS_NUM_FM1_DTSEC 6 255 #define CONFIG_SYS_NUM_FM1_10GEC 1 256 #define CONFIG_SYS_NUM_FM2_DTSEC 8 257 #define CONFIG_SYS_NUM_FM2_10GEC 1 258 #if defined(CONFIG_ARCH_T4160) 259 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 260 #endif 261 #endif 262 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 263 #define CONFIG_SYS_FSL_SRDS_1 264 #define CONFIG_SYS_FSL_SRDS_2 265 #define CONFIG_SYS_FSL_SRDS_3 266 #define CONFIG_SYS_FSL_SRDS_4 267 #define CONFIG_SYS_NUM_FMAN 2 268 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 269 #define CONFIG_SYS_PME_CLK 0 270 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 271 #define CONFIG_SYS_FMAN_V3 272 #define CONFIG_SYS_FM1_CLK 3 273 #define CONFIG_SYS_FM2_CLK 3 274 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 275 #define CONFIG_SYS_FSL_TBCLK_DIV 16 276 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 277 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 278 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 279 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 280 #define CONFIG_SYS_FSL_SRIO_LIODN 281 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 282 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 283 #define CONFIG_SYS_FSL_SFP_VER_3_0 284 #define CONFIG_SYS_FSL_PCI_VER_3_X 285 286 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) 287 #define CONFIG_E6500 288 #define CONFIG_SYS_PPC64 /* 64-bit core */ 289 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 290 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 291 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 292 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 293 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 294 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 295 #define CONFIG_SYS_FSL_SRDS_1 296 #define CONFIG_SYS_FSL_SRDS_2 297 #define CONFIG_SYS_MAPLE 298 #define CONFIG_SYS_CPRI 299 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 300 #define CONFIG_SYS_NUM_FMAN 1 301 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 302 #define CONFIG_SYS_FM1_CLK 0 303 #define CONFIG_SYS_CPRI_CLK 3 304 #define CONFIG_SYS_ULB_CLK 4 305 #define CONFIG_SYS_ETVPE_CLK 1 306 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 307 #define CONFIG_SYS_FMAN_V3 308 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 309 #define CONFIG_SYS_FSL_TBCLK_DIV 16 310 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 311 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 312 #define CONFIG_SYS_FSL_SFP_VER_3_0 313 314 #ifdef CONFIG_ARCH_B4860 315 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 316 #define CONFIG_MAX_DSP_CPUS 12 317 #define CONFIG_NUM_DSP_CPUS 6 318 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 319 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 320 #define CONFIG_SYS_NUM_FM1_DTSEC 6 321 #define CONFIG_SYS_NUM_FM1_10GEC 2 322 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 323 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 324 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 325 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 326 #define CONFIG_SYS_FSL_SRIO_LIODN 327 #else 328 #define CONFIG_MAX_DSP_CPUS 2 329 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 330 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 331 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 332 #define CONFIG_SYS_NUM_FM1_DTSEC 4 333 #define CONFIG_SYS_NUM_FM1_10GEC 0 334 #endif 335 336 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) 337 #define CONFIG_E5500 338 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 339 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 340 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 341 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 342 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 343 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 344 #define CONFIG_SYS_FSL_SRDS_1 345 #define CONFIG_SYS_NUM_FMAN 1 346 #define CONFIG_SYS_NUM_FM1_DTSEC 5 347 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 348 #define CONFIG_PME_PLAT_CLK_DIV 2 349 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 350 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 351 #define CONFIG_SYS_FMAN_V3 352 #define CONFIG_FM_PLAT_CLK_DIV 1 353 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 354 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 355 per rcw field value */ 356 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 357 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 358 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 359 #define CONFIG_SYS_FSL_TBCLK_DIV 16 360 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 361 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 362 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 363 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 364 #define QE_MURAM_SIZE 0x6000UL 365 #define MAX_QE_RISC 1 366 #define QE_NUM_OF_SNUM 28 367 #define CONFIG_SYS_FSL_SFP_VER_3_0 368 369 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) 370 #define CONFIG_E5500 371 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 372 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 373 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 374 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 375 #define CONFIG_SYS_FMAN_V3 376 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 377 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 378 #define CONFIG_SYS_FSL_SRDS_1 379 #define CONFIG_SYS_NUM_FMAN 1 380 #define CONFIG_SYS_NUM_FM1_DTSEC 4 381 #define CONFIG_SYS_NUM_FM1_10GEC 1 382 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 383 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 384 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 385 #define CONFIG_SYS_FM1_CLK 0 386 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 387 per rcw field value */ 388 #define CONFIG_QBMAN_CLK_DIV 1 389 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 390 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 391 #define CONFIG_SYS_FSL_TBCLK_DIV 16 392 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 393 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 394 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 395 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 396 #define QE_MURAM_SIZE 0x6000UL 397 #define MAX_QE_RISC 1 398 #define QE_NUM_OF_SNUM 28 399 #define CONFIG_SYS_FSL_SFP_VER_3_0 400 401 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) 402 #define CONFIG_E6500 403 #define CONFIG_SYS_PPC64 /* 64-bit core */ 404 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 405 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 406 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 407 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 408 #define CONFIG_SYS_FSL_QMAN_V3 409 #define CONFIG_SYS_NUM_FMAN 1 410 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 411 #define CONFIG_SYS_FSL_SRDS_1 412 #define CONFIG_SYS_FSL_PCI_VER_3_X 413 #if defined(CONFIG_ARCH_T2080) 414 #define CONFIG_SYS_NUM_FM1_DTSEC 8 415 #define CONFIG_SYS_NUM_FM1_10GEC 4 416 #define CONFIG_SYS_FSL_SRDS_2 417 #define CONFIG_SYS_FSL_SRIO_LIODN 418 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 419 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 420 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 421 #elif defined(CONFIG_ARCH_T2081) 422 #define CONFIG_SYS_NUM_FM1_DTSEC 6 423 #define CONFIG_SYS_NUM_FM1_10GEC 2 424 #endif 425 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 426 #define CONFIG_PME_PLAT_CLK_DIV 1 427 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 428 #define CONFIG_SYS_FM1_CLK 0 429 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 430 per rcw field value */ 431 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 432 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 433 #define CONFIG_SYS_FMAN_V3 434 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 435 #define CONFIG_SYS_FSL_TBCLK_DIV 16 436 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 437 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 438 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 439 #define CONFIG_SYS_FSL_SFP_VER_3_0 440 #define CONFIG_SYS_FSL_ISBC_VER 2 441 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 442 #define CONFIG_SYS_FSL_SFP_VER_3_0 443 444 445 #elif defined(CONFIG_ARCH_C29X) 446 #define CONFIG_FSL_SDHC_V2_3 447 #define CONFIG_TSECV2_1 448 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 449 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 450 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 451 452 #endif 453 454 #ifdef CONFIG_E6500 455 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 456 #else 457 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 458 #endif 459 460 #if !defined(CONFIG_ARCH_C29X) 461 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 462 #endif 463 464 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 465