1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 /* Number of TLB CAM entries we have on FSL Book-E chips */ 27 #if defined(CONFIG_E500MC) 28 #define CONFIG_SYS_NUM_TLBCAMS 64 29 #elif defined(CONFIG_E500) 30 #define CONFIG_SYS_NUM_TLBCAMS 16 31 #endif 32 33 #if defined(CONFIG_MPC8536) 34 #define CONFIG_MAX_CPUS 1 35 #define CONFIG_SYS_FSL_NUM_LAWS 12 36 #define CONFIG_SYS_FSL_SEC_COMPAT 2 37 38 #elif defined(CONFIG_MPC8540) 39 #define CONFIG_MAX_CPUS 1 40 #define CONFIG_SYS_FSL_NUM_LAWS 8 41 42 #elif defined(CONFIG_MPC8541) 43 #define CONFIG_MAX_CPUS 1 44 #define CONFIG_SYS_FSL_NUM_LAWS 8 45 #define CONFIG_SYS_FSL_SEC_COMPAT 2 46 47 #elif defined(CONFIG_MPC8544) 48 #define CONFIG_MAX_CPUS 1 49 #define CONFIG_SYS_FSL_NUM_LAWS 10 50 #define CONFIG_SYS_FSL_SEC_COMPAT 2 51 52 #elif defined(CONFIG_MPC8548) 53 #define CONFIG_MAX_CPUS 1 54 #define CONFIG_SYS_FSL_NUM_LAWS 10 55 #define CONFIG_SYS_FSL_SEC_COMPAT 2 56 57 #elif defined(CONFIG_MPC8555) 58 #define CONFIG_MAX_CPUS 1 59 #define CONFIG_SYS_FSL_NUM_LAWS 8 60 #define CONFIG_SYS_FSL_SEC_COMPAT 2 61 62 #elif defined(CONFIG_MPC8560) 63 #define CONFIG_MAX_CPUS 1 64 #define CONFIG_SYS_FSL_NUM_LAWS 8 65 66 #elif defined(CONFIG_MPC8568) 67 #define CONFIG_MAX_CPUS 1 68 #define CONFIG_SYS_FSL_NUM_LAWS 10 69 #define CONFIG_SYS_FSL_SEC_COMPAT 2 70 71 #elif defined(CONFIG_MPC8569) 72 #define CONFIG_MAX_CPUS 1 73 #define CONFIG_SYS_FSL_NUM_LAWS 10 74 #define CONFIG_SYS_FSL_SEC_COMPAT 2 75 76 #elif defined(CONFIG_MPC8572) 77 #define CONFIG_MAX_CPUS 2 78 #define CONFIG_SYS_FSL_NUM_LAWS 12 79 #define CONFIG_SYS_FSL_SEC_COMPAT 2 80 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 81 82 #elif defined(CONFIG_P1010) 83 #define CONFIG_MAX_CPUS 1 84 #define CONFIG_SYS_FSL_NUM_LAWS 12 85 #define CONFIG_TSECV2 86 #define CONFIG_SYS_FSL_SEC_COMPAT 4 87 88 #elif defined(CONFIG_P1011) 89 #define CONFIG_MAX_CPUS 1 90 #define CONFIG_SYS_FSL_NUM_LAWS 12 91 #define CONFIG_TSECV2 92 #define CONFIG_SYS_FSL_SEC_COMPAT 2 93 94 #elif defined(CONFIG_P1012) 95 #define CONFIG_MAX_CPUS 1 96 #define CONFIG_SYS_FSL_NUM_LAWS 12 97 #define CONFIG_TSECV2 98 #define CONFIG_SYS_FSL_SEC_COMPAT 2 99 100 #elif defined(CONFIG_P1013) 101 #define CONFIG_MAX_CPUS 1 102 #define CONFIG_SYS_FSL_NUM_LAWS 12 103 #define CONFIG_TSECV2 104 #define CONFIG_SYS_FSL_SEC_COMPAT 2 105 106 #elif defined(CONFIG_P1014) 107 #define CONFIG_MAX_CPUS 1 108 #define CONFIG_SYS_FSL_NUM_LAWS 12 109 #define CONFIG_TSECV2 110 #define CONFIG_SYS_FSL_SEC_COMPAT 4 111 112 #elif defined(CONFIG_P1020) 113 #define CONFIG_MAX_CPUS 2 114 #define CONFIG_SYS_FSL_NUM_LAWS 12 115 #define CONFIG_TSECV2 116 #define CONFIG_SYS_FSL_SEC_COMPAT 2 117 118 #elif defined(CONFIG_P1021) 119 #define CONFIG_MAX_CPUS 2 120 #define CONFIG_SYS_FSL_NUM_LAWS 12 121 #define CONFIG_TSECV2 122 #define CONFIG_SYS_FSL_SEC_COMPAT 2 123 124 #elif defined(CONFIG_P1022) 125 #define CONFIG_MAX_CPUS 2 126 #define CONFIG_SYS_FSL_NUM_LAWS 12 127 #define CONFIG_TSECV2 128 #define CONFIG_SYS_FSL_SEC_COMPAT 2 129 130 #elif defined(CONFIG_P2010) 131 #define CONFIG_MAX_CPUS 1 132 #define CONFIG_SYS_FSL_NUM_LAWS 12 133 #define CONFIG_SYS_FSL_SEC_COMPAT 2 134 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 135 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 136 137 #elif defined(CONFIG_P2020) 138 #define CONFIG_MAX_CPUS 2 139 #define CONFIG_SYS_FSL_NUM_LAWS 12 140 #define CONFIG_SYS_FSL_SEC_COMPAT 2 141 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 142 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 143 144 #elif defined(CONFIG_PPC_P2040) 145 #define CONFIG_MAX_CPUS 4 146 #define CONFIG_SYS_FSL_NUM_LAWS 32 147 #define CONFIG_SYS_FSL_SEC_COMPAT 4 148 149 #elif defined(CONFIG_PPC_P3041) 150 #define CONFIG_MAX_CPUS 4 151 #define CONFIG_SYS_FSL_NUM_LAWS 32 152 #define CONFIG_SYS_FSL_SEC_COMPAT 4 153 154 #elif defined(CONFIG_PPC_P4040) 155 #define CONFIG_MAX_CPUS 4 156 #define CONFIG_SYS_FSL_NUM_LAWS 32 157 #define CONFIG_SYS_FSL_SEC_COMPAT 4 158 159 #elif defined(CONFIG_PPC_P4080) 160 #define CONFIG_MAX_CPUS 8 161 #define CONFIG_SYS_FSL_NUM_LAWS 32 162 #define CONFIG_SYS_FSL_SEC_COMPAT 4 163 #define CONFIG_SYS_NUM_FMAN 2 164 #define CONFIG_SYS_NUM_FM1_DTSEC 4 165 #define CONFIG_SYS_NUM_FM2_DTSEC 4 166 #define CONFIG_SYS_NUM_FM1_10GEC 1 167 #define CONFIG_SYS_NUM_FM2_10GEC 1 168 #define CONFIG_NUM_DDR_CONTROLLERS 2 169 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 170 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 171 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 172 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 173 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 174 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 175 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 176 #define CONFIG_SYS_P4080_ERRATUM_CPU22 177 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 178 179 #elif defined(CONFIG_PPC_P5010) 180 #define CONFIG_MAX_CPUS 1 181 #define CONFIG_SYS_FSL_NUM_LAWS 32 182 #define CONFIG_SYS_FSL_SEC_COMPAT 4 183 184 #elif defined(CONFIG_PPC_P5020) 185 #define CONFIG_MAX_CPUS 2 186 #define CONFIG_SYS_FSL_NUM_LAWS 32 187 #define CONFIG_SYS_FSL_SEC_COMPAT 4 188 189 #else 190 #error Processor type not defined for this platform 191 #endif 192 193 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 194