1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 /* 13 * This macro should be removed when we no longer care about backwards 14 * compatibility with older operating systems. 15 */ 16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 17 18 #include <fsl_ddrc_version.h> 19 20 /* IP endianness */ 21 #define CONFIG_SYS_FSL_IFC_BE 22 #define CONFIG_SYS_FSL_SFP_BE 23 #define CONFIG_SYS_FSL_SEC_MON_BE 24 25 #if defined(CONFIG_ARCH_MPC8536) 26 #define CONFIG_SYS_FSL_ERRATUM_A004508 27 #define CONFIG_SYS_FSL_ERRATUM_A005125 28 29 #elif defined(CONFIG_ARCH_MPC8540) 30 31 #elif defined(CONFIG_ARCH_MPC8541) 32 33 #elif defined(CONFIG_ARCH_MPC8544) 34 #define CONFIG_SYS_FSL_ERRATUM_A005125 35 36 #elif defined(CONFIG_ARCH_MPC8548) 37 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 38 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 39 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 40 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 41 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 42 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 43 #define CONFIG_SYS_FSL_RMU 44 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 45 #define CONFIG_SYS_FSL_ERRATUM_A005125 46 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 47 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 48 49 #elif defined(CONFIG_ARCH_MPC8555) 50 51 #elif defined(CONFIG_ARCH_MPC8560) 52 53 #elif defined(CONFIG_ARCH_MPC8568) 54 #define QE_MURAM_SIZE 0x10000UL 55 #define MAX_QE_RISC 2 56 #define QE_NUM_OF_SNUM 28 57 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 58 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 59 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 60 #define CONFIG_SYS_FSL_RMU 61 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 62 63 #elif defined(CONFIG_ARCH_MPC8569) 64 #define QE_MURAM_SIZE 0x20000UL 65 #define MAX_QE_RISC 4 66 #define QE_NUM_OF_SNUM 46 67 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 68 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 69 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 70 #define CONFIG_SYS_FSL_RMU 71 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 72 #define CONFIG_SYS_FSL_ERRATUM_A004508 73 #define CONFIG_SYS_FSL_ERRATUM_A005125 74 75 #elif defined(CONFIG_ARCH_MPC8572) 76 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 77 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 78 #define CONFIG_SYS_FSL_ERRATUM_A004508 79 #define CONFIG_SYS_FSL_ERRATUM_A005125 80 81 #elif defined(CONFIG_ARCH_P1010) 82 #define CONFIG_FSL_SDHC_V2_3 83 #define CONFIG_TSECV2 84 #define CONFIG_NUM_DDR_CONTROLLERS 1 85 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 86 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 87 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 88 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 89 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 90 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 91 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 92 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 93 #define CONFIG_SYS_FSL_ERRATUM_A005125 94 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 95 #define CONFIG_SYS_FSL_ERRATUM_A004508 96 #define CONFIG_SYS_FSL_ERRATUM_A007075 97 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 98 #define CONFIG_SYS_FSL_ERRATUM_A006261 99 #define CONFIG_SYS_FSL_ERRATUM_A004477 100 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 101 #define CONFIG_ESDHC_HC_BLK_ADDR 102 103 /* P1011 is single core version of P1020 */ 104 #elif defined(CONFIG_ARCH_P1011) 105 #define CONFIG_TSECV2 106 #define CONFIG_FSL_PCIE_DISABLE_ASPM 107 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 108 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 109 #define CONFIG_SYS_FSL_ERRATUM_A004508 110 #define CONFIG_SYS_FSL_ERRATUM_A005125 111 112 #elif defined(CONFIG_ARCH_P1020) 113 #define CONFIG_TSECV2 114 #define CONFIG_FSL_PCIE_DISABLE_ASPM 115 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 116 #define CONFIG_SYS_FSL_ERRATUM_A004508 117 #define CONFIG_SYS_FSL_ERRATUM_A005125 118 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 119 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 120 #endif 121 122 #elif defined(CONFIG_ARCH_P1021) 123 #define CONFIG_TSECV2 124 #define CONFIG_FSL_PCIE_DISABLE_ASPM 125 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 126 #define QE_MURAM_SIZE 0x6000UL 127 #define MAX_QE_RISC 1 128 #define QE_NUM_OF_SNUM 28 129 #define CONFIG_SYS_FSL_ERRATUM_A004508 130 #define CONFIG_SYS_FSL_ERRATUM_A005125 131 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 132 133 #elif defined(CONFIG_ARCH_P1022) 134 #define CONFIG_TSECV2 135 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 136 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 137 #define CONFIG_FSL_SATA_ERRATUM_A001 138 #define CONFIG_SYS_FSL_ERRATUM_A004508 139 #define CONFIG_SYS_FSL_ERRATUM_A005125 140 #define CONFIG_SYS_FSL_ERRATUM_A004477 141 142 #elif defined(CONFIG_ARCH_P1023) 143 #define CONFIG_SYS_NUM_FMAN 1 144 #define CONFIG_SYS_NUM_FM1_DTSEC 2 145 #define CONFIG_NUM_DDR_CONTROLLERS 1 146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 147 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 148 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 149 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 150 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 151 #define CONFIG_SYS_FSL_ERRATUM_A004508 152 #define CONFIG_SYS_FSL_ERRATUM_A005125 153 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 154 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 155 156 /* P1024 is lower end variant of P1020 */ 157 #elif defined(CONFIG_ARCH_P1024) 158 #define CONFIG_TSECV2 159 #define CONFIG_FSL_PCIE_DISABLE_ASPM 160 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 161 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 162 #define CONFIG_SYS_FSL_ERRATUM_A004508 163 #define CONFIG_SYS_FSL_ERRATUM_A005125 164 165 /* P1025 is lower end variant of P1021 */ 166 #elif defined(CONFIG_ARCH_P1025) 167 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 168 #define CONFIG_TSECV2 169 #define CONFIG_FSL_PCIE_DISABLE_ASPM 170 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 171 #define QE_MURAM_SIZE 0x6000UL 172 #define MAX_QE_RISC 1 173 #define QE_NUM_OF_SNUM 28 174 #define CONFIG_SYS_FSL_ERRATUM_A004508 175 #define CONFIG_SYS_FSL_ERRATUM_A005125 176 177 #elif defined(CONFIG_ARCH_P2020) 178 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 179 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 180 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 181 #define CONFIG_SYS_FSL_RMU 182 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 183 #define CONFIG_SYS_FSL_ERRATUM_A004508 184 #define CONFIG_SYS_FSL_ERRATUM_A005125 185 #define CONFIG_SYS_FSL_ERRATUM_A004477 186 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 187 188 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ 189 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 190 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 191 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 192 #define CONFIG_SYS_NUM_FMAN 1 193 #define CONFIG_SYS_NUM_FM1_DTSEC 5 194 #define CONFIG_SYS_NUM_FM1_10GEC 1 195 #define CONFIG_NUM_DDR_CONTROLLERS 1 196 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 197 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 198 #define CONFIG_SYS_FSL_TBCLK_DIV 32 199 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 200 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 201 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 202 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 203 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 204 #define CONFIG_SYS_FSL_ERRATUM_USB14 205 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 206 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 207 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 208 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 209 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 210 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 211 #define CONFIG_SYS_FSL_ERRATUM_A004510 212 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 213 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 214 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 215 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 216 #define CONFIG_SYS_FSL_ERRATUM_A004849 217 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 218 #define CONFIG_SYS_FSL_ERRATUM_A006261 219 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 220 221 #elif defined(CONFIG_ARCH_P3041) 222 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 223 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 224 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 225 #define CONFIG_SYS_NUM_FMAN 1 226 #define CONFIG_SYS_NUM_FM1_DTSEC 5 227 #define CONFIG_SYS_NUM_FM1_10GEC 1 228 #define CONFIG_NUM_DDR_CONTROLLERS 1 229 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 230 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 231 #define CONFIG_SYS_FSL_TBCLK_DIV 32 232 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 233 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 234 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 235 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 236 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 237 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 238 #define CONFIG_SYS_FSL_ERRATUM_USB14 239 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 240 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 241 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 242 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 243 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 244 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 245 #define CONFIG_SYS_FSL_ERRATUM_A004510 246 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 247 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 248 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 249 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 250 #define CONFIG_SYS_FSL_ERRATUM_A004849 251 #define CONFIG_SYS_FSL_ERRATUM_A005812 252 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 253 #define CONFIG_SYS_FSL_ERRATUM_A006261 254 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 255 256 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ 257 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 258 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 259 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 260 #define CONFIG_SYS_NUM_FMAN 2 261 #define CONFIG_SYS_NUM_FM1_DTSEC 4 262 #define CONFIG_SYS_NUM_FM2_DTSEC 4 263 #define CONFIG_SYS_NUM_FM1_10GEC 1 264 #define CONFIG_SYS_NUM_FM2_10GEC 1 265 #define CONFIG_NUM_DDR_CONTROLLERS 2 266 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 267 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 268 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 269 #define CONFIG_SYS_FSL_TBCLK_DIV 16 270 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 271 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 272 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 273 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 274 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 275 #define CONFIG_SYS_P4080_ERRATUM_CPU22 276 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 277 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 278 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 279 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 280 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 281 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 282 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 283 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 284 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 285 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 286 #define CONFIG_SYS_FSL_RMU 287 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 288 #define CONFIG_SYS_FSL_ERRATUM_A004510 289 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 290 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 291 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 292 #define CONFIG_SYS_FSL_ERRATUM_A004849 293 #define CONFIG_SYS_FSL_ERRATUM_A004580 294 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 295 #define CONFIG_SYS_FSL_ERRATUM_A005812 296 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 297 #define CONFIG_SYS_FSL_ERRATUM_A007075 298 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 299 300 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ 301 #define CONFIG_SYS_PPC64 /* 64-bit core */ 302 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 303 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 304 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 305 #define CONFIG_SYS_NUM_FMAN 1 306 #define CONFIG_SYS_NUM_FM1_DTSEC 5 307 #define CONFIG_SYS_NUM_FM1_10GEC 1 308 #define CONFIG_NUM_DDR_CONTROLLERS 2 309 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 310 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 311 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 312 #define CONFIG_SYS_FSL_TBCLK_DIV 32 313 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 314 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 315 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 316 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 317 #define CONFIG_SYS_FSL_ERRATUM_USB14 318 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 319 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 320 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 321 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 322 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 323 #define CONFIG_SYS_FSL_ERRATUM_A004510 324 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 325 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 326 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 327 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 328 #define CONFIG_SYS_FSL_ERRATUM_A006261 329 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 330 331 #elif defined(CONFIG_ARCH_P5040) 332 #define CONFIG_SYS_PPC64 333 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 334 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 335 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 336 #define CONFIG_SYS_NUM_FMAN 2 337 #define CONFIG_SYS_NUM_FM1_DTSEC 5 338 #define CONFIG_SYS_NUM_FM1_10GEC 1 339 #define CONFIG_SYS_NUM_FM2_DTSEC 5 340 #define CONFIG_SYS_NUM_FM2_10GEC 1 341 #define CONFIG_NUM_DDR_CONTROLLERS 2 342 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 343 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 344 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 345 #define CONFIG_SYS_FSL_TBCLK_DIV 16 346 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 347 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 348 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 349 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 350 #define CONFIG_SYS_FSL_ERRATUM_USB14 351 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 352 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 353 #define CONFIG_SYS_FSL_ERRATUM_A004699 354 #define CONFIG_SYS_FSL_ERRATUM_A004510 355 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 356 #define CONFIG_SYS_FSL_ERRATUM_A006261 357 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 358 #define CONFIG_SYS_FSL_ERRATUM_A005812 359 360 #elif defined(CONFIG_ARCH_BSC9131) 361 #define CONFIG_FSL_SDHC_V2_3 362 #define CONFIG_TSECV2 363 #define CONFIG_NUM_DDR_CONTROLLERS 1 364 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 365 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 366 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 367 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 368 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 369 #define CONFIG_NAND_FSL_IFC 370 #define CONFIG_SYS_FSL_ERRATUM_A005125 371 #define CONFIG_SYS_FSL_ERRATUM_A004477 372 #define CONFIG_ESDHC_HC_BLK_ADDR 373 374 #elif defined(CONFIG_ARCH_BSC9132) 375 #define CONFIG_FSL_SDHC_V2_3 376 #define CONFIG_TSECV2 377 #define CONFIG_NUM_DDR_CONTROLLERS 2 378 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 379 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 380 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 381 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 382 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 383 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 384 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 385 #define CONFIG_NAND_FSL_IFC 386 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 387 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 388 #define CONFIG_SYS_FSL_ERRATUM_A005125 389 #define CONFIG_SYS_FSL_ERRATUM_A005434 390 #define CONFIG_SYS_FSL_ERRATUM_A004477 391 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 392 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 393 #define CONFIG_ESDHC_HC_BLK_ADDR 394 395 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) 396 #define CONFIG_E6500 397 #define CONFIG_SYS_PPC64 /* 64-bit core */ 398 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 399 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 400 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 401 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 402 #ifdef CONFIG_ARCH_T4240 403 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 404 #define CONFIG_SYS_NUM_FM1_DTSEC 8 405 #define CONFIG_SYS_NUM_FM1_10GEC 2 406 #define CONFIG_SYS_NUM_FM2_DTSEC 8 407 #define CONFIG_SYS_NUM_FM2_10GEC 2 408 #define CONFIG_NUM_DDR_CONTROLLERS 3 409 #define CONFIG_SYS_FSL_ERRATUM_A006261 410 #else 411 #define CONFIG_SYS_NUM_FM1_DTSEC 6 412 #define CONFIG_SYS_NUM_FM1_10GEC 1 413 #define CONFIG_SYS_NUM_FM2_DTSEC 8 414 #define CONFIG_SYS_NUM_FM2_10GEC 1 415 #define CONFIG_NUM_DDR_CONTROLLERS 2 416 #if defined(CONFIG_ARCH_T4160) 417 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 418 #endif 419 #endif 420 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 421 #define CONFIG_SYS_FSL_SRDS_1 422 #define CONFIG_SYS_FSL_SRDS_2 423 #define CONFIG_SYS_FSL_SRDS_3 424 #define CONFIG_SYS_FSL_SRDS_4 425 #define CONFIG_SYS_NUM_FMAN 2 426 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 427 #define CONFIG_SYS_PME_CLK 0 428 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 429 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 430 #define CONFIG_SYS_FMAN_V3 431 #define CONFIG_SYS_FM1_CLK 3 432 #define CONFIG_SYS_FM2_CLK 3 433 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 434 #define CONFIG_SYS_FSL_TBCLK_DIV 16 435 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 436 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 437 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 438 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 439 #define CONFIG_SYS_FSL_SRIO_LIODN 440 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 441 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 442 #define CONFIG_SYS_FSL_ERRATUM_A004468 443 #define CONFIG_SYS_FSL_ERRATUM_A005871 444 #define CONFIG_SYS_FSL_ERRATUM_A006379 445 #define CONFIG_SYS_FSL_ERRATUM_A007186 446 #define CONFIG_SYS_FSL_ERRATUM_A006593 447 #define CONFIG_SYS_FSL_ERRATUM_A007798 448 #define CONFIG_SYS_FSL_ERRATUM_A009942 449 #define CONFIG_SYS_FSL_SFP_VER_3_0 450 #define CONFIG_SYS_FSL_PCI_VER_3_X 451 452 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) 453 #define CONFIG_E6500 454 #define CONFIG_SYS_PPC64 /* 64-bit core */ 455 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 456 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 457 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 458 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 459 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 460 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 461 #define CONFIG_SYS_FSL_SRDS_1 462 #define CONFIG_SYS_FSL_SRDS_2 463 #define CONFIG_SYS_MAPLE 464 #define CONFIG_SYS_CPRI 465 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 466 #define CONFIG_SYS_NUM_FMAN 1 467 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 468 #define CONFIG_SYS_FM1_CLK 0 469 #define CONFIG_SYS_CPRI_CLK 3 470 #define CONFIG_SYS_ULB_CLK 4 471 #define CONFIG_SYS_ETVPE_CLK 1 472 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 473 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 474 #define CONFIG_SYS_FMAN_V3 475 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 476 #define CONFIG_SYS_FSL_TBCLK_DIV 16 477 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 478 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 479 #define CONFIG_SYS_FSL_ERRATUM_A005871 480 #define CONFIG_SYS_FSL_ERRATUM_A006379 481 #define CONFIG_SYS_FSL_ERRATUM_A007186 482 #define CONFIG_SYS_FSL_ERRATUM_A006593 483 #define CONFIG_SYS_FSL_ERRATUM_A007075 484 #define CONFIG_SYS_FSL_ERRATUM_A006475 485 #define CONFIG_SYS_FSL_ERRATUM_A006384 486 #define CONFIG_SYS_FSL_ERRATUM_A007212 487 #define CONFIG_SYS_FSL_ERRATUM_A004477 488 #define CONFIG_SYS_FSL_ERRATUM_A009942 489 #define CONFIG_SYS_FSL_SFP_VER_3_0 490 491 #ifdef CONFIG_ARCH_B4860 492 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 493 #define CONFIG_MAX_DSP_CPUS 12 494 #define CONFIG_NUM_DSP_CPUS 6 495 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 496 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 497 #define CONFIG_SYS_NUM_FM1_DTSEC 6 498 #define CONFIG_SYS_NUM_FM1_10GEC 2 499 #define CONFIG_NUM_DDR_CONTROLLERS 2 500 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 501 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 502 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 503 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 504 #define CONFIG_SYS_FSL_SRIO_LIODN 505 #else 506 #define CONFIG_MAX_DSP_CPUS 2 507 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 508 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 509 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 510 #define CONFIG_SYS_NUM_FM1_DTSEC 4 511 #define CONFIG_SYS_NUM_FM1_10GEC 0 512 #define CONFIG_NUM_DDR_CONTROLLERS 1 513 #endif 514 515 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) 516 #define CONFIG_E5500 517 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 518 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 519 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 520 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 521 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 522 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 523 #define CONFIG_SYS_FSL_SRDS_1 524 #define CONFIG_SYS_NUM_FMAN 1 525 #define CONFIG_SYS_NUM_FM1_DTSEC 5 526 #define CONFIG_NUM_DDR_CONTROLLERS 1 527 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 528 #define CONFIG_PME_PLAT_CLK_DIV 2 529 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 530 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 531 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 532 #define CONFIG_SYS_FSL_ERRATUM_A008044 533 #define CONFIG_SYS_FMAN_V3 534 #define CONFIG_FM_PLAT_CLK_DIV 1 535 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 536 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 537 per rcw field value */ 538 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 539 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 540 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 541 #define CONFIG_SYS_FSL_TBCLK_DIV 16 542 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 543 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 544 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 545 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 546 #define QE_MURAM_SIZE 0x6000UL 547 #define MAX_QE_RISC 1 548 #define QE_NUM_OF_SNUM 28 549 #define CONFIG_SYS_FSL_SFP_VER_3_0 550 #define CONFIG_SYS_FSL_ERRATUM_A008378 551 #define CONFIG_SYS_FSL_ERRATUM_A009663 552 #define CONFIG_SYS_FSL_ERRATUM_A009942 553 554 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) 555 #define CONFIG_E5500 556 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 557 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 558 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 559 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 560 #define CONFIG_SYS_FMAN_V3 561 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 562 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 563 #define CONFIG_SYS_FSL_SRDS_1 564 #define CONFIG_SYS_NUM_FMAN 1 565 #define CONFIG_SYS_NUM_FM1_DTSEC 4 566 #define CONFIG_SYS_NUM_FM1_10GEC 1 567 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 568 #define CONFIG_NUM_DDR_CONTROLLERS 1 569 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 570 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 571 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 572 #define CONFIG_SYS_FM1_CLK 0 573 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 574 per rcw field value */ 575 #define CONFIG_QBMAN_CLK_DIV 1 576 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 577 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 578 #define CONFIG_SYS_FSL_TBCLK_DIV 16 579 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 580 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 581 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 582 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 583 #define QE_MURAM_SIZE 0x6000UL 584 #define MAX_QE_RISC 1 585 #define QE_NUM_OF_SNUM 28 586 #define CONFIG_SYS_FSL_SFP_VER_3_0 587 #define CONFIG_SYS_FSL_ERRATUM_A008378 588 #define CONFIG_SYS_FSL_ERRATUM_A009663 589 #define CONFIG_SYS_FSL_ERRATUM_A009942 590 591 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) 592 #define CONFIG_E6500 593 #define CONFIG_SYS_PPC64 /* 64-bit core */ 594 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 595 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 596 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 597 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 598 #define CONFIG_SYS_FSL_QMAN_V3 599 #define CONFIG_SYS_NUM_FMAN 1 600 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 601 #define CONFIG_SYS_FSL_SRDS_1 602 #define CONFIG_SYS_FSL_PCI_VER_3_X 603 #if defined(CONFIG_ARCH_T2080) 604 #define CONFIG_SYS_NUM_FM1_DTSEC 8 605 #define CONFIG_SYS_NUM_FM1_10GEC 4 606 #define CONFIG_SYS_FSL_SRDS_2 607 #define CONFIG_SYS_FSL_SRIO_LIODN 608 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 609 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 610 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 611 #elif defined(CONFIG_ARCH_T2081) 612 #define CONFIG_SYS_NUM_FM1_DTSEC 6 613 #define CONFIG_SYS_NUM_FM1_10GEC 2 614 #endif 615 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 616 #define CONFIG_NUM_DDR_CONTROLLERS 1 617 #define CONFIG_PME_PLAT_CLK_DIV 1 618 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 619 #define CONFIG_SYS_FM1_CLK 0 620 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 621 per rcw field value */ 622 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 623 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 624 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 625 #define CONFIG_SYS_FMAN_V3 626 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 627 #define CONFIG_SYS_FSL_TBCLK_DIV 16 628 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 629 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 630 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 631 #define CONFIG_SYS_FSL_ERRATUM_A007212 632 #define CONFIG_SYS_FSL_SFP_VER_3_0 633 #define CONFIG_SYS_FSL_ISBC_VER 2 634 #define CONFIG_SYS_FSL_ERRATUM_A006593 635 #define CONFIG_SYS_FSL_ERRATUM_A007186 636 #define CONFIG_SYS_FSL_ERRATUM_A006379 637 #define CONFIG_SYS_FSL_ERRATUM_A009942 638 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 639 #define CONFIG_SYS_FSL_SFP_VER_3_0 640 641 642 #elif defined(CONFIG_ARCH_C29X) 643 #define CONFIG_FSL_SDHC_V2_3 644 #define CONFIG_TSECV2_1 645 #define CONFIG_NUM_DDR_CONTROLLERS 1 646 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 647 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 648 #define CONFIG_SYS_FSL_ERRATUM_A005125 649 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 650 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 651 652 #elif defined(CONFIG_ARCH_QEMU_E500) 653 654 #else 655 #error Processor type not defined for this platform 656 #endif 657 658 #ifdef CONFIG_E6500 659 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 660 #else 661 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 662 #endif 663 664 #if !defined(CONFIG_ARCH_C29X) 665 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 666 #endif 667 668 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 669