1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 28 #endif 29 30 /* Number of TLB CAM entries we have on FSL Book-E chips */ 31 #if defined(CONFIG_E500MC) 32 #define CONFIG_SYS_NUM_TLBCAMS 64 33 #elif defined(CONFIG_E500) 34 #define CONFIG_SYS_NUM_TLBCAMS 16 35 #endif 36 37 #if defined(CONFIG_MPC8536) 38 #define CONFIG_MAX_CPUS 1 39 #define CONFIG_SYS_FSL_NUM_LAWS 12 40 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 41 #define CONFIG_SYS_FSL_SEC_COMPAT 2 42 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 43 44 #elif defined(CONFIG_MPC8540) 45 #define CONFIG_MAX_CPUS 1 46 #define CONFIG_SYS_FSL_NUM_LAWS 8 47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 48 49 #elif defined(CONFIG_MPC8541) 50 #define CONFIG_MAX_CPUS 1 51 #define CONFIG_SYS_FSL_NUM_LAWS 8 52 #define CONFIG_SYS_FSL_SEC_COMPAT 2 53 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 54 55 #elif defined(CONFIG_MPC8544) 56 #define CONFIG_MAX_CPUS 1 57 #define CONFIG_SYS_FSL_NUM_LAWS 10 58 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 59 #define CONFIG_SYS_FSL_SEC_COMPAT 2 60 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 61 62 #elif defined(CONFIG_MPC8548) 63 #define CONFIG_MAX_CPUS 1 64 #define CONFIG_SYS_FSL_NUM_LAWS 10 65 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 66 #define CONFIG_SYS_FSL_SEC_COMPAT 2 67 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 68 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 69 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 70 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 71 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 72 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 73 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 74 #define CONFIG_SYS_FSL_RMU 75 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 76 77 #elif defined(CONFIG_MPC8555) 78 #define CONFIG_MAX_CPUS 1 79 #define CONFIG_SYS_FSL_NUM_LAWS 8 80 #define CONFIG_SYS_FSL_SEC_COMPAT 2 81 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 82 83 #elif defined(CONFIG_MPC8560) 84 #define CONFIG_MAX_CPUS 1 85 #define CONFIG_SYS_FSL_NUM_LAWS 8 86 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 87 88 #elif defined(CONFIG_MPC8568) 89 #define CONFIG_MAX_CPUS 1 90 #define CONFIG_SYS_FSL_NUM_LAWS 10 91 #define CONFIG_SYS_FSL_SEC_COMPAT 2 92 #define QE_MURAM_SIZE 0x10000UL 93 #define MAX_QE_RISC 2 94 #define QE_NUM_OF_SNUM 28 95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 96 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 97 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 98 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 99 #define CONFIG_SYS_FSL_RMU 100 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 101 102 #elif defined(CONFIG_MPC8569) 103 #define CONFIG_MAX_CPUS 1 104 #define CONFIG_SYS_FSL_NUM_LAWS 10 105 #define CONFIG_SYS_FSL_SEC_COMPAT 2 106 #define QE_MURAM_SIZE 0x20000UL 107 #define MAX_QE_RISC 4 108 #define QE_NUM_OF_SNUM 46 109 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 110 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 111 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 112 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 113 #define CONFIG_SYS_FSL_RMU 114 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 115 116 #elif defined(CONFIG_MPC8572) 117 #define CONFIG_MAX_CPUS 2 118 #define CONFIG_SYS_FSL_NUM_LAWS 12 119 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 120 #define CONFIG_SYS_FSL_SEC_COMPAT 2 121 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 122 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 123 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 124 125 #elif defined(CONFIG_P1010) 126 #define CONFIG_MAX_CPUS 1 127 #define CONFIG_FSL_SDHC_V2_3 128 #define CONFIG_SYS_FSL_NUM_LAWS 12 129 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 130 #define CONFIG_TSECV2 131 #define CONFIG_SYS_FSL_SEC_COMPAT 4 132 #define CONFIG_FSL_SATA_V2 133 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 134 #define CONFIG_NUM_DDR_CONTROLLERS 1 135 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 136 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 137 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 138 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 139 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 140 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 141 142 /* P1011 is single core version of P1020 */ 143 #elif defined(CONFIG_P1011) 144 #define CONFIG_MAX_CPUS 1 145 #define CONFIG_SYS_FSL_NUM_LAWS 12 146 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 147 #define CONFIG_TSECV2 148 #define CONFIG_FSL_PCIE_DISABLE_ASPM 149 #define CONFIG_SYS_FSL_SEC_COMPAT 2 150 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 151 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 152 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 153 154 /* P1012 is single core version of P1021 */ 155 #elif defined(CONFIG_P1012) 156 #define CONFIG_MAX_CPUS 1 157 #define CONFIG_SYS_FSL_NUM_LAWS 12 158 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 159 #define CONFIG_TSECV2 160 #define CONFIG_FSL_PCIE_DISABLE_ASPM 161 #define CONFIG_SYS_FSL_SEC_COMPAT 2 162 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 163 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 164 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 165 #define QE_MURAM_SIZE 0x6000UL 166 #define MAX_QE_RISC 1 167 #define QE_NUM_OF_SNUM 28 168 169 /* P1013 is single core version of P1022 */ 170 #elif defined(CONFIG_P1013) 171 #define CONFIG_MAX_CPUS 1 172 #define CONFIG_SYS_FSL_NUM_LAWS 12 173 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 174 #define CONFIG_TSECV2 175 #define CONFIG_SYS_FSL_SEC_COMPAT 2 176 #define CONFIG_FSL_SATA_V2 177 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 178 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 179 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 180 #define CONFIG_FSL_SATA_ERRATUM_A001 181 182 #elif defined(CONFIG_P1014) 183 #define CONFIG_MAX_CPUS 1 184 #define CONFIG_FSL_SDHC_V2_3 185 #define CONFIG_SYS_FSL_NUM_LAWS 12 186 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 187 #define CONFIG_TSECV2 188 #define CONFIG_SYS_FSL_SEC_COMPAT 4 189 #define CONFIG_FSL_SATA_V2 190 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 191 #define CONFIG_NUM_DDR_CONTROLLERS 1 192 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 193 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 194 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 195 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 196 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 197 198 /* P1017 is single core version of P1023 */ 199 #elif defined(CONFIG_P1017) 200 #define CONFIG_MAX_CPUS 1 201 #define CONFIG_SYS_FSL_NUM_LAWS 12 202 #define CONFIG_SYS_FSL_SEC_COMPAT 4 203 #define CONFIG_SYS_NUM_FMAN 1 204 #define CONFIG_SYS_NUM_FM1_DTSEC 2 205 #define CONFIG_NUM_DDR_CONTROLLERS 1 206 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 207 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 208 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 209 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 210 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 211 212 #elif defined(CONFIG_P1020) 213 #define CONFIG_MAX_CPUS 2 214 #define CONFIG_SYS_FSL_NUM_LAWS 12 215 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 216 #define CONFIG_TSECV2 217 #define CONFIG_FSL_PCIE_DISABLE_ASPM 218 #define CONFIG_SYS_FSL_SEC_COMPAT 2 219 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 220 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 221 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 222 223 #elif defined(CONFIG_P1021) 224 #define CONFIG_MAX_CPUS 2 225 #define CONFIG_SYS_FSL_NUM_LAWS 12 226 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 227 #define CONFIG_TSECV2 228 #define CONFIG_FSL_PCIE_DISABLE_ASPM 229 #define CONFIG_SYS_FSL_SEC_COMPAT 2 230 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 231 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 232 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 233 #define QE_MURAM_SIZE 0x6000UL 234 #define MAX_QE_RISC 1 235 #define QE_NUM_OF_SNUM 28 236 237 #elif defined(CONFIG_P1022) 238 #define CONFIG_MAX_CPUS 2 239 #define CONFIG_SYS_FSL_NUM_LAWS 12 240 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 241 #define CONFIG_TSECV2 242 #define CONFIG_SYS_FSL_SEC_COMPAT 2 243 #define CONFIG_FSL_SATA_V2 244 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 245 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 246 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 247 #define CONFIG_FSL_SATA_ERRATUM_A001 248 249 #elif defined(CONFIG_P1023) 250 #define CONFIG_MAX_CPUS 2 251 #define CONFIG_SYS_FSL_NUM_LAWS 12 252 #define CONFIG_SYS_FSL_SEC_COMPAT 4 253 #define CONFIG_SYS_NUM_FMAN 1 254 #define CONFIG_SYS_NUM_FM1_DTSEC 2 255 #define CONFIG_NUM_DDR_CONTROLLERS 1 256 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 257 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 258 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 259 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 260 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 261 262 /* P1024 is lower end variant of P1020 */ 263 #elif defined(CONFIG_P1024) 264 #define CONFIG_MAX_CPUS 2 265 #define CONFIG_SYS_FSL_NUM_LAWS 12 266 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 267 #define CONFIG_TSECV2 268 #define CONFIG_FSL_PCIE_DISABLE_ASPM 269 #define CONFIG_SYS_FSL_SEC_COMPAT 2 270 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 271 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 272 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 273 274 /* P1025 is lower end variant of P1021 */ 275 #elif defined(CONFIG_P1025) 276 #define CONFIG_MAX_CPUS 2 277 #define CONFIG_SYS_FSL_NUM_LAWS 12 278 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 279 #define CONFIG_TSECV2 280 #define CONFIG_FSL_PCIE_DISABLE_ASPM 281 #define CONFIG_SYS_FSL_SEC_COMPAT 2 282 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 283 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 284 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 285 #define QE_MURAM_SIZE 0x6000UL 286 #define MAX_QE_RISC 1 287 #define QE_NUM_OF_SNUM 28 288 289 /* P2010 is single core version of P2020 */ 290 #elif defined(CONFIG_P2010) 291 #define CONFIG_MAX_CPUS 1 292 #define CONFIG_SYS_FSL_NUM_LAWS 12 293 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 294 #define CONFIG_SYS_FSL_SEC_COMPAT 2 295 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 296 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 297 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 298 299 #elif defined(CONFIG_P2020) 300 #define CONFIG_MAX_CPUS 2 301 #define CONFIG_SYS_FSL_NUM_LAWS 12 302 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 303 #define CONFIG_SYS_FSL_SEC_COMPAT 2 304 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 305 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 306 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 307 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 308 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 309 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 310 #define CONFIG_SYS_FSL_RMU 311 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 312 313 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 314 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 315 #define CONFIG_MAX_CPUS 4 316 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 317 #define CONFIG_SYS_FSL_NUM_LAWS 32 318 #define CONFIG_SYS_FSL_SEC_COMPAT 4 319 #define CONFIG_FSL_SATA_V2 320 #define CONFIG_SYS_NUM_FMAN 1 321 #define CONFIG_SYS_NUM_FM1_DTSEC 5 322 #define CONFIG_SYS_NUM_FM1_10GEC 1 323 #define CONFIG_NUM_DDR_CONTROLLERS 1 324 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 325 #define CONFIG_SYS_FSL_TBCLK_DIV 32 326 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 327 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 328 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 329 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 330 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 331 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 332 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 333 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 334 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 335 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 336 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 337 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 338 #define CONFIG_SYS_FSL_ERRATUM_A004510 339 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 340 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 341 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 342 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 343 344 #elif defined(CONFIG_PPC_P3041) 345 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 346 #define CONFIG_MAX_CPUS 4 347 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 348 #define CONFIG_SYS_FSL_NUM_LAWS 32 349 #define CONFIG_SYS_FSL_SEC_COMPAT 4 350 #define CONFIG_FSL_SATA_V2 351 #define CONFIG_SYS_NUM_FMAN 1 352 #define CONFIG_SYS_NUM_FM1_DTSEC 5 353 #define CONFIG_SYS_NUM_FM1_10GEC 1 354 #define CONFIG_NUM_DDR_CONTROLLERS 1 355 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 356 #define CONFIG_SYS_FSL_TBCLK_DIV 32 357 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 358 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 359 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 360 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 361 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 362 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 363 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 364 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 365 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 366 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 367 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 368 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 369 #define CONFIG_SYS_FSL_ERRATUM_A004510 370 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 371 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 372 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 373 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 374 375 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 376 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 377 #define CONFIG_MAX_CPUS 8 378 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 379 #define CONFIG_SYS_FSL_NUM_LAWS 32 380 #define CONFIG_SYS_FSL_SEC_COMPAT 4 381 #define CONFIG_SYS_NUM_FMAN 2 382 #define CONFIG_SYS_NUM_FM1_DTSEC 4 383 #define CONFIG_SYS_NUM_FM2_DTSEC 4 384 #define CONFIG_SYS_NUM_FM1_10GEC 1 385 #define CONFIG_SYS_NUM_FM2_10GEC 1 386 #define CONFIG_NUM_DDR_CONTROLLERS 2 387 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 388 #define CONFIG_SYS_FSL_TBCLK_DIV 16 389 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 390 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 391 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 392 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 393 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 394 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 395 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 396 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 397 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 398 #define CONFIG_SYS_P4080_ERRATUM_CPU22 399 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 400 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 401 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 402 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 403 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 404 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 405 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 406 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 407 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 408 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 409 #define CONFIG_SYS_FSL_RMU 410 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 411 #define CONFIG_SYS_FSL_ERRATUM_A004510 412 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 413 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 414 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 415 416 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 417 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 418 #define CONFIG_MAX_CPUS 2 419 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 420 #define CONFIG_SYS_FSL_NUM_LAWS 32 421 #define CONFIG_SYS_FSL_SEC_COMPAT 4 422 #define CONFIG_FSL_SATA_V2 423 #define CONFIG_SYS_NUM_FMAN 1 424 #define CONFIG_SYS_NUM_FM1_DTSEC 5 425 #define CONFIG_SYS_NUM_FM1_10GEC 1 426 #define CONFIG_NUM_DDR_CONTROLLERS 2 427 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 428 #define CONFIG_SYS_FSL_TBCLK_DIV 32 429 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 430 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 431 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 432 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 433 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 434 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 435 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 436 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 437 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 438 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 439 #define CONFIG_SYS_FSL_ERRATUM_A004510 440 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 441 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 442 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 443 444 #elif defined(CONFIG_PPC_P5040) 445 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 446 #define CONFIG_MAX_CPUS 4 447 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 448 #define CONFIG_SYS_FSL_NUM_LAWS 32 449 #define CONFIG_SYS_FSL_SEC_COMPAT 4 450 #define CONFIG_SYS_NUM_FMAN 2 451 #define CONFIG_SYS_NUM_FM1_DTSEC 5 452 #define CONFIG_SYS_NUM_FM1_10GEC 1 453 #define CONFIG_SYS_NUM_FM2_DTSEC 5 454 #define CONFIG_SYS_NUM_FM2_10GEC 1 455 #define CONFIG_NUM_DDR_CONTROLLERS 2 456 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 457 #define CONFIG_SYS_FSL_TBCLK_DIV 16 458 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 459 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 460 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 461 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 462 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 463 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 464 #define CONFIG_SYS_FSL_ERRATUM_USB138 465 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 466 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 467 #define CONFIG_SYS_FSL_ERRATUM_A004699 468 #define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC 469 #define CONFIG_SYS_FSL_ERRATUM_A004510 470 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 471 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 472 473 #elif defined(CONFIG_BSC9131) 474 #define CONFIG_MAX_CPUS 1 475 #define CONFIG_FSL_SDHC_V2_3 476 #define CONFIG_SYS_FSL_NUM_LAWS 12 477 #define CONFIG_TSECV2 478 #define CONFIG_SYS_FSL_SEC_COMPAT 4 479 #define CONFIG_NUM_DDR_CONTROLLERS 1 480 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 481 #define CONFIG_NAND_FSL_IFC 482 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 483 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 484 485 #else 486 #error Processor type not defined for this platform 487 #endif 488 489 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 490 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 491 #endif 492 493 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 494