1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #define FSL_DDR_VER_4_7 47 23 24 /* Number of TLB CAM entries we have on FSL Book-E chips */ 25 #if defined(CONFIG_E500MC) 26 #define CONFIG_SYS_NUM_TLBCAMS 64 27 #elif defined(CONFIG_E500) 28 #define CONFIG_SYS_NUM_TLBCAMS 16 29 #endif 30 31 #if defined(CONFIG_MPC8536) 32 #define CONFIG_MAX_CPUS 1 33 #define CONFIG_SYS_FSL_NUM_LAWS 12 34 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 35 #define CONFIG_SYS_FSL_SEC_COMPAT 2 36 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 37 38 #elif defined(CONFIG_MPC8540) 39 #define CONFIG_MAX_CPUS 1 40 #define CONFIG_SYS_FSL_NUM_LAWS 8 41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 42 43 #elif defined(CONFIG_MPC8541) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_FSL_SEC_COMPAT 2 47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 48 49 #elif defined(CONFIG_MPC8544) 50 #define CONFIG_MAX_CPUS 1 51 #define CONFIG_SYS_FSL_NUM_LAWS 10 52 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 53 #define CONFIG_SYS_FSL_SEC_COMPAT 2 54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 55 56 #elif defined(CONFIG_MPC8548) 57 #define CONFIG_MAX_CPUS 1 58 #define CONFIG_SYS_FSL_NUM_LAWS 10 59 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 60 #define CONFIG_SYS_FSL_SEC_COMPAT 2 61 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 62 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 63 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 64 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 65 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 66 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 67 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 68 #define CONFIG_SYS_FSL_RMU 69 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 70 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 71 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 72 73 #elif defined(CONFIG_MPC8555) 74 #define CONFIG_MAX_CPUS 1 75 #define CONFIG_SYS_FSL_NUM_LAWS 8 76 #define CONFIG_SYS_FSL_SEC_COMPAT 2 77 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 78 79 #elif defined(CONFIG_MPC8560) 80 #define CONFIG_MAX_CPUS 1 81 #define CONFIG_SYS_FSL_NUM_LAWS 8 82 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 83 84 #elif defined(CONFIG_MPC8568) 85 #define CONFIG_MAX_CPUS 1 86 #define CONFIG_SYS_FSL_NUM_LAWS 10 87 #define CONFIG_SYS_FSL_SEC_COMPAT 2 88 #define QE_MURAM_SIZE 0x10000UL 89 #define MAX_QE_RISC 2 90 #define QE_NUM_OF_SNUM 28 91 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 92 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 93 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 94 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 95 #define CONFIG_SYS_FSL_RMU 96 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 97 98 #elif defined(CONFIG_MPC8569) 99 #define CONFIG_MAX_CPUS 1 100 #define CONFIG_SYS_FSL_NUM_LAWS 10 101 #define CONFIG_SYS_FSL_SEC_COMPAT 2 102 #define QE_MURAM_SIZE 0x20000UL 103 #define MAX_QE_RISC 4 104 #define QE_NUM_OF_SNUM 46 105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 109 #define CONFIG_SYS_FSL_RMU 110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 111 112 #elif defined(CONFIG_MPC8572) 113 #define CONFIG_MAX_CPUS 2 114 #define CONFIG_SYS_FSL_NUM_LAWS 12 115 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 116 #define CONFIG_SYS_FSL_SEC_COMPAT 2 117 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 118 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 119 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 120 121 #elif defined(CONFIG_P1010) 122 #define CONFIG_MAX_CPUS 1 123 #define CONFIG_FSL_SDHC_V2_3 124 #define CONFIG_SYS_FSL_NUM_LAWS 12 125 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 126 #define CONFIG_TSECV2 127 #define CONFIG_SYS_FSL_SEC_COMPAT 4 128 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 129 #define CONFIG_NUM_DDR_CONTROLLERS 1 130 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 131 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 132 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 133 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 134 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 135 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 136 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 137 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 138 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 139 140 /* P1011 is single core version of P1020 */ 141 #elif defined(CONFIG_P1011) 142 #define CONFIG_MAX_CPUS 1 143 #define CONFIG_SYS_FSL_NUM_LAWS 12 144 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 145 #define CONFIG_TSECV2 146 #define CONFIG_FSL_PCIE_DISABLE_ASPM 147 #define CONFIG_SYS_FSL_SEC_COMPAT 2 148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 149 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 151 152 /* P1012 is single core version of P1021 */ 153 #elif defined(CONFIG_P1012) 154 #define CONFIG_MAX_CPUS 1 155 #define CONFIG_SYS_FSL_NUM_LAWS 12 156 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 157 #define CONFIG_TSECV2 158 #define CONFIG_FSL_PCIE_DISABLE_ASPM 159 #define CONFIG_SYS_FSL_SEC_COMPAT 2 160 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 161 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 162 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 163 #define QE_MURAM_SIZE 0x6000UL 164 #define MAX_QE_RISC 1 165 #define QE_NUM_OF_SNUM 28 166 167 /* P1013 is single core version of P1022 */ 168 #elif defined(CONFIG_P1013) 169 #define CONFIG_MAX_CPUS 1 170 #define CONFIG_SYS_FSL_NUM_LAWS 12 171 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 172 #define CONFIG_TSECV2 173 #define CONFIG_SYS_FSL_SEC_COMPAT 2 174 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 175 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 176 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 177 #define CONFIG_FSL_SATA_ERRATUM_A001 178 179 #elif defined(CONFIG_P1014) 180 #define CONFIG_MAX_CPUS 1 181 #define CONFIG_FSL_SDHC_V2_3 182 #define CONFIG_SYS_FSL_NUM_LAWS 12 183 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 184 #define CONFIG_TSECV2 185 #define CONFIG_SYS_FSL_SEC_COMPAT 4 186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 187 #define CONFIG_NUM_DDR_CONTROLLERS 1 188 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 189 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 190 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 191 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 192 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 193 194 /* P1017 is single core version of P1023 */ 195 #elif defined(CONFIG_P1017) 196 #define CONFIG_MAX_CPUS 1 197 #define CONFIG_SYS_FSL_NUM_LAWS 12 198 #define CONFIG_SYS_FSL_SEC_COMPAT 4 199 #define CONFIG_SYS_NUM_FMAN 1 200 #define CONFIG_SYS_NUM_FM1_DTSEC 2 201 #define CONFIG_NUM_DDR_CONTROLLERS 1 202 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 203 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 204 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 205 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 206 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 207 208 #elif defined(CONFIG_P1020) 209 #define CONFIG_MAX_CPUS 2 210 #define CONFIG_SYS_FSL_NUM_LAWS 12 211 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 212 #define CONFIG_TSECV2 213 #define CONFIG_FSL_PCIE_DISABLE_ASPM 214 #define CONFIG_SYS_FSL_SEC_COMPAT 2 215 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 216 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 217 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 218 219 #elif defined(CONFIG_P1021) 220 #define CONFIG_MAX_CPUS 2 221 #define CONFIG_SYS_FSL_NUM_LAWS 12 222 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 223 #define CONFIG_TSECV2 224 #define CONFIG_FSL_PCIE_DISABLE_ASPM 225 #define CONFIG_SYS_FSL_SEC_COMPAT 2 226 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 227 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 228 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 229 #define QE_MURAM_SIZE 0x6000UL 230 #define MAX_QE_RISC 1 231 #define QE_NUM_OF_SNUM 28 232 233 #elif defined(CONFIG_P1022) 234 #define CONFIG_MAX_CPUS 2 235 #define CONFIG_SYS_FSL_NUM_LAWS 12 236 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 237 #define CONFIG_TSECV2 238 #define CONFIG_SYS_FSL_SEC_COMPAT 2 239 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 240 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 241 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 242 #define CONFIG_FSL_SATA_ERRATUM_A001 243 244 #elif defined(CONFIG_P1023) 245 #define CONFIG_MAX_CPUS 2 246 #define CONFIG_SYS_FSL_NUM_LAWS 12 247 #define CONFIG_SYS_FSL_SEC_COMPAT 4 248 #define CONFIG_SYS_NUM_FMAN 1 249 #define CONFIG_SYS_NUM_FM1_DTSEC 2 250 #define CONFIG_NUM_DDR_CONTROLLERS 1 251 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 252 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 253 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 254 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 255 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 256 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 257 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 258 259 /* P1024 is lower end variant of P1020 */ 260 #elif defined(CONFIG_P1024) 261 #define CONFIG_MAX_CPUS 2 262 #define CONFIG_SYS_FSL_NUM_LAWS 12 263 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 264 #define CONFIG_TSECV2 265 #define CONFIG_FSL_PCIE_DISABLE_ASPM 266 #define CONFIG_SYS_FSL_SEC_COMPAT 2 267 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 268 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 269 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 270 271 /* P1025 is lower end variant of P1021 */ 272 #elif defined(CONFIG_P1025) 273 #define CONFIG_MAX_CPUS 2 274 #define CONFIG_SYS_FSL_NUM_LAWS 12 275 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 276 #define CONFIG_TSECV2 277 #define CONFIG_FSL_PCIE_DISABLE_ASPM 278 #define CONFIG_SYS_FSL_SEC_COMPAT 2 279 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 280 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 281 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 282 #define QE_MURAM_SIZE 0x6000UL 283 #define MAX_QE_RISC 1 284 #define QE_NUM_OF_SNUM 28 285 286 /* P2010 is single core version of P2020 */ 287 #elif defined(CONFIG_P2010) 288 #define CONFIG_MAX_CPUS 1 289 #define CONFIG_SYS_FSL_NUM_LAWS 12 290 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 291 #define CONFIG_SYS_FSL_SEC_COMPAT 2 292 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 293 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 294 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 295 296 #elif defined(CONFIG_P2020) 297 #define CONFIG_MAX_CPUS 2 298 #define CONFIG_SYS_FSL_NUM_LAWS 12 299 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 300 #define CONFIG_SYS_FSL_SEC_COMPAT 2 301 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 302 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 303 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 304 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 305 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 306 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 307 #define CONFIG_SYS_FSL_RMU 308 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 309 310 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 311 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 312 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 313 #define CONFIG_MAX_CPUS 4 314 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 315 #define CONFIG_SYS_FSL_NUM_LAWS 32 316 #define CONFIG_SYS_FSL_SEC_COMPAT 4 317 #define CONFIG_SYS_NUM_FMAN 1 318 #define CONFIG_SYS_NUM_FM1_DTSEC 5 319 #define CONFIG_SYS_NUM_FM1_10GEC 1 320 #define CONFIG_NUM_DDR_CONTROLLERS 1 321 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 322 #define CONFIG_SYS_FSL_TBCLK_DIV 32 323 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 324 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 325 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 326 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 327 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 328 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 329 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 330 #define CONFIG_SYS_FSL_ERRATUM_USB14 331 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 332 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 333 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 334 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 335 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 336 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 337 #define CONFIG_SYS_FSL_ERRATUM_A004510 338 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 339 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 340 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 341 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 342 #define CONFIG_SYS_FSL_ERRATUM_A004849 343 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 344 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 345 346 #elif defined(CONFIG_PPC_P3041) 347 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 348 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 349 #define CONFIG_MAX_CPUS 4 350 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 351 #define CONFIG_SYS_FSL_NUM_LAWS 32 352 #define CONFIG_SYS_FSL_SEC_COMPAT 4 353 #define CONFIG_SYS_NUM_FMAN 1 354 #define CONFIG_SYS_NUM_FM1_DTSEC 5 355 #define CONFIG_SYS_NUM_FM1_10GEC 1 356 #define CONFIG_NUM_DDR_CONTROLLERS 1 357 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 358 #define CONFIG_SYS_FSL_TBCLK_DIV 32 359 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 360 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 361 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 362 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 363 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 364 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 365 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 366 #define CONFIG_SYS_FSL_ERRATUM_USB14 367 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 368 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 369 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 370 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 371 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 372 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 373 #define CONFIG_SYS_FSL_ERRATUM_A004510 374 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 375 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 376 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 377 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 378 #define CONFIG_SYS_FSL_ERRATUM_A004849 379 #define CONFIG_SYS_FSL_ERRATUM_A005812 380 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 381 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 382 383 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 384 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 385 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 386 #define CONFIG_MAX_CPUS 8 387 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 388 #define CONFIG_SYS_FSL_NUM_LAWS 32 389 #define CONFIG_SYS_FSL_SEC_COMPAT 4 390 #define CONFIG_SYS_NUM_FMAN 2 391 #define CONFIG_SYS_NUM_FM1_DTSEC 4 392 #define CONFIG_SYS_NUM_FM2_DTSEC 4 393 #define CONFIG_SYS_NUM_FM1_10GEC 1 394 #define CONFIG_SYS_NUM_FM2_10GEC 1 395 #define CONFIG_NUM_DDR_CONTROLLERS 2 396 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 397 #define CONFIG_SYS_FSL_TBCLK_DIV 16 398 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 399 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 400 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 401 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 402 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 403 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 404 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 405 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 406 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 407 #define CONFIG_SYS_P4080_ERRATUM_CPU22 408 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 409 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 410 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 411 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 412 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 413 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 414 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 415 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 416 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 417 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 418 #define CONFIG_SYS_FSL_RMU 419 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 420 #define CONFIG_SYS_FSL_ERRATUM_A004510 421 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 422 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 423 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 424 #define CONFIG_SYS_FSL_ERRATUM_A004849 425 #define CONFIG_SYS_FSL_ERRATUM_A004580 426 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 427 #define CONFIG_SYS_FSL_ERRATUM_A005812 428 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 429 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 430 431 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 432 #define CONFIG_SYS_PPC64 /* 64-bit core */ 433 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 434 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 435 #define CONFIG_MAX_CPUS 2 436 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 437 #define CONFIG_SYS_FSL_NUM_LAWS 32 438 #define CONFIG_SYS_FSL_SEC_COMPAT 4 439 #define CONFIG_SYS_NUM_FMAN 1 440 #define CONFIG_SYS_NUM_FM1_DTSEC 5 441 #define CONFIG_SYS_NUM_FM1_10GEC 1 442 #define CONFIG_NUM_DDR_CONTROLLERS 2 443 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 444 #define CONFIG_SYS_FSL_TBCLK_DIV 32 445 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 446 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 447 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 448 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 449 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 450 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 451 #define CONFIG_SYS_FSL_ERRATUM_USB14 452 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 453 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 454 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 455 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 456 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 457 #define CONFIG_SYS_FSL_ERRATUM_A004510 458 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 459 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 460 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 461 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 462 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 463 464 #elif defined(CONFIG_PPC_P5040) 465 #define CONFIG_SYS_PPC64 466 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 467 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 468 #define CONFIG_MAX_CPUS 4 469 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 470 #define CONFIG_SYS_FSL_NUM_LAWS 32 471 #define CONFIG_SYS_FSL_SEC_COMPAT 4 472 #define CONFIG_SYS_NUM_FMAN 2 473 #define CONFIG_SYS_NUM_FM1_DTSEC 5 474 #define CONFIG_SYS_NUM_FM1_10GEC 1 475 #define CONFIG_SYS_NUM_FM2_DTSEC 5 476 #define CONFIG_SYS_NUM_FM2_10GEC 1 477 #define CONFIG_NUM_DDR_CONTROLLERS 2 478 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 479 #define CONFIG_SYS_FSL_TBCLK_DIV 16 480 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 481 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 482 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 483 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 484 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 485 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 486 #define CONFIG_SYS_FSL_ERRATUM_USB14 487 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 488 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 489 #define CONFIG_SYS_FSL_ERRATUM_A004699 490 #define CONFIG_SYS_FSL_ERRATUM_A004510 491 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 492 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 493 #define CONFIG_SYS_FSL_ERRATUM_A005812 494 495 #elif defined(CONFIG_BSC9131) 496 #define CONFIG_MAX_CPUS 1 497 #define CONFIG_FSL_SDHC_V2_3 498 #define CONFIG_SYS_FSL_NUM_LAWS 12 499 #define CONFIG_TSECV2 500 #define CONFIG_SYS_FSL_SEC_COMPAT 4 501 #define CONFIG_NUM_DDR_CONTROLLERS 1 502 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 503 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 504 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 505 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 506 #define CONFIG_NAND_FSL_IFC 507 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 508 509 #elif defined(CONFIG_BSC9132) 510 #define CONFIG_MAX_CPUS 2 511 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 512 #define CONFIG_FSL_SDHC_V2_3 513 #define CONFIG_SYS_FSL_NUM_LAWS 12 514 #define CONFIG_TSECV2 515 #define CONFIG_SYS_FSL_SEC_COMPAT 4 516 #define CONFIG_NUM_DDR_CONTROLLERS 2 517 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 518 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 519 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 520 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 521 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 522 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 523 #define CONFIG_NAND_FSL_IFC 524 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 525 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 526 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 527 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 528 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 529 530 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 531 #define CONFIG_E6500 532 #define CONFIG_SYS_PPC64 /* 64-bit core */ 533 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 534 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 535 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 536 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 537 #ifdef CONFIG_PPC_T4240 538 #define CONFIG_MAX_CPUS 12 539 #define CONFIG_SYS_NUM_FM1_DTSEC 8 540 #define CONFIG_SYS_NUM_FM1_10GEC 2 541 #define CONFIG_SYS_NUM_FM2_DTSEC 8 542 #define CONFIG_SYS_NUM_FM2_10GEC 2 543 #define CONFIG_NUM_DDR_CONTROLLERS 3 544 #else 545 #define CONFIG_MAX_CPUS 8 546 #define CONFIG_SYS_NUM_FM1_DTSEC 7 547 #define CONFIG_SYS_NUM_FM1_10GEC 1 548 #define CONFIG_SYS_NUM_FM2_DTSEC 7 549 #define CONFIG_SYS_NUM_FM2_10GEC 1 550 #define CONFIG_NUM_DDR_CONTROLLERS 2 551 #endif 552 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 553 #define CONFIG_SYS_FSL_NUM_LAWS 32 554 #define CONFIG_SYS_FSL_SRDS_1 555 #define CONFIG_SYS_FSL_SRDS_2 556 #define CONFIG_SYS_FSL_SRDS_3 557 #define CONFIG_SYS_FSL_SRDS_4 558 #define CONFIG_SYS_FSL_SEC_COMPAT 4 559 #define CONFIG_SYS_NUM_FMAN 2 560 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 561 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 562 #define CONFIG_SYS_FMAN_V3 563 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 564 #define CONFIG_SYS_FSL_TBCLK_DIV 16 565 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 566 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 567 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 568 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 569 #define CONFIG_SYS_FSL_SRIO_LIODN 570 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 571 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 572 #define CONFIG_SYS_FSL_ERRATUM_A004468 573 #define CONFIG_SYS_FSL_ERRATUM_A_004934 574 #define CONFIG_SYS_FSL_ERRATUM_A005871 575 #define CONFIG_SYS_FSL_ERRATUM_A006593 576 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 577 #define CONFIG_SYS_FSL_PCI_VER_3_X 578 579 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 580 #define CONFIG_E6500 581 #define CONFIG_SYS_PPC64 /* 64-bit core */ 582 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 583 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 584 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 585 #define CONFIG_SYS_FSL_NUM_LAWS 32 586 #define CONFIG_SYS_FSL_SRDS_1 587 #define CONFIG_SYS_FSL_SRDS_2 588 #define CONFIG_SYS_FSL_SEC_COMPAT 4 589 #define CONFIG_SYS_NUM_FMAN 1 590 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 591 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 592 #define CONFIG_SYS_FMAN_V3 593 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 594 #define CONFIG_SYS_FSL_TBCLK_DIV 16 595 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 596 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 597 #define CONFIG_SYS_FSL_ERRATUM_A_004934 598 #define CONFIG_SYS_FSL_ERRATUM_A005871 599 #define CONFIG_SYS_FSL_ERRATUM_A006593 600 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 601 602 #ifdef CONFIG_PPC_B4860 603 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 604 #define CONFIG_MAX_CPUS 4 605 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 606 #define CONFIG_SYS_NUM_FM1_DTSEC 6 607 #define CONFIG_SYS_NUM_FM1_10GEC 2 608 #define CONFIG_NUM_DDR_CONTROLLERS 2 609 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 610 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 611 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 612 #define CONFIG_SYS_FSL_SRIO_LIODN 613 #else 614 #define CONFIG_MAX_CPUS 2 615 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 616 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 617 #define CONFIG_SYS_NUM_FM1_DTSEC 4 618 #define CONFIG_SYS_NUM_FM1_10GEC 0 619 #define CONFIG_NUM_DDR_CONTROLLERS 1 620 #endif 621 622 #elif defined(CONFIG_PPC_T1040) 623 #define CONFIG_E5500 624 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 625 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 626 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 627 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 628 #define CONFIG_MAX_CPUS 4 629 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 630 #define CONFIG_SYS_FSL_NUM_LAWS 16 631 #define CONFIG_SYS_FSL_SEC_COMPAT 4 632 #define CONFIG_SYS_NUM_FMAN 1 633 #define CONFIG_SYS_NUM_FM1_DTSEC 5 634 #define CONFIG_NUM_DDR_CONTROLLERS 1 635 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 636 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 637 #define CONFIG_SYS_FMAN_V3 638 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 639 #define CONFIG_SYS_FSL_TBCLK_DIV 32 640 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 641 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 642 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 643 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 644 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 645 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 646 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 647 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 648 649 #elif defined(CONFIG_PPC_C29X) 650 #define CONFIG_MAX_CPUS 1 651 #define CONFIG_FSL_SDHC_V2_3 652 #define CONFIG_SYS_FSL_NUM_LAWS 12 653 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 654 #define CONFIG_TSECV2_1 655 #define CONFIG_SYS_FSL_SEC_COMPAT 6 656 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 657 #define CONFIG_NUM_DDR_CONTROLLERS 1 658 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 659 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 660 661 #else 662 #error Processor type not defined for this platform 663 #endif 664 665 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 666 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 667 #endif 668 669 #ifdef CONFIG_E6500 670 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 671 #else 672 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 673 #endif 674 675 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 676