1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 /* 13 * This macro should be removed when we no longer care about backwards 14 * compatibility with older operating systems. 15 */ 16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 17 18 #include <fsl_ddrc_version.h> 19 #define CONFIG_SYS_FSL_DDR_BE 20 21 /* IP endianness */ 22 #define CONFIG_SYS_FSL_IFC_BE 23 #define CONFIG_SYS_FSL_SFP_BE 24 #define CONFIG_SYS_FSL_SEC_MON_BE 25 26 #if defined(CONFIG_ARCH_MPC8536) 27 #define CONFIG_SYS_FSL_ERRATUM_A004508 28 #define CONFIG_SYS_FSL_ERRATUM_A005125 29 30 #elif defined(CONFIG_ARCH_MPC8540) 31 #define CONFIG_SYS_FSL_DDRC_GEN1 32 33 #elif defined(CONFIG_ARCH_MPC8541) 34 #define CONFIG_SYS_FSL_DDRC_GEN1 35 36 #elif defined(CONFIG_ARCH_MPC8544) 37 #define CONFIG_SYS_FSL_DDRC_GEN2 38 #define CONFIG_SYS_FSL_ERRATUM_A005125 39 40 #elif defined(CONFIG_ARCH_MPC8548) 41 #define CONFIG_SYS_FSL_DDRC_GEN2 42 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 43 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 44 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 45 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 46 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 47 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 48 #define CONFIG_SYS_FSL_RMU 49 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 50 #define CONFIG_SYS_FSL_ERRATUM_A005125 51 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 52 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 53 54 #elif defined(CONFIG_ARCH_MPC8555) 55 #define CONFIG_SYS_FSL_DDRC_GEN1 56 57 #elif defined(CONFIG_ARCH_MPC8560) 58 #define CONFIG_SYS_FSL_DDRC_GEN1 59 60 #elif defined(CONFIG_ARCH_MPC8568) 61 #define CONFIG_SYS_FSL_DDRC_GEN2 62 #define QE_MURAM_SIZE 0x10000UL 63 #define MAX_QE_RISC 2 64 #define QE_NUM_OF_SNUM 28 65 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 66 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 67 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 68 #define CONFIG_SYS_FSL_RMU 69 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 70 71 #elif defined(CONFIG_ARCH_MPC8569) 72 #define QE_MURAM_SIZE 0x20000UL 73 #define MAX_QE_RISC 4 74 #define QE_NUM_OF_SNUM 46 75 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 76 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 77 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 78 #define CONFIG_SYS_FSL_RMU 79 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 80 #define CONFIG_SYS_FSL_ERRATUM_A004508 81 #define CONFIG_SYS_FSL_ERRATUM_A005125 82 83 #elif defined(CONFIG_ARCH_MPC8572) 84 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 85 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 86 #define CONFIG_SYS_FSL_ERRATUM_A004508 87 #define CONFIG_SYS_FSL_ERRATUM_A005125 88 89 #elif defined(CONFIG_ARCH_P1010) 90 #define CONFIG_FSL_SDHC_V2_3 91 #define CONFIG_TSECV2 92 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 93 #define CONFIG_NUM_DDR_CONTROLLERS 1 94 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 95 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 96 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 97 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 98 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 99 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 100 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 101 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 102 #define CONFIG_SYS_FSL_ERRATUM_A005125 103 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 104 #define CONFIG_SYS_FSL_ERRATUM_A004508 105 #define CONFIG_SYS_FSL_ERRATUM_A007075 106 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 107 #define CONFIG_SYS_FSL_ERRATUM_A006261 108 #define CONFIG_SYS_FSL_ERRATUM_A004477 109 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 110 #define CONFIG_ESDHC_HC_BLK_ADDR 111 112 /* P1011 is single core version of P1020 */ 113 #elif defined(CONFIG_ARCH_P1011) 114 #define CONFIG_TSECV2 115 #define CONFIG_FSL_PCIE_DISABLE_ASPM 116 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 117 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 118 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 119 #define CONFIG_SYS_FSL_ERRATUM_A004508 120 #define CONFIG_SYS_FSL_ERRATUM_A005125 121 122 #elif defined(CONFIG_ARCH_P1020) 123 #define CONFIG_TSECV2 124 #define CONFIG_FSL_PCIE_DISABLE_ASPM 125 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 126 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 127 #define CONFIG_SYS_FSL_ERRATUM_A004508 128 #define CONFIG_SYS_FSL_ERRATUM_A005125 129 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 130 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 131 #endif 132 133 #elif defined(CONFIG_ARCH_P1021) 134 #define CONFIG_TSECV2 135 #define CONFIG_FSL_PCIE_DISABLE_ASPM 136 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 137 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 138 #define QE_MURAM_SIZE 0x6000UL 139 #define MAX_QE_RISC 1 140 #define QE_NUM_OF_SNUM 28 141 #define CONFIG_SYS_FSL_ERRATUM_A004508 142 #define CONFIG_SYS_FSL_ERRATUM_A005125 143 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 144 145 #elif defined(CONFIG_ARCH_P1022) 146 #define CONFIG_TSECV2 147 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 148 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 149 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 150 #define CONFIG_FSL_SATA_ERRATUM_A001 151 #define CONFIG_SYS_FSL_ERRATUM_A004508 152 #define CONFIG_SYS_FSL_ERRATUM_A005125 153 #define CONFIG_SYS_FSL_ERRATUM_A004477 154 155 #elif defined(CONFIG_ARCH_P1023) 156 #define CONFIG_SYS_NUM_FMAN 1 157 #define CONFIG_SYS_NUM_FM1_DTSEC 2 158 #define CONFIG_NUM_DDR_CONTROLLERS 1 159 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 160 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 161 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 162 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 163 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 164 #define CONFIG_SYS_FSL_ERRATUM_A004508 165 #define CONFIG_SYS_FSL_ERRATUM_A005125 166 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 167 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 168 169 /* P1024 is lower end variant of P1020 */ 170 #elif defined(CONFIG_ARCH_P1024) 171 #define CONFIG_TSECV2 172 #define CONFIG_FSL_PCIE_DISABLE_ASPM 173 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 174 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 175 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 176 #define CONFIG_SYS_FSL_ERRATUM_A004508 177 #define CONFIG_SYS_FSL_ERRATUM_A005125 178 179 /* P1025 is lower end variant of P1021 */ 180 #elif defined(CONFIG_ARCH_P1025) 181 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 182 #define CONFIG_TSECV2 183 #define CONFIG_FSL_PCIE_DISABLE_ASPM 184 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 185 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 186 #define QE_MURAM_SIZE 0x6000UL 187 #define MAX_QE_RISC 1 188 #define QE_NUM_OF_SNUM 28 189 #define CONFIG_SYS_FSL_ERRATUM_A004508 190 #define CONFIG_SYS_FSL_ERRATUM_A005125 191 192 #elif defined(CONFIG_ARCH_P2020) 193 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 194 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 195 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 196 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 197 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 198 #define CONFIG_SYS_FSL_RMU 199 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 200 #define CONFIG_SYS_FSL_ERRATUM_A004508 201 #define CONFIG_SYS_FSL_ERRATUM_A005125 202 #define CONFIG_SYS_FSL_ERRATUM_A004477 203 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 204 205 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ 206 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 207 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 208 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 209 #define CONFIG_SYS_NUM_FMAN 1 210 #define CONFIG_SYS_NUM_FM1_DTSEC 5 211 #define CONFIG_SYS_NUM_FM1_10GEC 1 212 #define CONFIG_NUM_DDR_CONTROLLERS 1 213 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 214 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 215 #define CONFIG_SYS_FSL_TBCLK_DIV 32 216 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 217 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 218 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 219 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 220 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 221 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 222 #define CONFIG_SYS_FSL_ERRATUM_USB14 223 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 224 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 225 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 226 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 227 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 228 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 229 #define CONFIG_SYS_FSL_ERRATUM_A004510 230 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 231 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 232 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 233 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 234 #define CONFIG_SYS_FSL_ERRATUM_A004849 235 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 236 #define CONFIG_SYS_FSL_ERRATUM_A006261 237 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 238 239 #elif defined(CONFIG_ARCH_P3041) 240 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 241 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 242 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 243 #define CONFIG_SYS_NUM_FMAN 1 244 #define CONFIG_SYS_NUM_FM1_DTSEC 5 245 #define CONFIG_SYS_NUM_FM1_10GEC 1 246 #define CONFIG_NUM_DDR_CONTROLLERS 1 247 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 248 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 249 #define CONFIG_SYS_FSL_TBCLK_DIV 32 250 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 251 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 252 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 253 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 254 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 255 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 256 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 257 #define CONFIG_SYS_FSL_ERRATUM_USB14 258 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 259 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 260 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 261 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 262 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 263 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 264 #define CONFIG_SYS_FSL_ERRATUM_A004510 265 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 266 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 267 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 268 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 269 #define CONFIG_SYS_FSL_ERRATUM_A004849 270 #define CONFIG_SYS_FSL_ERRATUM_A005812 271 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 272 #define CONFIG_SYS_FSL_ERRATUM_A006261 273 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 274 275 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ 276 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 277 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 278 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 279 #define CONFIG_SYS_NUM_FMAN 2 280 #define CONFIG_SYS_NUM_FM1_DTSEC 4 281 #define CONFIG_SYS_NUM_FM2_DTSEC 4 282 #define CONFIG_SYS_NUM_FM1_10GEC 1 283 #define CONFIG_SYS_NUM_FM2_10GEC 1 284 #define CONFIG_NUM_DDR_CONTROLLERS 2 285 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 286 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 287 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 288 #define CONFIG_SYS_FSL_TBCLK_DIV 16 289 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 290 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 291 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 292 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 293 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 294 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 295 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 296 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 297 #define CONFIG_SYS_P4080_ERRATUM_CPU22 298 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 299 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 300 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 301 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 302 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 303 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 304 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 305 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 306 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 307 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 308 #define CONFIG_SYS_FSL_RMU 309 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 310 #define CONFIG_SYS_FSL_ERRATUM_A004510 311 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 312 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 313 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 314 #define CONFIG_SYS_FSL_ERRATUM_A004849 315 #define CONFIG_SYS_FSL_ERRATUM_A004580 316 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 317 #define CONFIG_SYS_FSL_ERRATUM_A005812 318 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 319 #define CONFIG_SYS_FSL_ERRATUM_A007075 320 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 321 322 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ 323 #define CONFIG_SYS_PPC64 /* 64-bit core */ 324 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 325 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 326 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 327 #define CONFIG_SYS_NUM_FMAN 1 328 #define CONFIG_SYS_NUM_FM1_DTSEC 5 329 #define CONFIG_SYS_NUM_FM1_10GEC 1 330 #define CONFIG_NUM_DDR_CONTROLLERS 2 331 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 332 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 333 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 334 #define CONFIG_SYS_FSL_TBCLK_DIV 32 335 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 336 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 337 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 338 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 339 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 340 #define CONFIG_SYS_FSL_ERRATUM_USB14 341 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 342 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 343 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 344 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 345 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 346 #define CONFIG_SYS_FSL_ERRATUM_A004510 347 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 348 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 349 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 350 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 351 #define CONFIG_SYS_FSL_ERRATUM_A006261 352 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 353 354 #elif defined(CONFIG_ARCH_P5040) 355 #define CONFIG_SYS_PPC64 356 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 357 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 358 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 359 #define CONFIG_SYS_NUM_FMAN 2 360 #define CONFIG_SYS_NUM_FM1_DTSEC 5 361 #define CONFIG_SYS_NUM_FM1_10GEC 1 362 #define CONFIG_SYS_NUM_FM2_DTSEC 5 363 #define CONFIG_SYS_NUM_FM2_10GEC 1 364 #define CONFIG_NUM_DDR_CONTROLLERS 2 365 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 366 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 367 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 368 #define CONFIG_SYS_FSL_TBCLK_DIV 16 369 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 370 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 371 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 372 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 373 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 374 #define CONFIG_SYS_FSL_ERRATUM_USB14 375 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 376 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 377 #define CONFIG_SYS_FSL_ERRATUM_A004699 378 #define CONFIG_SYS_FSL_ERRATUM_A004510 379 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 380 #define CONFIG_SYS_FSL_ERRATUM_A006261 381 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 382 #define CONFIG_SYS_FSL_ERRATUM_A005812 383 384 #elif defined(CONFIG_ARCH_BSC9131) 385 #define CONFIG_FSL_SDHC_V2_3 386 #define CONFIG_TSECV2 387 #define CONFIG_NUM_DDR_CONTROLLERS 1 388 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 389 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 390 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 391 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 392 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 393 #define CONFIG_NAND_FSL_IFC 394 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 395 #define CONFIG_SYS_FSL_ERRATUM_A005125 396 #define CONFIG_SYS_FSL_ERRATUM_A004477 397 #define CONFIG_ESDHC_HC_BLK_ADDR 398 399 #elif defined(CONFIG_ARCH_BSC9132) 400 #define CONFIG_FSL_SDHC_V2_3 401 #define CONFIG_TSECV2 402 #define CONFIG_NUM_DDR_CONTROLLERS 2 403 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 404 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 405 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 406 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 407 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 408 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 409 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 410 #define CONFIG_NAND_FSL_IFC 411 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 412 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 413 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 414 #define CONFIG_SYS_FSL_ERRATUM_A005125 415 #define CONFIG_SYS_FSL_ERRATUM_A005434 416 #define CONFIG_SYS_FSL_ERRATUM_A004477 417 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 418 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 419 #define CONFIG_ESDHC_HC_BLK_ADDR 420 421 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) 422 #define CONFIG_E6500 423 #define CONFIG_SYS_PPC64 /* 64-bit core */ 424 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 425 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 426 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 427 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 428 #ifdef CONFIG_ARCH_T4240 429 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 430 #define CONFIG_SYS_NUM_FM1_DTSEC 8 431 #define CONFIG_SYS_NUM_FM1_10GEC 2 432 #define CONFIG_SYS_NUM_FM2_DTSEC 8 433 #define CONFIG_SYS_NUM_FM2_10GEC 2 434 #define CONFIG_NUM_DDR_CONTROLLERS 3 435 #define CONFIG_SYS_FSL_ERRATUM_A006261 436 #else 437 #define CONFIG_SYS_NUM_FM1_DTSEC 6 438 #define CONFIG_SYS_NUM_FM1_10GEC 1 439 #define CONFIG_SYS_NUM_FM2_DTSEC 8 440 #define CONFIG_SYS_NUM_FM2_10GEC 1 441 #define CONFIG_NUM_DDR_CONTROLLERS 2 442 #if defined(CONFIG_ARCH_T4160) 443 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 444 #endif 445 #endif 446 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 447 #define CONFIG_SYS_FSL_SRDS_1 448 #define CONFIG_SYS_FSL_SRDS_2 449 #define CONFIG_SYS_FSL_SRDS_3 450 #define CONFIG_SYS_FSL_SRDS_4 451 #define CONFIG_SYS_NUM_FMAN 2 452 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 453 #define CONFIG_SYS_PME_CLK 0 454 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 455 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 456 #define CONFIG_SYS_FMAN_V3 457 #define CONFIG_SYS_FM1_CLK 3 458 #define CONFIG_SYS_FM2_CLK 3 459 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 460 #define CONFIG_SYS_FSL_TBCLK_DIV 16 461 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 462 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 463 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 464 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 465 #define CONFIG_SYS_FSL_SRIO_LIODN 466 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 467 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 468 #define CONFIG_SYS_FSL_ERRATUM_A004468 469 #define CONFIG_SYS_FSL_ERRATUM_A005871 470 #define CONFIG_SYS_FSL_ERRATUM_A006379 471 #define CONFIG_SYS_FSL_ERRATUM_A007186 472 #define CONFIG_SYS_FSL_ERRATUM_A006593 473 #define CONFIG_SYS_FSL_ERRATUM_A007798 474 #define CONFIG_SYS_FSL_ERRATUM_A009942 475 #define CONFIG_SYS_FSL_SFP_VER_3_0 476 #define CONFIG_SYS_FSL_PCI_VER_3_X 477 478 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) 479 #define CONFIG_E6500 480 #define CONFIG_SYS_PPC64 /* 64-bit core */ 481 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 482 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 483 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 484 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 485 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 486 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 487 #define CONFIG_SYS_FSL_SRDS_1 488 #define CONFIG_SYS_FSL_SRDS_2 489 #define CONFIG_SYS_MAPLE 490 #define CONFIG_SYS_CPRI 491 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 492 #define CONFIG_SYS_NUM_FMAN 1 493 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 494 #define CONFIG_SYS_FM1_CLK 0 495 #define CONFIG_SYS_CPRI_CLK 3 496 #define CONFIG_SYS_ULB_CLK 4 497 #define CONFIG_SYS_ETVPE_CLK 1 498 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 499 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 500 #define CONFIG_SYS_FMAN_V3 501 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 502 #define CONFIG_SYS_FSL_TBCLK_DIV 16 503 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 504 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 505 #define CONFIG_SYS_FSL_ERRATUM_A005871 506 #define CONFIG_SYS_FSL_ERRATUM_A006379 507 #define CONFIG_SYS_FSL_ERRATUM_A007186 508 #define CONFIG_SYS_FSL_ERRATUM_A006593 509 #define CONFIG_SYS_FSL_ERRATUM_A007075 510 #define CONFIG_SYS_FSL_ERRATUM_A006475 511 #define CONFIG_SYS_FSL_ERRATUM_A006384 512 #define CONFIG_SYS_FSL_ERRATUM_A007212 513 #define CONFIG_SYS_FSL_ERRATUM_A004477 514 #define CONFIG_SYS_FSL_ERRATUM_A009942 515 #define CONFIG_SYS_FSL_SFP_VER_3_0 516 517 #ifdef CONFIG_ARCH_B4860 518 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 519 #define CONFIG_MAX_DSP_CPUS 12 520 #define CONFIG_NUM_DSP_CPUS 6 521 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 522 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 523 #define CONFIG_SYS_NUM_FM1_DTSEC 6 524 #define CONFIG_SYS_NUM_FM1_10GEC 2 525 #define CONFIG_NUM_DDR_CONTROLLERS 2 526 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 527 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 528 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 529 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 530 #define CONFIG_SYS_FSL_SRIO_LIODN 531 #else 532 #define CONFIG_MAX_DSP_CPUS 2 533 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 534 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 535 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 536 #define CONFIG_SYS_NUM_FM1_DTSEC 4 537 #define CONFIG_SYS_NUM_FM1_10GEC 0 538 #define CONFIG_NUM_DDR_CONTROLLERS 1 539 #endif 540 541 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) 542 #define CONFIG_E5500 543 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 544 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 545 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 546 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 547 #ifdef CONFIG_SYS_FSL_DDR4 548 #define CONFIG_SYS_FSL_DDRC_GEN4 549 #endif 550 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 551 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 552 #define CONFIG_SYS_FSL_SRDS_1 553 #define CONFIG_SYS_NUM_FMAN 1 554 #define CONFIG_SYS_NUM_FM1_DTSEC 5 555 #define CONFIG_NUM_DDR_CONTROLLERS 1 556 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 557 #define CONFIG_PME_PLAT_CLK_DIV 2 558 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 559 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 560 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 561 #define CONFIG_SYS_FSL_ERRATUM_A008044 562 #define CONFIG_SYS_FMAN_V3 563 #define CONFIG_FM_PLAT_CLK_DIV 1 564 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 565 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 566 per rcw field value */ 567 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 568 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 569 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 570 #define CONFIG_SYS_FSL_TBCLK_DIV 16 571 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 572 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 573 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 574 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 575 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 576 #define QE_MURAM_SIZE 0x6000UL 577 #define MAX_QE_RISC 1 578 #define QE_NUM_OF_SNUM 28 579 #define CONFIG_SYS_FSL_SFP_VER_3_0 580 #define CONFIG_SYS_FSL_ERRATUM_A008378 581 #define CONFIG_SYS_FSL_ERRATUM_A009663 582 #define CONFIG_SYS_FSL_ERRATUM_A009942 583 584 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) 585 #define CONFIG_E5500 586 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 587 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 588 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 589 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 590 #define CONFIG_SYS_FMAN_V3 591 #ifdef CONFIG_SYS_FSL_DDR4 592 #define CONFIG_SYS_FSL_DDRC_GEN4 593 #endif 594 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 595 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 596 #define CONFIG_SYS_FSL_SRDS_1 597 #define CONFIG_SYS_NUM_FMAN 1 598 #define CONFIG_SYS_NUM_FM1_DTSEC 4 599 #define CONFIG_SYS_NUM_FM1_10GEC 1 600 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 601 #define CONFIG_NUM_DDR_CONTROLLERS 1 602 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 603 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 604 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 605 #define CONFIG_SYS_FM1_CLK 0 606 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 607 per rcw field value */ 608 #define CONFIG_QBMAN_CLK_DIV 1 609 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 610 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 611 #define CONFIG_SYS_FSL_TBCLK_DIV 16 612 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 613 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 614 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 615 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 616 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 617 #define QE_MURAM_SIZE 0x6000UL 618 #define MAX_QE_RISC 1 619 #define QE_NUM_OF_SNUM 28 620 #define CONFIG_SYS_FSL_SFP_VER_3_0 621 #define CONFIG_SYS_FSL_ERRATUM_A008378 622 #define CONFIG_SYS_FSL_ERRATUM_A009663 623 #define CONFIG_SYS_FSL_ERRATUM_A009942 624 625 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) 626 #define CONFIG_E6500 627 #define CONFIG_SYS_PPC64 /* 64-bit core */ 628 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 629 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 630 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 631 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 632 #define CONFIG_SYS_FSL_QMAN_V3 633 #define CONFIG_SYS_NUM_FMAN 1 634 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 635 #define CONFIG_SYS_FSL_SRDS_1 636 #define CONFIG_SYS_FSL_PCI_VER_3_X 637 #if defined(CONFIG_ARCH_T2080) 638 #define CONFIG_SYS_NUM_FM1_DTSEC 8 639 #define CONFIG_SYS_NUM_FM1_10GEC 4 640 #define CONFIG_SYS_FSL_SRDS_2 641 #define CONFIG_SYS_FSL_SRIO_LIODN 642 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 643 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 644 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 645 #elif defined(CONFIG_ARCH_T2081) 646 #define CONFIG_SYS_NUM_FM1_DTSEC 6 647 #define CONFIG_SYS_NUM_FM1_10GEC 2 648 #endif 649 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 650 #define CONFIG_NUM_DDR_CONTROLLERS 1 651 #define CONFIG_PME_PLAT_CLK_DIV 1 652 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 653 #define CONFIG_SYS_FM1_CLK 0 654 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 655 per rcw field value */ 656 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 657 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 658 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 659 #define CONFIG_SYS_FMAN_V3 660 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 661 #define CONFIG_SYS_FSL_TBCLK_DIV 16 662 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 663 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 664 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 665 #define CONFIG_SYS_FSL_ERRATUM_A007212 666 #define CONFIG_SYS_FSL_SFP_VER_3_0 667 #define CONFIG_SYS_FSL_ISBC_VER 2 668 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 669 #define CONFIG_SYS_FSL_ERRATUM_A006593 670 #define CONFIG_SYS_FSL_ERRATUM_A007186 671 #define CONFIG_SYS_FSL_ERRATUM_A006379 672 #define CONFIG_SYS_FSL_ERRATUM_A009942 673 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 674 #define CONFIG_SYS_FSL_SFP_VER_3_0 675 676 677 #elif defined(CONFIG_ARCH_C29X) 678 #define CONFIG_FSL_SDHC_V2_3 679 #define CONFIG_TSECV2_1 680 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 681 #define CONFIG_NUM_DDR_CONTROLLERS 1 682 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 683 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 684 #define CONFIG_SYS_FSL_ERRATUM_A005125 685 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 686 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 687 688 #elif defined(CONFIG_ARCH_QEMU_E500) 689 690 #else 691 #error Processor type not defined for this platform 692 #endif 693 694 #ifdef CONFIG_E6500 695 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 696 #else 697 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 698 #endif 699 700 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 701 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 702 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ 703 !defined(CONFIG_SYS_FSL_DDRC_GEN4) 704 #define CONFIG_SYS_FSL_DDRC_GEN3 705 #endif 706 707 #if !defined(CONFIG_ARCH_C29X) 708 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 709 #endif 710 711 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 712