1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 /* Number of TLB CAM entries we have on FSL Book-E chips */ 27 #if defined(CONFIG_E500MC) 28 #define CONFIG_SYS_NUM_TLBCAMS 64 29 #elif defined(CONFIG_E500) 30 #define CONFIG_SYS_NUM_TLBCAMS 16 31 #endif 32 33 #if defined(CONFIG_MPC8536) 34 #define CONFIG_MAX_CPUS 1 35 #define CONFIG_SYS_FSL_NUM_LAWS 12 36 #define CONFIG_SYS_FSL_SEC_COMPAT 2 37 38 #elif defined(CONFIG_MPC8540) 39 #define CONFIG_MAX_CPUS 1 40 #define CONFIG_SYS_FSL_NUM_LAWS 8 41 42 #elif defined(CONFIG_MPC8541) 43 #define CONFIG_MAX_CPUS 1 44 #define CONFIG_SYS_FSL_NUM_LAWS 8 45 #define CONFIG_SYS_FSL_SEC_COMPAT 2 46 47 #elif defined(CONFIG_MPC8544) 48 #define CONFIG_MAX_CPUS 1 49 #define CONFIG_SYS_FSL_NUM_LAWS 10 50 #define CONFIG_SYS_FSL_SEC_COMPAT 2 51 52 #elif defined(CONFIG_MPC8548) 53 #define CONFIG_MAX_CPUS 1 54 #define CONFIG_SYS_FSL_NUM_LAWS 10 55 #define CONFIG_SYS_FSL_SEC_COMPAT 2 56 57 #elif defined(CONFIG_MPC8555) 58 #define CONFIG_MAX_CPUS 1 59 #define CONFIG_SYS_FSL_NUM_LAWS 8 60 #define CONFIG_SYS_FSL_SEC_COMPAT 2 61 62 #elif defined(CONFIG_MPC8560) 63 #define CONFIG_MAX_CPUS 1 64 #define CONFIG_SYS_FSL_NUM_LAWS 8 65 66 #elif defined(CONFIG_MPC8568) 67 #define CONFIG_MAX_CPUS 1 68 #define CONFIG_SYS_FSL_NUM_LAWS 10 69 #define CONFIG_SYS_FSL_SEC_COMPAT 2 70 #define QE_MURAM_SIZE 0x10000UL 71 #define MAX_QE_RISC 2 72 #define QE_NUM_OF_SNUM 28 73 74 #elif defined(CONFIG_MPC8569) 75 #define CONFIG_MAX_CPUS 1 76 #define CONFIG_SYS_FSL_NUM_LAWS 10 77 #define CONFIG_SYS_FSL_SEC_COMPAT 2 78 #define QE_MURAM_SIZE 0x20000UL 79 #define MAX_QE_RISC 4 80 #define QE_NUM_OF_SNUM 46 81 82 #elif defined(CONFIG_MPC8572) 83 #define CONFIG_MAX_CPUS 2 84 #define CONFIG_SYS_FSL_NUM_LAWS 12 85 #define CONFIG_SYS_FSL_SEC_COMPAT 2 86 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 87 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 88 89 #elif defined(CONFIG_P1010) 90 #define CONFIG_MAX_CPUS 1 91 #define CONFIG_SYS_FSL_NUM_LAWS 12 92 #define CONFIG_TSECV2 93 #define CONFIG_SYS_FSL_SEC_COMPAT 4 94 95 #elif defined(CONFIG_P1011) 96 #define CONFIG_MAX_CPUS 1 97 #define CONFIG_SYS_FSL_NUM_LAWS 12 98 #define CONFIG_TSECV2 99 #define CONFIG_FSL_PCIE_DISABLE_ASPM 100 #define CONFIG_SYS_FSL_SEC_COMPAT 2 101 102 #elif defined(CONFIG_P1012) 103 #define CONFIG_MAX_CPUS 1 104 #define CONFIG_SYS_FSL_NUM_LAWS 12 105 #define CONFIG_TSECV2 106 #define CONFIG_FSL_PCIE_DISABLE_ASPM 107 #define CONFIG_SYS_FSL_SEC_COMPAT 2 108 109 #elif defined(CONFIG_P1013) 110 #define CONFIG_MAX_CPUS 1 111 #define CONFIG_SYS_FSL_NUM_LAWS 12 112 #define CONFIG_TSECV2 113 #define CONFIG_SYS_FSL_SEC_COMPAT 2 114 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 115 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 116 #define CONFIG_FSL_SATA_ERRATUM_A001 117 118 #elif defined(CONFIG_P1014) 119 #define CONFIG_MAX_CPUS 1 120 #define CONFIG_SYS_FSL_NUM_LAWS 12 121 #define CONFIG_TSECV2 122 #define CONFIG_SYS_FSL_SEC_COMPAT 4 123 124 #elif defined(CONFIG_P1017) 125 #define CONFIG_MAX_CPUS 1 126 #define CONFIG_SYS_FSL_NUM_LAWS 12 127 #define CONFIG_SYS_FSL_SEC_COMPAT 4 128 #define CONFIG_SYS_NUM_FMAN 1 129 #define CONFIG_SYS_NUM_FM1_DTSEC 2 130 #define CONFIG_NUM_DDR_CONTROLLERS 1 131 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 132 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 133 134 #elif defined(CONFIG_P1020) 135 #define CONFIG_MAX_CPUS 2 136 #define CONFIG_SYS_FSL_NUM_LAWS 12 137 #define CONFIG_TSECV2 138 #define CONFIG_FSL_PCIE_DISABLE_ASPM 139 #define CONFIG_SYS_FSL_SEC_COMPAT 2 140 141 #elif defined(CONFIG_P1021) 142 #define CONFIG_MAX_CPUS 2 143 #define CONFIG_SYS_FSL_NUM_LAWS 12 144 #define CONFIG_TSECV2 145 #define CONFIG_FSL_PCIE_DISABLE_ASPM 146 #define CONFIG_SYS_FSL_SEC_COMPAT 2 147 148 #elif defined(CONFIG_P1022) 149 #define CONFIG_MAX_CPUS 2 150 #define CONFIG_SYS_FSL_NUM_LAWS 12 151 #define CONFIG_TSECV2 152 #define CONFIG_SYS_FSL_SEC_COMPAT 2 153 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 154 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 155 #define CONFIG_FSL_SATA_ERRATUM_A001 156 157 #elif defined(CONFIG_P1023) 158 #define CONFIG_MAX_CPUS 2 159 #define CONFIG_SYS_FSL_NUM_LAWS 12 160 #define CONFIG_SYS_FSL_SEC_COMPAT 4 161 #define CONFIG_SYS_NUM_FMAN 1 162 #define CONFIG_SYS_NUM_FM1_DTSEC 2 163 #define CONFIG_NUM_DDR_CONTROLLERS 1 164 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 165 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 166 167 #elif defined(CONFIG_P2010) 168 #define CONFIG_MAX_CPUS 1 169 #define CONFIG_SYS_FSL_NUM_LAWS 12 170 #define CONFIG_SYS_FSL_SEC_COMPAT 2 171 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 172 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 173 174 #elif defined(CONFIG_P2020) 175 #define CONFIG_MAX_CPUS 2 176 #define CONFIG_SYS_FSL_NUM_LAWS 12 177 #define CONFIG_SYS_FSL_SEC_COMPAT 2 178 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 179 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 180 181 #elif defined(CONFIG_PPC_P2040) 182 #define CONFIG_MAX_CPUS 4 183 #define CONFIG_SYS_FSL_NUM_LAWS 32 184 #define CONFIG_SYS_FSL_SEC_COMPAT 4 185 #define CONFIG_SYS_NUM_FMAN 1 186 #define CONFIG_SYS_NUM_FM1_DTSEC 5 187 #define CONFIG_NUM_DDR_CONTROLLERS 1 188 189 #elif defined(CONFIG_PPC_P3041) 190 #define CONFIG_MAX_CPUS 4 191 #define CONFIG_SYS_FSL_NUM_LAWS 32 192 #define CONFIG_SYS_FSL_SEC_COMPAT 4 193 #define CONFIG_SYS_NUM_FMAN 1 194 #define CONFIG_SYS_NUM_FM1_DTSEC 5 195 #define CONFIG_SYS_NUM_FM1_10GEC 1 196 #define CONFIG_NUM_DDR_CONTROLLERS 1 197 198 #elif defined(CONFIG_PPC_P4040) 199 #define CONFIG_MAX_CPUS 4 200 #define CONFIG_SYS_FSL_NUM_LAWS 32 201 #define CONFIG_SYS_FSL_SEC_COMPAT 4 202 203 #elif defined(CONFIG_PPC_P4080) 204 #define CONFIG_MAX_CPUS 8 205 #define CONFIG_SYS_FSL_NUM_LAWS 32 206 #define CONFIG_SYS_FSL_SEC_COMPAT 4 207 #define CONFIG_SYS_NUM_FMAN 2 208 #define CONFIG_SYS_NUM_FM1_DTSEC 4 209 #define CONFIG_SYS_NUM_FM2_DTSEC 4 210 #define CONFIG_SYS_NUM_FM1_10GEC 1 211 #define CONFIG_SYS_NUM_FM2_10GEC 1 212 #define CONFIG_NUM_DDR_CONTROLLERS 2 213 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 214 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 215 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 216 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 217 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 218 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 219 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 220 #define CONFIG_SYS_P4080_ERRATUM_CPU22 221 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 222 223 #elif defined(CONFIG_PPC_P5010) 224 #define CONFIG_MAX_CPUS 1 225 #define CONFIG_SYS_FSL_NUM_LAWS 32 226 #define CONFIG_SYS_FSL_SEC_COMPAT 4 227 #define CONFIG_SYS_NUM_FMAN 1 228 #define CONFIG_SYS_NUM_FM1_DTSEC 5 229 #define CONFIG_SYS_NUM_FM1_10GEC 1 230 #define CONFIG_NUM_DDR_CONTROLLERS 1 231 232 #elif defined(CONFIG_PPC_P5020) 233 #define CONFIG_MAX_CPUS 2 234 #define CONFIG_SYS_FSL_NUM_LAWS 32 235 #define CONFIG_SYS_FSL_SEC_COMPAT 4 236 #define CONFIG_SYS_NUM_FMAN 1 237 #define CONFIG_SYS_NUM_FM1_DTSEC 5 238 #define CONFIG_SYS_NUM_FM1_10GEC 1 239 #define CONFIG_NUM_DDR_CONTROLLERS 2 240 241 #else 242 #error Processor type not defined for this platform 243 #endif 244 245 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 246