1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 28 #endif 29 30 /* Number of TLB CAM entries we have on FSL Book-E chips */ 31 #if defined(CONFIG_E500MC) 32 #define CONFIG_SYS_NUM_TLBCAMS 64 33 #elif defined(CONFIG_E500) 34 #define CONFIG_SYS_NUM_TLBCAMS 16 35 #endif 36 37 #if defined(CONFIG_MPC8536) 38 #define CONFIG_MAX_CPUS 1 39 #define CONFIG_SYS_FSL_NUM_LAWS 12 40 #define CONFIG_SYS_FSL_SEC_COMPAT 2 41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 42 43 #elif defined(CONFIG_MPC8540) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 47 48 #elif defined(CONFIG_MPC8541) 49 #define CONFIG_MAX_CPUS 1 50 #define CONFIG_SYS_FSL_NUM_LAWS 8 51 #define CONFIG_SYS_FSL_SEC_COMPAT 2 52 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 53 54 #elif defined(CONFIG_MPC8544) 55 #define CONFIG_MAX_CPUS 1 56 #define CONFIG_SYS_FSL_NUM_LAWS 10 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_MPC8548) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2 64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 65 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 66 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 67 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 68 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 69 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 70 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 71 #define CONFIG_SYS_FSL_RMU 72 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 73 74 #elif defined(CONFIG_MPC8555) 75 #define CONFIG_MAX_CPUS 1 76 #define CONFIG_SYS_FSL_NUM_LAWS 8 77 #define CONFIG_SYS_FSL_SEC_COMPAT 2 78 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 79 80 #elif defined(CONFIG_MPC8560) 81 #define CONFIG_MAX_CPUS 1 82 #define CONFIG_SYS_FSL_NUM_LAWS 8 83 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 84 85 #elif defined(CONFIG_MPC8568) 86 #define CONFIG_MAX_CPUS 1 87 #define CONFIG_SYS_FSL_NUM_LAWS 10 88 #define CONFIG_SYS_FSL_SEC_COMPAT 2 89 #define QE_MURAM_SIZE 0x10000UL 90 #define MAX_QE_RISC 2 91 #define QE_NUM_OF_SNUM 28 92 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 93 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 94 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 95 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 96 #define CONFIG_SYS_FSL_RMU 97 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 98 99 #elif defined(CONFIG_MPC8569) 100 #define CONFIG_MAX_CPUS 1 101 #define CONFIG_SYS_FSL_NUM_LAWS 10 102 #define CONFIG_SYS_FSL_SEC_COMPAT 2 103 #define QE_MURAM_SIZE 0x20000UL 104 #define MAX_QE_RISC 4 105 #define QE_NUM_OF_SNUM 46 106 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 107 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 108 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 109 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 110 #define CONFIG_SYS_FSL_RMU 111 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 112 113 #elif defined(CONFIG_MPC8572) 114 #define CONFIG_MAX_CPUS 2 115 #define CONFIG_SYS_FSL_NUM_LAWS 12 116 #define CONFIG_SYS_FSL_SEC_COMPAT 2 117 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 118 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 119 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 120 121 #elif defined(CONFIG_P1010) 122 #define CONFIG_MAX_CPUS 1 123 #define CONFIG_FSL_SDHC_V2_3 124 #define CONFIG_SYS_FSL_NUM_LAWS 12 125 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 126 #define CONFIG_TSECV2 127 #define CONFIG_SYS_FSL_SEC_COMPAT 4 128 #define CONFIG_FSL_SATA_V2 129 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 130 #define CONFIG_NUM_DDR_CONTROLLERS 1 131 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 132 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 133 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 134 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 135 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 136 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 137 138 /* P1011 is single core version of P1020 */ 139 #elif defined(CONFIG_P1011) 140 #define CONFIG_MAX_CPUS 1 141 #define CONFIG_SYS_FSL_NUM_LAWS 12 142 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 143 #define CONFIG_TSECV2 144 #define CONFIG_FSL_PCIE_DISABLE_ASPM 145 #define CONFIG_SYS_FSL_SEC_COMPAT 2 146 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 147 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 148 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 149 150 /* P1012 is single core version of P1021 */ 151 #elif defined(CONFIG_P1012) 152 #define CONFIG_MAX_CPUS 1 153 #define CONFIG_SYS_FSL_NUM_LAWS 12 154 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 155 #define CONFIG_TSECV2 156 #define CONFIG_FSL_PCIE_DISABLE_ASPM 157 #define CONFIG_SYS_FSL_SEC_COMPAT 2 158 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 159 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 160 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 161 #define QE_MURAM_SIZE 0x6000UL 162 #define MAX_QE_RISC 1 163 #define QE_NUM_OF_SNUM 28 164 165 /* P1013 is single core version of P1022 */ 166 #elif defined(CONFIG_P1013) 167 #define CONFIG_MAX_CPUS 1 168 #define CONFIG_SYS_FSL_NUM_LAWS 12 169 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 170 #define CONFIG_TSECV2 171 #define CONFIG_SYS_FSL_SEC_COMPAT 2 172 #define CONFIG_FSL_SATA_V2 173 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 174 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 175 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 176 #define CONFIG_FSL_SATA_ERRATUM_A001 177 178 #elif defined(CONFIG_P1014) 179 #define CONFIG_MAX_CPUS 1 180 #define CONFIG_FSL_SDHC_V2_3 181 #define CONFIG_SYS_FSL_NUM_LAWS 12 182 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 183 #define CONFIG_TSECV2 184 #define CONFIG_SYS_FSL_SEC_COMPAT 4 185 #define CONFIG_FSL_SATA_V2 186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 187 #define CONFIG_NUM_DDR_CONTROLLERS 1 188 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 189 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 190 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 191 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 192 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 193 194 /* P1015 is single core version of P1024 */ 195 #elif defined(CONFIG_P1015) 196 #define CONFIG_MAX_CPUS 1 197 #define CONFIG_SYS_FSL_NUM_LAWS 12 198 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 199 #define CONFIG_TSECV2 200 #define CONFIG_FSL_PCIE_DISABLE_ASPM 201 #define CONFIG_SYS_FSL_SEC_COMPAT 2 202 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 203 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 204 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 205 206 /* P1016 is single core version of P1025 */ 207 #elif defined(CONFIG_P1016) 208 #define CONFIG_MAX_CPUS 1 209 #define CONFIG_SYS_FSL_NUM_LAWS 12 210 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 211 #define CONFIG_TSECV2 212 #define CONFIG_FSL_PCIE_DISABLE_ASPM 213 #define CONFIG_SYS_FSL_SEC_COMPAT 2 214 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 215 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 216 #define QE_MURAM_SIZE 0x6000UL 217 #define MAX_QE_RISC 1 218 #define QE_NUM_OF_SNUM 28 219 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 220 221 /* P1017 is single core version of P1023 */ 222 #elif defined(CONFIG_P1017) 223 #define CONFIG_MAX_CPUS 1 224 #define CONFIG_SYS_FSL_NUM_LAWS 12 225 #define CONFIG_SYS_FSL_SEC_COMPAT 4 226 #define CONFIG_SYS_NUM_FMAN 1 227 #define CONFIG_SYS_NUM_FM1_DTSEC 2 228 #define CONFIG_NUM_DDR_CONTROLLERS 1 229 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 230 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 231 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 232 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 233 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 234 235 #elif defined(CONFIG_P1020) 236 #define CONFIG_MAX_CPUS 2 237 #define CONFIG_SYS_FSL_NUM_LAWS 12 238 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 239 #define CONFIG_TSECV2 240 #define CONFIG_FSL_PCIE_DISABLE_ASPM 241 #define CONFIG_SYS_FSL_SEC_COMPAT 2 242 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 243 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 244 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 245 246 #elif defined(CONFIG_P1021) 247 #define CONFIG_MAX_CPUS 2 248 #define CONFIG_SYS_FSL_NUM_LAWS 12 249 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 250 #define CONFIG_TSECV2 251 #define CONFIG_FSL_PCIE_DISABLE_ASPM 252 #define CONFIG_SYS_FSL_SEC_COMPAT 2 253 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 254 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 255 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 256 #define QE_MURAM_SIZE 0x6000UL 257 #define MAX_QE_RISC 1 258 #define QE_NUM_OF_SNUM 28 259 260 #elif defined(CONFIG_P1022) 261 #define CONFIG_MAX_CPUS 2 262 #define CONFIG_SYS_FSL_NUM_LAWS 12 263 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 264 #define CONFIG_TSECV2 265 #define CONFIG_SYS_FSL_SEC_COMPAT 2 266 #define CONFIG_FSL_SATA_V2 267 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 268 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 269 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 270 #define CONFIG_FSL_SATA_ERRATUM_A001 271 272 #elif defined(CONFIG_P1023) 273 #define CONFIG_MAX_CPUS 2 274 #define CONFIG_SYS_FSL_NUM_LAWS 12 275 #define CONFIG_SYS_FSL_SEC_COMPAT 4 276 #define CONFIG_SYS_NUM_FMAN 1 277 #define CONFIG_SYS_NUM_FM1_DTSEC 2 278 #define CONFIG_NUM_DDR_CONTROLLERS 1 279 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 280 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 281 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 282 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 283 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 284 285 /* P1024 is lower end variant of P1020 */ 286 #elif defined(CONFIG_P1024) 287 #define CONFIG_MAX_CPUS 2 288 #define CONFIG_SYS_FSL_NUM_LAWS 12 289 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 290 #define CONFIG_TSECV2 291 #define CONFIG_FSL_PCIE_DISABLE_ASPM 292 #define CONFIG_SYS_FSL_SEC_COMPAT 2 293 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 294 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 295 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 296 297 /* P1025 is lower end variant of P1021 */ 298 #elif defined(CONFIG_P1025) 299 #define CONFIG_MAX_CPUS 2 300 #define CONFIG_SYS_FSL_NUM_LAWS 12 301 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 302 #define CONFIG_TSECV2 303 #define CONFIG_FSL_PCIE_DISABLE_ASPM 304 #define CONFIG_SYS_FSL_SEC_COMPAT 2 305 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 306 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 307 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 308 #define QE_MURAM_SIZE 0x6000UL 309 #define MAX_QE_RISC 1 310 #define QE_NUM_OF_SNUM 28 311 312 /* P2010 is single core version of P2020 */ 313 #elif defined(CONFIG_P2010) 314 #define CONFIG_MAX_CPUS 1 315 #define CONFIG_SYS_FSL_NUM_LAWS 12 316 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 317 #define CONFIG_SYS_FSL_SEC_COMPAT 2 318 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 319 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 320 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 321 322 #elif defined(CONFIG_P2020) 323 #define CONFIG_MAX_CPUS 2 324 #define CONFIG_SYS_FSL_NUM_LAWS 12 325 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 326 #define CONFIG_SYS_FSL_SEC_COMPAT 2 327 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 328 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 329 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 330 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 331 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 332 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 333 #define CONFIG_SYS_FSL_RMU 334 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 335 336 #elif defined(CONFIG_PPC_P2040) 337 #define CONFIG_MAX_CPUS 4 338 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 339 #define CONFIG_SYS_FSL_NUM_LAWS 32 340 #define CONFIG_SYS_FSL_SEC_COMPAT 4 341 #define CONFIG_SYS_NUM_FMAN 1 342 #define CONFIG_SYS_NUM_FM1_DTSEC 5 343 #define CONFIG_NUM_DDR_CONTROLLERS 1 344 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 345 #define CONFIG_SYS_FSL_TBCLK_DIV 32 346 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 347 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 348 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 349 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 350 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 351 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 352 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 353 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 354 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 355 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 356 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 357 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 358 359 #elif defined(CONFIG_PPC_P2041) 360 #define CONFIG_MAX_CPUS 4 361 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 362 #define CONFIG_SYS_FSL_NUM_LAWS 32 363 #define CONFIG_SYS_FSL_SEC_COMPAT 4 364 #define CONFIG_FSL_SATA_V2 365 #define CONFIG_SYS_NUM_FMAN 1 366 #define CONFIG_SYS_NUM_FM1_DTSEC 5 367 #define CONFIG_SYS_NUM_FM1_10GEC 1 368 #define CONFIG_NUM_DDR_CONTROLLERS 1 369 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 370 #define CONFIG_SYS_FSL_TBCLK_DIV 32 371 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 372 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 373 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 374 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 375 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 376 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 377 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 378 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 379 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 380 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 381 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 382 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 383 384 #elif defined(CONFIG_PPC_P3041) 385 #define CONFIG_MAX_CPUS 4 386 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 387 #define CONFIG_SYS_FSL_NUM_LAWS 32 388 #define CONFIG_SYS_FSL_SEC_COMPAT 4 389 #define CONFIG_FSL_SATA_V2 390 #define CONFIG_SYS_NUM_FMAN 1 391 #define CONFIG_SYS_NUM_FM1_DTSEC 5 392 #define CONFIG_SYS_NUM_FM1_10GEC 1 393 #define CONFIG_NUM_DDR_CONTROLLERS 1 394 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 395 #define CONFIG_SYS_FSL_TBCLK_DIV 32 396 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 397 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 398 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 399 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 400 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 401 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 402 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 403 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 404 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 405 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 406 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 407 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 408 409 #elif defined(CONFIG_PPC_P3060) 410 #define CONFIG_MAX_CPUS 8 411 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 412 #define CONFIG_SYS_FSL_NUM_LAWS 32 413 #define CONFIG_SYS_FSL_SEC_COMPAT 4 414 #define CONFIG_SYS_NUM_FMAN 2 415 #define CONFIG_SYS_NUM_FM1_DTSEC 4 416 #define CONFIG_SYS_NUM_FM2_DTSEC 4 417 #define CONFIG_NUM_DDR_CONTROLLERS 1 418 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 419 #define CONFIG_SYS_FSL_TBCLK_DIV 16 420 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 421 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 422 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 423 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 424 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 425 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 426 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 427 428 #elif defined(CONFIG_PPC_P4040) 429 #define CONFIG_MAX_CPUS 4 430 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 431 #define CONFIG_SYS_FSL_NUM_LAWS 32 432 #define CONFIG_SYS_FSL_SEC_COMPAT 4 433 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 434 #define CONFIG_SYS_FSL_TBCLK_DIV 16 435 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 436 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 437 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 438 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 439 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 440 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 441 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 442 443 #elif defined(CONFIG_PPC_P4080) 444 #define CONFIG_MAX_CPUS 8 445 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 446 #define CONFIG_SYS_FSL_NUM_LAWS 32 447 #define CONFIG_SYS_FSL_SEC_COMPAT 4 448 #define CONFIG_SYS_NUM_FMAN 2 449 #define CONFIG_SYS_NUM_FM1_DTSEC 4 450 #define CONFIG_SYS_NUM_FM2_DTSEC 4 451 #define CONFIG_SYS_NUM_FM1_10GEC 1 452 #define CONFIG_SYS_NUM_FM2_10GEC 1 453 #define CONFIG_NUM_DDR_CONTROLLERS 2 454 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 455 #define CONFIG_SYS_FSL_TBCLK_DIV 16 456 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 457 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 458 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 459 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 460 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 461 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 462 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 463 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 464 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 465 #define CONFIG_SYS_P4080_ERRATUM_CPU22 466 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 467 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 468 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 469 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 470 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 471 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 472 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 473 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 474 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 475 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 476 #define CONFIG_SYS_FSL_RMU 477 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 478 479 /* P5010 is single core version of P5020 */ 480 #elif defined(CONFIG_PPC_P5010) 481 #define CONFIG_MAX_CPUS 1 482 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 483 #define CONFIG_SYS_FSL_NUM_LAWS 32 484 #define CONFIG_SYS_FSL_SEC_COMPAT 4 485 #define CONFIG_FSL_SATA_V2 486 #define CONFIG_SYS_NUM_FMAN 1 487 #define CONFIG_SYS_NUM_FM1_DTSEC 5 488 #define CONFIG_SYS_NUM_FM1_10GEC 1 489 #define CONFIG_NUM_DDR_CONTROLLERS 1 490 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 491 #define CONFIG_SYS_FSL_TBCLK_DIV 32 492 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 493 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 494 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 495 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 496 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 497 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 498 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 499 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 500 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 501 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 502 503 #elif defined(CONFIG_PPC_P5020) 504 #define CONFIG_MAX_CPUS 2 505 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 506 #define CONFIG_SYS_FSL_NUM_LAWS 32 507 #define CONFIG_SYS_FSL_SEC_COMPAT 4 508 #define CONFIG_FSL_SATA_V2 509 #define CONFIG_SYS_NUM_FMAN 1 510 #define CONFIG_SYS_NUM_FM1_DTSEC 5 511 #define CONFIG_SYS_NUM_FM1_10GEC 1 512 #define CONFIG_NUM_DDR_CONTROLLERS 2 513 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 514 #define CONFIG_SYS_FSL_TBCLK_DIV 32 515 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 516 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 517 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 518 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 519 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 520 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 521 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 522 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 523 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 524 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 525 526 #elif defined(CONFIG_BSC9131) 527 #define CONFIG_MAX_CPUS 1 528 #define CONFIG_FSL_SDHC_V2_3 529 #define CONFIG_SYS_FSL_NUM_LAWS 12 530 #define CONFIG_TSECV2 531 #define CONFIG_SYS_FSL_SEC_COMPAT 4 532 #define CONFIG_NUM_DDR_CONTROLLERS 1 533 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 534 #define CONFIG_NAND_FSL_IFC 535 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 536 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 537 538 #else 539 #error Processor type not defined for this platform 540 #endif 541 542 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 543 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 544 #endif 545 546 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 547