1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #include <fsl_ddrc_version.h> 23 #define CONFIG_SYS_FSL_DDR_BE 24 25 /* IP endianness */ 26 #define CONFIG_SYS_FSL_IFC_BE 27 #define CONFIG_SYS_FSL_SEC_BE 28 #define CONFIG_SYS_FSL_SFP_BE 29 #define CONFIG_SYS_FSL_SEC_MON_BE 30 31 /* Number of TLB CAM entries we have on FSL Book-E chips */ 32 #if defined(CONFIG_E500MC) 33 #define CONFIG_SYS_NUM_TLBCAMS 64 34 #elif defined(CONFIG_E500) 35 #define CONFIG_SYS_NUM_TLBCAMS 16 36 #endif 37 38 #if defined(CONFIG_ARCH_MPC8536) 39 #define CONFIG_MAX_CPUS 1 40 #define CONFIG_SYS_FSL_NUM_LAWS 12 41 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 42 #define CONFIG_SYS_FSL_SEC_COMPAT 2 43 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 44 #define CONFIG_SYS_FSL_ERRATUM_A004508 45 #define CONFIG_SYS_FSL_ERRATUM_A005125 46 47 #elif defined(CONFIG_ARCH_MPC8540) 48 #define CONFIG_MAX_CPUS 1 49 #define CONFIG_SYS_FSL_NUM_LAWS 8 50 #define CONFIG_SYS_FSL_DDRC_GEN1 51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 52 53 #elif defined(CONFIG_ARCH_MPC8541) 54 #define CONFIG_MAX_CPUS 1 55 #define CONFIG_SYS_FSL_NUM_LAWS 8 56 #define CONFIG_SYS_FSL_DDRC_GEN1 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_ARCH_MPC8544) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_DDRC_GEN2 64 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 65 #define CONFIG_SYS_FSL_SEC_COMPAT 2 66 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 67 #define CONFIG_SYS_FSL_ERRATUM_A005125 68 69 #elif defined(CONFIG_ARCH_MPC8548) 70 #define CONFIG_MAX_CPUS 1 71 #define CONFIG_SYS_FSL_NUM_LAWS 10 72 #define CONFIG_SYS_FSL_DDRC_GEN2 73 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 74 #define CONFIG_SYS_FSL_SEC_COMPAT 2 75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 76 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 77 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 78 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 79 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 80 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 81 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 82 #define CONFIG_SYS_FSL_RMU 83 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 84 #define CONFIG_SYS_FSL_ERRATUM_A005125 85 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 86 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 87 88 #elif defined(CONFIG_ARCH_MPC8555) 89 #define CONFIG_MAX_CPUS 1 90 #define CONFIG_SYS_FSL_NUM_LAWS 8 91 #define CONFIG_SYS_FSL_DDRC_GEN1 92 #define CONFIG_SYS_FSL_SEC_COMPAT 2 93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 94 95 #elif defined(CONFIG_ARCH_MPC8560) 96 #define CONFIG_MAX_CPUS 1 97 #define CONFIG_SYS_FSL_NUM_LAWS 8 98 #define CONFIG_SYS_FSL_DDRC_GEN1 99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 100 101 #elif defined(CONFIG_ARCH_MPC8568) 102 #define CONFIG_MAX_CPUS 1 103 #define CONFIG_SYS_FSL_NUM_LAWS 10 104 #define CONFIG_SYS_FSL_DDRC_GEN2 105 #define CONFIG_SYS_FSL_SEC_COMPAT 2 106 #define QE_MURAM_SIZE 0x10000UL 107 #define MAX_QE_RISC 2 108 #define QE_NUM_OF_SNUM 28 109 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 110 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 111 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 112 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 113 #define CONFIG_SYS_FSL_RMU 114 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 115 116 #elif defined(CONFIG_ARCH_MPC8569) 117 #define CONFIG_MAX_CPUS 1 118 #define CONFIG_SYS_FSL_NUM_LAWS 10 119 #define CONFIG_SYS_FSL_SEC_COMPAT 2 120 #define QE_MURAM_SIZE 0x20000UL 121 #define MAX_QE_RISC 4 122 #define QE_NUM_OF_SNUM 46 123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 124 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 125 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 126 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 127 #define CONFIG_SYS_FSL_RMU 128 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 129 #define CONFIG_SYS_FSL_ERRATUM_A004508 130 #define CONFIG_SYS_FSL_ERRATUM_A005125 131 132 #elif defined(CONFIG_ARCH_MPC8572) 133 #define CONFIG_MAX_CPUS 2 134 #define CONFIG_SYS_FSL_NUM_LAWS 12 135 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 136 #define CONFIG_SYS_FSL_SEC_COMPAT 2 137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 138 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 139 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 140 #define CONFIG_SYS_FSL_ERRATUM_A004508 141 #define CONFIG_SYS_FSL_ERRATUM_A005125 142 143 #elif defined(CONFIG_ARCH_P1010) 144 #define CONFIG_MAX_CPUS 1 145 #define CONFIG_FSL_SDHC_V2_3 146 #define CONFIG_SYS_FSL_NUM_LAWS 12 147 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 148 #define CONFIG_TSECV2 149 #define CONFIG_SYS_FSL_SEC_COMPAT 4 150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 151 #define CONFIG_NUM_DDR_CONTROLLERS 1 152 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 153 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 154 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 155 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 156 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 157 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 158 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 159 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 160 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 161 #define CONFIG_SYS_FSL_ERRATUM_A005125 162 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 163 #define CONFIG_SYS_FSL_ERRATUM_A004508 164 #define CONFIG_SYS_FSL_ERRATUM_A007075 165 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 166 #define CONFIG_SYS_FSL_ERRATUM_A006261 167 #define CONFIG_SYS_FSL_ERRATUM_A004477 168 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 169 #define CONFIG_ESDHC_HC_BLK_ADDR 170 171 /* P1011 is single core version of P1020 */ 172 #elif defined(CONFIG_ARCH_P1011) 173 #define CONFIG_MAX_CPUS 1 174 #define CONFIG_SYS_FSL_NUM_LAWS 12 175 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 176 #define CONFIG_TSECV2 177 #define CONFIG_FSL_PCIE_DISABLE_ASPM 178 #define CONFIG_SYS_FSL_SEC_COMPAT 2 179 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 180 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 181 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 182 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 183 #define CONFIG_SYS_FSL_ERRATUM_A004508 184 #define CONFIG_SYS_FSL_ERRATUM_A005125 185 186 /* P1017 is single core version of P1023 */ 187 #elif defined(CONFIG_P1017) 188 #define CONFIG_MAX_CPUS 1 189 #define CONFIG_SYS_FSL_NUM_LAWS 12 190 #define CONFIG_SYS_FSL_SEC_COMPAT 4 191 #define CONFIG_SYS_NUM_FMAN 1 192 #define CONFIG_SYS_NUM_FM1_DTSEC 2 193 #define CONFIG_NUM_DDR_CONTROLLERS 1 194 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 195 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 196 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 197 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 198 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 199 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 200 #define CONFIG_SYS_FSL_ERRATUM_A004508 201 #define CONFIG_SYS_FSL_ERRATUM_A005125 202 203 #elif defined(CONFIG_P1020) 204 #define CONFIG_MAX_CPUS 2 205 #define CONFIG_SYS_FSL_NUM_LAWS 12 206 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 207 #define CONFIG_TSECV2 208 #define CONFIG_FSL_PCIE_DISABLE_ASPM 209 #define CONFIG_SYS_FSL_SEC_COMPAT 2 210 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 211 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 212 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 213 #define CONFIG_SYS_FSL_ERRATUM_A004508 214 #define CONFIG_SYS_FSL_ERRATUM_A005125 215 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 216 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 217 #endif 218 219 #elif defined(CONFIG_P1021) 220 #define CONFIG_MAX_CPUS 2 221 #define CONFIG_SYS_FSL_NUM_LAWS 12 222 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 223 #define CONFIG_TSECV2 224 #define CONFIG_FSL_PCIE_DISABLE_ASPM 225 #define CONFIG_SYS_FSL_SEC_COMPAT 2 226 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 227 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 228 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 229 #define QE_MURAM_SIZE 0x6000UL 230 #define MAX_QE_RISC 1 231 #define QE_NUM_OF_SNUM 28 232 #define CONFIG_SYS_FSL_ERRATUM_A004508 233 #define CONFIG_SYS_FSL_ERRATUM_A005125 234 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 235 236 #elif defined(CONFIG_ARCH_P1022) 237 #define CONFIG_MAX_CPUS 2 238 #define CONFIG_SYS_FSL_NUM_LAWS 12 239 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 240 #define CONFIG_TSECV2 241 #define CONFIG_SYS_FSL_SEC_COMPAT 2 242 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 243 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 244 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 245 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 246 #define CONFIG_FSL_SATA_ERRATUM_A001 247 #define CONFIG_SYS_FSL_ERRATUM_A004508 248 #define CONFIG_SYS_FSL_ERRATUM_A005125 249 #define CONFIG_SYS_FSL_ERRATUM_A004477 250 251 #elif defined(CONFIG_ARCH_P1023) 252 #define CONFIG_MAX_CPUS 2 253 #define CONFIG_SYS_FSL_NUM_LAWS 12 254 #define CONFIG_SYS_FSL_SEC_COMPAT 4 255 #define CONFIG_SYS_NUM_FMAN 1 256 #define CONFIG_SYS_NUM_FM1_DTSEC 2 257 #define CONFIG_NUM_DDR_CONTROLLERS 1 258 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 259 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 260 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 261 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 262 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 263 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 264 #define CONFIG_SYS_FSL_ERRATUM_A004508 265 #define CONFIG_SYS_FSL_ERRATUM_A005125 266 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 267 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 268 269 /* P1024 is lower end variant of P1020 */ 270 #elif defined(CONFIG_P1024) 271 #define CONFIG_MAX_CPUS 2 272 #define CONFIG_SYS_FSL_NUM_LAWS 12 273 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 274 #define CONFIG_TSECV2 275 #define CONFIG_FSL_PCIE_DISABLE_ASPM 276 #define CONFIG_SYS_FSL_SEC_COMPAT 2 277 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 278 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 279 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 280 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 281 #define CONFIG_SYS_FSL_ERRATUM_A004508 282 #define CONFIG_SYS_FSL_ERRATUM_A005125 283 284 /* P1025 is lower end variant of P1021 */ 285 #elif defined(CONFIG_P1025) 286 #define CONFIG_MAX_CPUS 2 287 #define CONFIG_SYS_FSL_NUM_LAWS 12 288 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 289 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 290 #define CONFIG_TSECV2 291 #define CONFIG_FSL_PCIE_DISABLE_ASPM 292 #define CONFIG_SYS_FSL_SEC_COMPAT 2 293 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 294 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 295 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 296 #define QE_MURAM_SIZE 0x6000UL 297 #define MAX_QE_RISC 1 298 #define QE_NUM_OF_SNUM 28 299 #define CONFIG_SYS_FSL_ERRATUM_A004508 300 #define CONFIG_SYS_FSL_ERRATUM_A005125 301 302 /* P2010 is single core version of P2020 */ 303 #elif defined(CONFIG_P2010) 304 #define CONFIG_MAX_CPUS 1 305 #define CONFIG_SYS_FSL_NUM_LAWS 12 306 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 307 #define CONFIG_SYS_FSL_SEC_COMPAT 2 308 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 309 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 310 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 311 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 312 #define CONFIG_SYS_FSL_ERRATUM_A004508 313 #define CONFIG_SYS_FSL_ERRATUM_A005125 314 315 #elif defined(CONFIG_P2020) 316 #define CONFIG_MAX_CPUS 2 317 #define CONFIG_SYS_FSL_NUM_LAWS 12 318 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 319 #define CONFIG_SYS_FSL_SEC_COMPAT 2 320 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 321 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 322 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 323 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 324 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 325 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 326 #define CONFIG_SYS_FSL_RMU 327 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 328 #define CONFIG_SYS_FSL_ERRATUM_A004508 329 #define CONFIG_SYS_FSL_ERRATUM_A005125 330 #define CONFIG_SYS_FSL_ERRATUM_A004477 331 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 332 333 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 334 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 335 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 336 #define CONFIG_MAX_CPUS 4 337 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 338 #define CONFIG_SYS_FSL_NUM_LAWS 32 339 #define CONFIG_SYS_FSL_SEC_COMPAT 4 340 #define CONFIG_SYS_NUM_FMAN 1 341 #define CONFIG_SYS_NUM_FM1_DTSEC 5 342 #define CONFIG_SYS_NUM_FM1_10GEC 1 343 #define CONFIG_NUM_DDR_CONTROLLERS 1 344 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 345 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 346 #define CONFIG_SYS_FSL_TBCLK_DIV 32 347 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 348 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 349 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 350 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 351 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 352 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 353 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 354 #define CONFIG_SYS_FSL_ERRATUM_USB14 355 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 356 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 357 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 358 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 359 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 360 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 361 #define CONFIG_SYS_FSL_ERRATUM_A004510 362 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 363 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 364 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 365 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 366 #define CONFIG_SYS_FSL_ERRATUM_A004849 367 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 368 #define CONFIG_SYS_FSL_ERRATUM_A006261 369 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 370 371 #elif defined(CONFIG_PPC_P3041) 372 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 373 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 374 #define CONFIG_MAX_CPUS 4 375 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 376 #define CONFIG_SYS_FSL_NUM_LAWS 32 377 #define CONFIG_SYS_FSL_SEC_COMPAT 4 378 #define CONFIG_SYS_NUM_FMAN 1 379 #define CONFIG_SYS_NUM_FM1_DTSEC 5 380 #define CONFIG_SYS_NUM_FM1_10GEC 1 381 #define CONFIG_NUM_DDR_CONTROLLERS 1 382 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 383 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 384 #define CONFIG_SYS_FSL_TBCLK_DIV 32 385 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 386 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 387 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 388 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 389 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 390 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 391 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 392 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 393 #define CONFIG_SYS_FSL_ERRATUM_USB14 394 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 395 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 396 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 397 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 398 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 399 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 400 #define CONFIG_SYS_FSL_ERRATUM_A004510 401 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 402 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 403 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 404 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 405 #define CONFIG_SYS_FSL_ERRATUM_A004849 406 #define CONFIG_SYS_FSL_ERRATUM_A005812 407 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 408 #define CONFIG_SYS_FSL_ERRATUM_A006261 409 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 410 411 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 412 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 413 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 414 #define CONFIG_MAX_CPUS 8 415 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 416 #define CONFIG_SYS_FSL_NUM_LAWS 32 417 #define CONFIG_SYS_FSL_SEC_COMPAT 4 418 #define CONFIG_SYS_NUM_FMAN 2 419 #define CONFIG_SYS_NUM_FM1_DTSEC 4 420 #define CONFIG_SYS_NUM_FM2_DTSEC 4 421 #define CONFIG_SYS_NUM_FM1_10GEC 1 422 #define CONFIG_SYS_NUM_FM2_10GEC 1 423 #define CONFIG_NUM_DDR_CONTROLLERS 2 424 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 425 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 426 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 427 #define CONFIG_SYS_FSL_TBCLK_DIV 16 428 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 429 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 430 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 431 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 432 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 433 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 434 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 435 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 436 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 437 #define CONFIG_SYS_P4080_ERRATUM_CPU22 438 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 439 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 440 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 441 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 442 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 443 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 444 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 445 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 446 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 447 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 448 #define CONFIG_SYS_FSL_RMU 449 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 450 #define CONFIG_SYS_FSL_ERRATUM_A004510 451 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 452 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 453 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 454 #define CONFIG_SYS_FSL_ERRATUM_A004849 455 #define CONFIG_SYS_FSL_ERRATUM_A004580 456 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 457 #define CONFIG_SYS_FSL_ERRATUM_A005812 458 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 459 #define CONFIG_SYS_FSL_ERRATUM_A007075 460 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 461 462 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 463 #define CONFIG_SYS_PPC64 /* 64-bit core */ 464 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 465 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 466 #define CONFIG_MAX_CPUS 2 467 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 468 #define CONFIG_SYS_FSL_NUM_LAWS 32 469 #define CONFIG_SYS_FSL_SEC_COMPAT 4 470 #define CONFIG_SYS_NUM_FMAN 1 471 #define CONFIG_SYS_NUM_FM1_DTSEC 5 472 #define CONFIG_SYS_NUM_FM1_10GEC 1 473 #define CONFIG_NUM_DDR_CONTROLLERS 2 474 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 475 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 476 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 477 #define CONFIG_SYS_FSL_TBCLK_DIV 32 478 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 479 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 480 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 481 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 482 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 483 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 484 #define CONFIG_SYS_FSL_ERRATUM_USB14 485 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 486 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 487 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 488 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 489 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 490 #define CONFIG_SYS_FSL_ERRATUM_A004510 491 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 492 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 493 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 494 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 495 #define CONFIG_SYS_FSL_ERRATUM_A006261 496 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 497 498 #elif defined(CONFIG_PPC_P5040) 499 #define CONFIG_SYS_PPC64 500 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 501 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 502 #define CONFIG_MAX_CPUS 4 503 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 504 #define CONFIG_SYS_FSL_NUM_LAWS 32 505 #define CONFIG_SYS_FSL_SEC_COMPAT 4 506 #define CONFIG_SYS_NUM_FMAN 2 507 #define CONFIG_SYS_NUM_FM1_DTSEC 5 508 #define CONFIG_SYS_NUM_FM1_10GEC 1 509 #define CONFIG_SYS_NUM_FM2_DTSEC 5 510 #define CONFIG_SYS_NUM_FM2_10GEC 1 511 #define CONFIG_NUM_DDR_CONTROLLERS 2 512 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 513 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 514 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 515 #define CONFIG_SYS_FSL_TBCLK_DIV 16 516 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 517 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 518 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 519 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 520 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 521 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 522 #define CONFIG_SYS_FSL_ERRATUM_USB14 523 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 524 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 525 #define CONFIG_SYS_FSL_ERRATUM_A004699 526 #define CONFIG_SYS_FSL_ERRATUM_A004510 527 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 528 #define CONFIG_SYS_FSL_ERRATUM_A006261 529 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 530 #define CONFIG_SYS_FSL_ERRATUM_A005812 531 532 #elif defined(CONFIG_ARCH_BSC9131) 533 #define CONFIG_MAX_CPUS 1 534 #define CONFIG_FSL_SDHC_V2_3 535 #define CONFIG_SYS_FSL_NUM_LAWS 12 536 #define CONFIG_TSECV2 537 #define CONFIG_SYS_FSL_SEC_COMPAT 4 538 #define CONFIG_NUM_DDR_CONTROLLERS 1 539 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 540 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 541 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 542 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 543 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 544 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 545 #define CONFIG_NAND_FSL_IFC 546 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 547 #define CONFIG_SYS_FSL_ERRATUM_A005125 548 #define CONFIG_SYS_FSL_ERRATUM_A004477 549 #define CONFIG_ESDHC_HC_BLK_ADDR 550 551 #elif defined(CONFIG_ARCH_BSC9132) 552 #define CONFIG_MAX_CPUS 2 553 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 554 #define CONFIG_FSL_SDHC_V2_3 555 #define CONFIG_SYS_FSL_NUM_LAWS 12 556 #define CONFIG_TSECV2 557 #define CONFIG_SYS_FSL_SEC_COMPAT 4 558 #define CONFIG_NUM_DDR_CONTROLLERS 2 559 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 560 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 561 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 562 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 563 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 564 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 565 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 566 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 567 #define CONFIG_NAND_FSL_IFC 568 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 569 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 570 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 571 #define CONFIG_SYS_FSL_ERRATUM_A005125 572 #define CONFIG_SYS_FSL_ERRATUM_A005434 573 #define CONFIG_SYS_FSL_ERRATUM_A004477 574 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 575 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 576 #define CONFIG_ESDHC_HC_BLK_ADDR 577 578 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 579 defined(CONFIG_PPC_T4080) 580 #define CONFIG_E6500 581 #define CONFIG_SYS_PPC64 /* 64-bit core */ 582 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 583 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 584 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 585 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 586 #ifdef CONFIG_PPC_T4240 587 #define CONFIG_MAX_CPUS 12 588 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 589 #define CONFIG_SYS_NUM_FM1_DTSEC 8 590 #define CONFIG_SYS_NUM_FM1_10GEC 2 591 #define CONFIG_SYS_NUM_FM2_DTSEC 8 592 #define CONFIG_SYS_NUM_FM2_10GEC 2 593 #define CONFIG_NUM_DDR_CONTROLLERS 3 594 #define CONFIG_SYS_FSL_ERRATUM_A006261 595 #else 596 #define CONFIG_SYS_NUM_FM1_DTSEC 6 597 #define CONFIG_SYS_NUM_FM1_10GEC 1 598 #define CONFIG_SYS_NUM_FM2_DTSEC 8 599 #define CONFIG_SYS_NUM_FM2_10GEC 1 600 #define CONFIG_NUM_DDR_CONTROLLERS 2 601 #if defined(CONFIG_PPC_T4160) 602 #define CONFIG_MAX_CPUS 8 603 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 604 #elif defined(CONFIG_PPC_T4080) 605 #define CONFIG_MAX_CPUS 4 606 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } 607 #endif 608 #endif 609 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 610 #define CONFIG_SYS_FSL_NUM_LAWS 32 611 #define CONFIG_SYS_FSL_SRDS_1 612 #define CONFIG_SYS_FSL_SRDS_2 613 #define CONFIG_SYS_FSL_SRDS_3 614 #define CONFIG_SYS_FSL_SRDS_4 615 #define CONFIG_SYS_FSL_SEC_COMPAT 4 616 #define CONFIG_SYS_NUM_FMAN 2 617 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 618 #define CONFIG_SYS_PME_CLK 0 619 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 620 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 621 #define CONFIG_SYS_FMAN_V3 622 #define CONFIG_SYS_FM1_CLK 3 623 #define CONFIG_SYS_FM2_CLK 3 624 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 625 #define CONFIG_SYS_FSL_TBCLK_DIV 16 626 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 627 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 628 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 629 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 630 #define CONFIG_SYS_FSL_SRIO_LIODN 631 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 632 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 633 #define CONFIG_SYS_FSL_ERRATUM_A004468 634 #define CONFIG_SYS_FSL_ERRATUM_A_004934 635 #define CONFIG_SYS_FSL_ERRATUM_A005871 636 #define CONFIG_SYS_FSL_ERRATUM_A006379 637 #define CONFIG_SYS_FSL_ERRATUM_A007186 638 #define CONFIG_SYS_FSL_ERRATUM_A006593 639 #define CONFIG_SYS_FSL_ERRATUM_A007798 640 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 641 #define CONFIG_SYS_FSL_SFP_VER_3_0 642 #define CONFIG_SYS_FSL_PCI_VER_3_X 643 644 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 645 #define CONFIG_E6500 646 #define CONFIG_SYS_PPC64 /* 64-bit core */ 647 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 648 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 649 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 650 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 651 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 652 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 653 #define CONFIG_SYS_FSL_NUM_LAWS 32 654 #define CONFIG_SYS_FSL_SRDS_1 655 #define CONFIG_SYS_FSL_SRDS_2 656 #define CONFIG_SYS_MAPLE 657 #define CONFIG_SYS_CPRI 658 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 659 #define CONFIG_SYS_FSL_SEC_COMPAT 4 660 #define CONFIG_SYS_NUM_FMAN 1 661 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 662 #define CONFIG_SYS_FM1_CLK 0 663 #define CONFIG_SYS_CPRI_CLK 3 664 #define CONFIG_SYS_ULB_CLK 4 665 #define CONFIG_SYS_ETVPE_CLK 1 666 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 667 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 668 #define CONFIG_SYS_FMAN_V3 669 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 670 #define CONFIG_SYS_FSL_TBCLK_DIV 16 671 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 672 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 673 #define CONFIG_SYS_FSL_ERRATUM_A_004934 674 #define CONFIG_SYS_FSL_ERRATUM_A005871 675 #define CONFIG_SYS_FSL_ERRATUM_A006379 676 #define CONFIG_SYS_FSL_ERRATUM_A007186 677 #define CONFIG_SYS_FSL_ERRATUM_A006593 678 #define CONFIG_SYS_FSL_ERRATUM_A007075 679 #define CONFIG_SYS_FSL_ERRATUM_A006475 680 #define CONFIG_SYS_FSL_ERRATUM_A006384 681 #define CONFIG_SYS_FSL_ERRATUM_A007212 682 #define CONFIG_SYS_FSL_ERRATUM_A004477 683 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 684 #define CONFIG_SYS_FSL_SFP_VER_3_0 685 686 #ifdef CONFIG_PPC_B4860 687 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 688 #define CONFIG_MAX_CPUS 4 689 #define CONFIG_MAX_DSP_CPUS 12 690 #define CONFIG_NUM_DSP_CPUS 6 691 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 692 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 693 #define CONFIG_SYS_NUM_FM1_DTSEC 6 694 #define CONFIG_SYS_NUM_FM1_10GEC 2 695 #define CONFIG_NUM_DDR_CONTROLLERS 2 696 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 697 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 698 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 699 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 700 #define CONFIG_SYS_FSL_SRIO_LIODN 701 #else 702 #define CONFIG_MAX_CPUS 2 703 #define CONFIG_MAX_DSP_CPUS 2 704 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 705 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 706 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 707 #define CONFIG_SYS_NUM_FM1_DTSEC 4 708 #define CONFIG_SYS_NUM_FM1_10GEC 0 709 #define CONFIG_NUM_DDR_CONTROLLERS 1 710 #endif 711 712 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 713 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 714 #define CONFIG_E5500 715 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 716 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 717 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 718 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 719 #ifdef CONFIG_SYS_FSL_DDR4 720 #define CONFIG_SYS_FSL_DDRC_GEN4 721 #endif 722 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 723 #define CONFIG_MAX_CPUS 4 724 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 725 #define CONFIG_MAX_CPUS 2 726 #endif 727 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 728 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 729 #define CONFIG_SYS_FSL_NUM_LAWS 16 730 #define CONFIG_SYS_FSL_SRDS_1 731 #define CONFIG_SYS_FSL_SEC_COMPAT 5 732 #define CONFIG_SYS_NUM_FMAN 1 733 #define CONFIG_SYS_NUM_FM1_DTSEC 5 734 #define CONFIG_NUM_DDR_CONTROLLERS 1 735 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 736 #define CONFIG_PME_PLAT_CLK_DIV 2 737 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 738 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 739 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 740 #define CONFIG_SYS_FSL_ERRATUM_A008044 741 #define CONFIG_SYS_FMAN_V3 742 #define CONFIG_FM_PLAT_CLK_DIV 1 743 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 744 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 745 per rcw field value */ 746 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 747 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 748 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 749 #define CONFIG_SYS_FSL_TBCLK_DIV 16 750 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 751 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 752 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 753 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 754 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 755 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 756 #define QE_MURAM_SIZE 0x6000UL 757 #define MAX_QE_RISC 1 758 #define QE_NUM_OF_SNUM 28 759 #define CONFIG_SYS_FSL_SFP_VER_3_0 760 #define CONFIG_SYS_FSL_ERRATUM_A008378 761 #define CONFIG_SYS_FSL_ERRATUM_A009663 762 763 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ 764 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 765 #define CONFIG_E5500 766 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 767 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 768 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 769 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 770 #define CONFIG_SYS_FMAN_V3 771 #ifdef CONFIG_SYS_FSL_DDR4 772 #define CONFIG_SYS_FSL_DDRC_GEN4 773 #endif 774 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) 775 #define CONFIG_MAX_CPUS 2 776 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 777 #define CONFIG_MAX_CPUS 1 778 #endif 779 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 780 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 781 #define CONFIG_SYS_FSL_NUM_LAWS 16 782 #define CONFIG_SYS_FSL_SRDS_1 783 #define CONFIG_SYS_FSL_SEC_COMPAT 5 784 #define CONFIG_SYS_NUM_FMAN 1 785 #define CONFIG_SYS_NUM_FM1_DTSEC 4 786 #define CONFIG_SYS_NUM_FM1_10GEC 1 787 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 788 #define CONFIG_NUM_DDR_CONTROLLERS 1 789 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 790 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 791 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 792 #define CONFIG_SYS_FM1_CLK 0 793 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 794 per rcw field value */ 795 #define CONFIG_QBMAN_CLK_DIV 1 796 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 797 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 798 #define CONFIG_SYS_FSL_TBCLK_DIV 16 799 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 800 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 801 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 802 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 803 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 804 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 805 #define QE_MURAM_SIZE 0x6000UL 806 #define MAX_QE_RISC 1 807 #define QE_NUM_OF_SNUM 28 808 #define CONFIG_SYS_FSL_SFP_VER_3_0 809 #define CONFIG_SYS_FSL_ERRATUM_A008378 810 #define CONFIG_SYS_FSL_ERRATUM_A009663 811 812 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 813 #define CONFIG_E6500 814 #define CONFIG_SYS_PPC64 /* 64-bit core */ 815 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 816 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 817 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 818 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 819 #define CONFIG_SYS_FSL_QMAN_V3 820 #define CONFIG_MAX_CPUS 4 821 #define CONFIG_SYS_FSL_NUM_LAWS 32 822 #define CONFIG_SYS_FSL_SEC_COMPAT 4 823 #define CONFIG_SYS_NUM_FMAN 1 824 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 825 #define CONFIG_SYS_FSL_SRDS_1 826 #define CONFIG_SYS_FSL_PCI_VER_3_X 827 #if defined(CONFIG_PPC_T2080) 828 #define CONFIG_SYS_NUM_FM1_DTSEC 8 829 #define CONFIG_SYS_NUM_FM1_10GEC 4 830 #define CONFIG_SYS_FSL_SRDS_2 831 #define CONFIG_SYS_FSL_SRIO_LIODN 832 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 833 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 834 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 835 #elif defined(CONFIG_PPC_T2081) 836 #define CONFIG_SYS_NUM_FM1_DTSEC 6 837 #define CONFIG_SYS_NUM_FM1_10GEC 2 838 #endif 839 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 840 #define CONFIG_NUM_DDR_CONTROLLERS 1 841 #define CONFIG_PME_PLAT_CLK_DIV 1 842 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 843 #define CONFIG_SYS_FM1_CLK 0 844 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 845 per rcw field value */ 846 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 847 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 848 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 849 #define CONFIG_SYS_FMAN_V3 850 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 851 #define CONFIG_SYS_FSL_TBCLK_DIV 16 852 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 853 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 854 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 855 #define CONFIG_SYS_FSL_ERRATUM_A007212 856 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 857 #define CONFIG_SYS_FSL_SFP_VER_3_0 858 #define CONFIG_SYS_FSL_ISBC_VER 2 859 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 860 #define CONFIG_SYS_FSL_ERRATUM_A006593 861 #define CONFIG_SYS_FSL_ERRATUM_A007186 862 #define CONFIG_SYS_FSL_ERRATUM_A006379 863 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 864 #define CONFIG_SYS_FSL_SFP_VER_3_0 865 866 867 #elif defined(CONFIG_ARCH_C29X) 868 #define CONFIG_MAX_CPUS 1 869 #define CONFIG_FSL_SDHC_V2_3 870 #define CONFIG_SYS_FSL_NUM_LAWS 12 871 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 872 #define CONFIG_TSECV2_1 873 #define CONFIG_SYS_FSL_SEC_COMPAT 6 874 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 875 #define CONFIG_NUM_DDR_CONTROLLERS 1 876 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 877 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 878 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 879 #define CONFIG_SYS_FSL_ERRATUM_A005125 880 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 881 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 882 883 #elif defined(CONFIG_QEMU_E500) 884 #define CONFIG_MAX_CPUS 1 885 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 886 887 #else 888 #error Processor type not defined for this platform 889 #endif 890 891 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 892 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 893 #endif 894 895 #ifdef CONFIG_E6500 896 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 897 #else 898 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 899 #endif 900 901 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 902 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 903 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ 904 !defined(CONFIG_SYS_FSL_DDRC_GEN4) 905 #define CONFIG_SYS_FSL_DDRC_GEN3 906 #endif 907 908 #if !defined(CONFIG_ARCH_C29X) 909 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 910 #endif 911 912 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 913