1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 28 #endif 29 30 /* Number of TLB CAM entries we have on FSL Book-E chips */ 31 #if defined(CONFIG_E500MC) 32 #define CONFIG_SYS_NUM_TLBCAMS 64 33 #elif defined(CONFIG_E500) 34 #define CONFIG_SYS_NUM_TLBCAMS 16 35 #endif 36 37 #if defined(CONFIG_MPC8536) 38 #define CONFIG_MAX_CPUS 1 39 #define CONFIG_SYS_FSL_NUM_LAWS 12 40 #define CONFIG_SYS_FSL_SEC_COMPAT 2 41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 42 43 #elif defined(CONFIG_MPC8540) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 47 48 #elif defined(CONFIG_MPC8541) 49 #define CONFIG_MAX_CPUS 1 50 #define CONFIG_SYS_FSL_NUM_LAWS 8 51 #define CONFIG_SYS_FSL_SEC_COMPAT 2 52 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 53 54 #elif defined(CONFIG_MPC8544) 55 #define CONFIG_MAX_CPUS 1 56 #define CONFIG_SYS_FSL_NUM_LAWS 10 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_MPC8548) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2 64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 65 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 66 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 67 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 68 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 69 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 70 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 71 #define CONFIG_SYS_FSL_RMU 72 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 73 74 #elif defined(CONFIG_MPC8555) 75 #define CONFIG_MAX_CPUS 1 76 #define CONFIG_SYS_FSL_NUM_LAWS 8 77 #define CONFIG_SYS_FSL_SEC_COMPAT 2 78 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 79 80 #elif defined(CONFIG_MPC8560) 81 #define CONFIG_MAX_CPUS 1 82 #define CONFIG_SYS_FSL_NUM_LAWS 8 83 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 84 85 #elif defined(CONFIG_MPC8568) 86 #define CONFIG_MAX_CPUS 1 87 #define CONFIG_SYS_FSL_NUM_LAWS 10 88 #define CONFIG_SYS_FSL_SEC_COMPAT 2 89 #define QE_MURAM_SIZE 0x10000UL 90 #define MAX_QE_RISC 2 91 #define QE_NUM_OF_SNUM 28 92 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 93 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 94 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 95 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 96 #define CONFIG_SYS_FSL_RMU 97 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 98 99 #elif defined(CONFIG_MPC8569) 100 #define CONFIG_MAX_CPUS 1 101 #define CONFIG_SYS_FSL_NUM_LAWS 10 102 #define CONFIG_SYS_FSL_SEC_COMPAT 2 103 #define QE_MURAM_SIZE 0x20000UL 104 #define MAX_QE_RISC 4 105 #define QE_NUM_OF_SNUM 46 106 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 107 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 108 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 109 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 110 #define CONFIG_SYS_FSL_RMU 111 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 112 113 #elif defined(CONFIG_MPC8572) 114 #define CONFIG_MAX_CPUS 2 115 #define CONFIG_SYS_FSL_NUM_LAWS 12 116 #define CONFIG_SYS_FSL_SEC_COMPAT 2 117 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 118 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 119 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 120 121 #elif defined(CONFIG_P1010) 122 #define CONFIG_MAX_CPUS 1 123 #define CONFIG_FSL_SDHC_V2_3 124 #define CONFIG_SYS_FSL_NUM_LAWS 12 125 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 126 #define CONFIG_TSECV2 127 #define CONFIG_SYS_FSL_SEC_COMPAT 4 128 #define CONFIG_FSL_SATA_V2 129 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 130 #define CONFIG_NUM_DDR_CONTROLLERS 1 131 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 132 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 133 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 134 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 135 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 136 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 137 138 /* P1011 is single core version of P1020 */ 139 #elif defined(CONFIG_P1011) 140 #define CONFIG_MAX_CPUS 1 141 #define CONFIG_SYS_FSL_NUM_LAWS 12 142 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 143 #define CONFIG_TSECV2 144 #define CONFIG_FSL_PCIE_DISABLE_ASPM 145 #define CONFIG_SYS_FSL_SEC_COMPAT 2 146 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 147 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 148 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 149 150 /* P1012 is single core version of P1021 */ 151 #elif defined(CONFIG_P1012) 152 #define CONFIG_MAX_CPUS 1 153 #define CONFIG_SYS_FSL_NUM_LAWS 12 154 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 155 #define CONFIG_TSECV2 156 #define CONFIG_FSL_PCIE_DISABLE_ASPM 157 #define CONFIG_SYS_FSL_SEC_COMPAT 2 158 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 159 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 160 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 161 #define QE_MURAM_SIZE 0x6000UL 162 #define MAX_QE_RISC 1 163 #define QE_NUM_OF_SNUM 28 164 165 /* P1013 is single core version of P1022 */ 166 #elif defined(CONFIG_P1013) 167 #define CONFIG_MAX_CPUS 1 168 #define CONFIG_SYS_FSL_NUM_LAWS 12 169 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 170 #define CONFIG_TSECV2 171 #define CONFIG_SYS_FSL_SEC_COMPAT 2 172 #define CONFIG_FSL_SATA_V2 173 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 174 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 175 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 176 #define CONFIG_FSL_SATA_ERRATUM_A001 177 178 #elif defined(CONFIG_P1014) 179 #define CONFIG_MAX_CPUS 1 180 #define CONFIG_FSL_SDHC_V2_3 181 #define CONFIG_SYS_FSL_NUM_LAWS 12 182 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 183 #define CONFIG_TSECV2 184 #define CONFIG_SYS_FSL_SEC_COMPAT 4 185 #define CONFIG_FSL_SATA_V2 186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 187 #define CONFIG_NUM_DDR_CONTROLLERS 1 188 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 189 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 190 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 191 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 192 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 193 194 /* P1017 is single core version of P1023 */ 195 #elif defined(CONFIG_P1017) 196 #define CONFIG_MAX_CPUS 1 197 #define CONFIG_SYS_FSL_NUM_LAWS 12 198 #define CONFIG_SYS_FSL_SEC_COMPAT 4 199 #define CONFIG_SYS_NUM_FMAN 1 200 #define CONFIG_SYS_NUM_FM1_DTSEC 2 201 #define CONFIG_NUM_DDR_CONTROLLERS 1 202 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 203 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 204 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 205 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 206 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 207 208 #elif defined(CONFIG_P1020) 209 #define CONFIG_MAX_CPUS 2 210 #define CONFIG_SYS_FSL_NUM_LAWS 12 211 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 212 #define CONFIG_TSECV2 213 #define CONFIG_FSL_PCIE_DISABLE_ASPM 214 #define CONFIG_SYS_FSL_SEC_COMPAT 2 215 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 216 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 217 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 218 219 #elif defined(CONFIG_P1021) 220 #define CONFIG_MAX_CPUS 2 221 #define CONFIG_SYS_FSL_NUM_LAWS 12 222 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 223 #define CONFIG_TSECV2 224 #define CONFIG_FSL_PCIE_DISABLE_ASPM 225 #define CONFIG_SYS_FSL_SEC_COMPAT 2 226 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 227 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 228 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 229 #define QE_MURAM_SIZE 0x6000UL 230 #define MAX_QE_RISC 1 231 #define QE_NUM_OF_SNUM 28 232 233 #elif defined(CONFIG_P1022) 234 #define CONFIG_MAX_CPUS 2 235 #define CONFIG_SYS_FSL_NUM_LAWS 12 236 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 237 #define CONFIG_TSECV2 238 #define CONFIG_SYS_FSL_SEC_COMPAT 2 239 #define CONFIG_FSL_SATA_V2 240 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 241 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 242 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 243 #define CONFIG_FSL_SATA_ERRATUM_A001 244 245 #elif defined(CONFIG_P1023) 246 #define CONFIG_MAX_CPUS 2 247 #define CONFIG_SYS_FSL_NUM_LAWS 12 248 #define CONFIG_SYS_FSL_SEC_COMPAT 4 249 #define CONFIG_SYS_NUM_FMAN 1 250 #define CONFIG_SYS_NUM_FM1_DTSEC 2 251 #define CONFIG_NUM_DDR_CONTROLLERS 1 252 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 253 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 254 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 255 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 256 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 257 258 /* P1024 is lower end variant of P1020 */ 259 #elif defined(CONFIG_P1024) 260 #define CONFIG_MAX_CPUS 2 261 #define CONFIG_SYS_FSL_NUM_LAWS 12 262 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 263 #define CONFIG_TSECV2 264 #define CONFIG_FSL_PCIE_DISABLE_ASPM 265 #define CONFIG_SYS_FSL_SEC_COMPAT 2 266 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 267 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 268 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 269 270 /* P1025 is lower end variant of P1021 */ 271 #elif defined(CONFIG_P1025) 272 #define CONFIG_MAX_CPUS 2 273 #define CONFIG_SYS_FSL_NUM_LAWS 12 274 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 275 #define CONFIG_TSECV2 276 #define CONFIG_FSL_PCIE_DISABLE_ASPM 277 #define CONFIG_SYS_FSL_SEC_COMPAT 2 278 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 279 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 280 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 281 #define QE_MURAM_SIZE 0x6000UL 282 #define MAX_QE_RISC 1 283 #define QE_NUM_OF_SNUM 28 284 285 /* P2010 is single core version of P2020 */ 286 #elif defined(CONFIG_P2010) 287 #define CONFIG_MAX_CPUS 1 288 #define CONFIG_SYS_FSL_NUM_LAWS 12 289 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 290 #define CONFIG_SYS_FSL_SEC_COMPAT 2 291 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 292 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 293 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 294 295 #elif defined(CONFIG_P2020) 296 #define CONFIG_MAX_CPUS 2 297 #define CONFIG_SYS_FSL_NUM_LAWS 12 298 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 299 #define CONFIG_SYS_FSL_SEC_COMPAT 2 300 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 301 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 302 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 303 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 304 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 305 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 306 #define CONFIG_SYS_FSL_RMU 307 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 308 309 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 310 #define CONFIG_MAX_CPUS 4 311 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 312 #define CONFIG_SYS_FSL_NUM_LAWS 32 313 #define CONFIG_SYS_FSL_SEC_COMPAT 4 314 #define CONFIG_FSL_SATA_V2 315 #define CONFIG_SYS_NUM_FMAN 1 316 #define CONFIG_SYS_NUM_FM1_DTSEC 5 317 #define CONFIG_SYS_NUM_FM1_10GEC 1 318 #define CONFIG_NUM_DDR_CONTROLLERS 1 319 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 320 #define CONFIG_SYS_FSL_TBCLK_DIV 32 321 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 322 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 323 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 324 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 325 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 326 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 327 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 328 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 329 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 330 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 331 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 332 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 333 #define CONFIG_SYS_FSL_ERRATUM_A004510 334 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 335 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 336 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 337 338 #elif defined(CONFIG_PPC_P3041) 339 #define CONFIG_MAX_CPUS 4 340 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 341 #define CONFIG_SYS_FSL_NUM_LAWS 32 342 #define CONFIG_SYS_FSL_SEC_COMPAT 4 343 #define CONFIG_FSL_SATA_V2 344 #define CONFIG_SYS_NUM_FMAN 1 345 #define CONFIG_SYS_NUM_FM1_DTSEC 5 346 #define CONFIG_SYS_NUM_FM1_10GEC 1 347 #define CONFIG_NUM_DDR_CONTROLLERS 1 348 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 349 #define CONFIG_SYS_FSL_TBCLK_DIV 32 350 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 351 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 352 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 353 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 354 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 355 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 356 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 357 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 358 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 359 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 360 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 361 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 362 #define CONFIG_SYS_FSL_ERRATUM_A004510 363 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 364 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 365 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 366 367 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 368 #define CONFIG_MAX_CPUS 8 369 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 370 #define CONFIG_SYS_FSL_NUM_LAWS 32 371 #define CONFIG_SYS_FSL_SEC_COMPAT 4 372 #define CONFIG_SYS_NUM_FMAN 2 373 #define CONFIG_SYS_NUM_FM1_DTSEC 4 374 #define CONFIG_SYS_NUM_FM2_DTSEC 4 375 #define CONFIG_SYS_NUM_FM1_10GEC 1 376 #define CONFIG_SYS_NUM_FM2_10GEC 1 377 #define CONFIG_NUM_DDR_CONTROLLERS 2 378 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 379 #define CONFIG_SYS_FSL_TBCLK_DIV 16 380 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 381 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 382 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 383 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 384 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 385 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 386 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 387 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 388 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 389 #define CONFIG_SYS_P4080_ERRATUM_CPU22 390 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 391 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 392 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 393 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 394 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 395 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 396 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 397 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 398 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 399 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 400 #define CONFIG_SYS_FSL_RMU 401 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 402 #define CONFIG_SYS_FSL_ERRATUM_A004510 403 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 404 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 405 406 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 407 #define CONFIG_MAX_CPUS 2 408 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 409 #define CONFIG_SYS_FSL_NUM_LAWS 32 410 #define CONFIG_SYS_FSL_SEC_COMPAT 4 411 #define CONFIG_FSL_SATA_V2 412 #define CONFIG_SYS_NUM_FMAN 1 413 #define CONFIG_SYS_NUM_FM1_DTSEC 5 414 #define CONFIG_SYS_NUM_FM1_10GEC 1 415 #define CONFIG_NUM_DDR_CONTROLLERS 2 416 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 417 #define CONFIG_SYS_FSL_TBCLK_DIV 32 418 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 419 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 420 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 421 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 422 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 423 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 424 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 425 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 426 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 427 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 428 #define CONFIG_SYS_FSL_ERRATUM_A004510 429 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 430 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 431 432 #elif defined(CONFIG_BSC9131) 433 #define CONFIG_MAX_CPUS 1 434 #define CONFIG_FSL_SDHC_V2_3 435 #define CONFIG_SYS_FSL_NUM_LAWS 12 436 #define CONFIG_TSECV2 437 #define CONFIG_SYS_FSL_SEC_COMPAT 4 438 #define CONFIG_NUM_DDR_CONTROLLERS 1 439 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 440 #define CONFIG_NAND_FSL_IFC 441 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 442 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 443 444 #else 445 #error Processor type not defined for this platform 446 #endif 447 448 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 449 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 450 #endif 451 452 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 453