1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 /* 13 * This macro should be removed when we no longer care about backwards 14 * compatibility with older operating systems. 15 */ 16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 17 18 #include <fsl_ddrc_version.h> 19 #define CONFIG_SYS_FSL_DDR_BE 20 21 /* IP endianness */ 22 #define CONFIG_SYS_FSL_IFC_BE 23 #define CONFIG_SYS_FSL_SEC_BE 24 #define CONFIG_SYS_FSL_SFP_BE 25 #define CONFIG_SYS_FSL_SEC_MON_BE 26 27 #if defined(CONFIG_ARCH_MPC8536) 28 #define CONFIG_SYS_FSL_ERRATUM_A004508 29 #define CONFIG_SYS_FSL_ERRATUM_A005125 30 31 #elif defined(CONFIG_ARCH_MPC8540) 32 #define CONFIG_SYS_FSL_DDRC_GEN1 33 34 #elif defined(CONFIG_ARCH_MPC8541) 35 #define CONFIG_SYS_FSL_DDRC_GEN1 36 37 #elif defined(CONFIG_ARCH_MPC8544) 38 #define CONFIG_SYS_FSL_DDRC_GEN2 39 #define CONFIG_SYS_FSL_ERRATUM_A005125 40 41 #elif defined(CONFIG_ARCH_MPC8548) 42 #define CONFIG_SYS_FSL_DDRC_GEN2 43 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 44 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 45 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 46 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 47 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 48 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 49 #define CONFIG_SYS_FSL_RMU 50 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 51 #define CONFIG_SYS_FSL_ERRATUM_A005125 52 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 53 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 54 55 #elif defined(CONFIG_ARCH_MPC8555) 56 #define CONFIG_SYS_FSL_DDRC_GEN1 57 58 #elif defined(CONFIG_ARCH_MPC8560) 59 #define CONFIG_SYS_FSL_DDRC_GEN1 60 61 #elif defined(CONFIG_ARCH_MPC8568) 62 #define CONFIG_SYS_FSL_DDRC_GEN2 63 #define QE_MURAM_SIZE 0x10000UL 64 #define MAX_QE_RISC 2 65 #define QE_NUM_OF_SNUM 28 66 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 67 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 68 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 69 #define CONFIG_SYS_FSL_RMU 70 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 71 72 #elif defined(CONFIG_ARCH_MPC8569) 73 #define QE_MURAM_SIZE 0x20000UL 74 #define MAX_QE_RISC 4 75 #define QE_NUM_OF_SNUM 46 76 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 77 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 78 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 79 #define CONFIG_SYS_FSL_RMU 80 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 81 #define CONFIG_SYS_FSL_ERRATUM_A004508 82 #define CONFIG_SYS_FSL_ERRATUM_A005125 83 84 #elif defined(CONFIG_ARCH_MPC8572) 85 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 86 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 87 #define CONFIG_SYS_FSL_ERRATUM_A004508 88 #define CONFIG_SYS_FSL_ERRATUM_A005125 89 90 #elif defined(CONFIG_ARCH_P1010) 91 #define CONFIG_FSL_SDHC_V2_3 92 #define CONFIG_TSECV2 93 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 94 #define CONFIG_NUM_DDR_CONTROLLERS 1 95 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 96 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 97 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 98 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 99 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 100 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 101 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 102 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 103 #define CONFIG_SYS_FSL_ERRATUM_A005125 104 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 105 #define CONFIG_SYS_FSL_ERRATUM_A004508 106 #define CONFIG_SYS_FSL_ERRATUM_A007075 107 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 108 #define CONFIG_SYS_FSL_ERRATUM_A006261 109 #define CONFIG_SYS_FSL_ERRATUM_A004477 110 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 111 #define CONFIG_ESDHC_HC_BLK_ADDR 112 113 /* P1011 is single core version of P1020 */ 114 #elif defined(CONFIG_ARCH_P1011) 115 #define CONFIG_TSECV2 116 #define CONFIG_FSL_PCIE_DISABLE_ASPM 117 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 118 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 119 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 120 #define CONFIG_SYS_FSL_ERRATUM_A004508 121 #define CONFIG_SYS_FSL_ERRATUM_A005125 122 123 #elif defined(CONFIG_ARCH_P1020) 124 #define CONFIG_TSECV2 125 #define CONFIG_FSL_PCIE_DISABLE_ASPM 126 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 127 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 128 #define CONFIG_SYS_FSL_ERRATUM_A004508 129 #define CONFIG_SYS_FSL_ERRATUM_A005125 130 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 131 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 132 #endif 133 134 #elif defined(CONFIG_ARCH_P1021) 135 #define CONFIG_TSECV2 136 #define CONFIG_FSL_PCIE_DISABLE_ASPM 137 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 138 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 139 #define QE_MURAM_SIZE 0x6000UL 140 #define MAX_QE_RISC 1 141 #define QE_NUM_OF_SNUM 28 142 #define CONFIG_SYS_FSL_ERRATUM_A004508 143 #define CONFIG_SYS_FSL_ERRATUM_A005125 144 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 145 146 #elif defined(CONFIG_ARCH_P1022) 147 #define CONFIG_TSECV2 148 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 149 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 151 #define CONFIG_FSL_SATA_ERRATUM_A001 152 #define CONFIG_SYS_FSL_ERRATUM_A004508 153 #define CONFIG_SYS_FSL_ERRATUM_A005125 154 #define CONFIG_SYS_FSL_ERRATUM_A004477 155 156 #elif defined(CONFIG_ARCH_P1023) 157 #define CONFIG_SYS_NUM_FMAN 1 158 #define CONFIG_SYS_NUM_FM1_DTSEC 2 159 #define CONFIG_NUM_DDR_CONTROLLERS 1 160 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 161 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 162 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 163 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 164 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 165 #define CONFIG_SYS_FSL_ERRATUM_A004508 166 #define CONFIG_SYS_FSL_ERRATUM_A005125 167 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 168 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 169 170 /* P1024 is lower end variant of P1020 */ 171 #elif defined(CONFIG_ARCH_P1024) 172 #define CONFIG_TSECV2 173 #define CONFIG_FSL_PCIE_DISABLE_ASPM 174 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 175 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 176 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 177 #define CONFIG_SYS_FSL_ERRATUM_A004508 178 #define CONFIG_SYS_FSL_ERRATUM_A005125 179 180 /* P1025 is lower end variant of P1021 */ 181 #elif defined(CONFIG_ARCH_P1025) 182 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 183 #define CONFIG_TSECV2 184 #define CONFIG_FSL_PCIE_DISABLE_ASPM 185 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 187 #define QE_MURAM_SIZE 0x6000UL 188 #define MAX_QE_RISC 1 189 #define QE_NUM_OF_SNUM 28 190 #define CONFIG_SYS_FSL_ERRATUM_A004508 191 #define CONFIG_SYS_FSL_ERRATUM_A005125 192 193 #elif defined(CONFIG_ARCH_P2020) 194 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 195 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 196 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 197 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 198 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 199 #define CONFIG_SYS_FSL_RMU 200 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 201 #define CONFIG_SYS_FSL_ERRATUM_A004508 202 #define CONFIG_SYS_FSL_ERRATUM_A005125 203 #define CONFIG_SYS_FSL_ERRATUM_A004477 204 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 205 206 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ 207 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 208 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 209 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 210 #define CONFIG_SYS_NUM_FMAN 1 211 #define CONFIG_SYS_NUM_FM1_DTSEC 5 212 #define CONFIG_SYS_NUM_FM1_10GEC 1 213 #define CONFIG_NUM_DDR_CONTROLLERS 1 214 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 215 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 216 #define CONFIG_SYS_FSL_TBCLK_DIV 32 217 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 218 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 219 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 220 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 221 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 222 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 223 #define CONFIG_SYS_FSL_ERRATUM_USB14 224 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 225 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 226 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 227 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 228 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 229 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 230 #define CONFIG_SYS_FSL_ERRATUM_A004510 231 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 232 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 233 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 234 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 235 #define CONFIG_SYS_FSL_ERRATUM_A004849 236 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 237 #define CONFIG_SYS_FSL_ERRATUM_A006261 238 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 239 240 #elif defined(CONFIG_ARCH_P3041) 241 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 242 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 243 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 244 #define CONFIG_SYS_NUM_FMAN 1 245 #define CONFIG_SYS_NUM_FM1_DTSEC 5 246 #define CONFIG_SYS_NUM_FM1_10GEC 1 247 #define CONFIG_NUM_DDR_CONTROLLERS 1 248 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 249 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 250 #define CONFIG_SYS_FSL_TBCLK_DIV 32 251 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 252 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 253 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 254 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 255 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 256 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 257 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 258 #define CONFIG_SYS_FSL_ERRATUM_USB14 259 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 260 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 261 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 262 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 263 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 264 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 265 #define CONFIG_SYS_FSL_ERRATUM_A004510 266 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 267 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 268 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 269 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 270 #define CONFIG_SYS_FSL_ERRATUM_A004849 271 #define CONFIG_SYS_FSL_ERRATUM_A005812 272 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 273 #define CONFIG_SYS_FSL_ERRATUM_A006261 274 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 275 276 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ 277 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 278 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 279 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 280 #define CONFIG_SYS_NUM_FMAN 2 281 #define CONFIG_SYS_NUM_FM1_DTSEC 4 282 #define CONFIG_SYS_NUM_FM2_DTSEC 4 283 #define CONFIG_SYS_NUM_FM1_10GEC 1 284 #define CONFIG_SYS_NUM_FM2_10GEC 1 285 #define CONFIG_NUM_DDR_CONTROLLERS 2 286 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 287 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 288 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 289 #define CONFIG_SYS_FSL_TBCLK_DIV 16 290 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 291 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 292 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 293 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 294 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 295 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 296 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 297 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 298 #define CONFIG_SYS_P4080_ERRATUM_CPU22 299 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 300 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 301 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 302 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 303 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 304 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 305 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 306 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 307 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 308 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 309 #define CONFIG_SYS_FSL_RMU 310 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 311 #define CONFIG_SYS_FSL_ERRATUM_A004510 312 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 313 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 314 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 315 #define CONFIG_SYS_FSL_ERRATUM_A004849 316 #define CONFIG_SYS_FSL_ERRATUM_A004580 317 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 318 #define CONFIG_SYS_FSL_ERRATUM_A005812 319 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 320 #define CONFIG_SYS_FSL_ERRATUM_A007075 321 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 322 323 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ 324 #define CONFIG_SYS_PPC64 /* 64-bit core */ 325 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 326 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 327 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 328 #define CONFIG_SYS_NUM_FMAN 1 329 #define CONFIG_SYS_NUM_FM1_DTSEC 5 330 #define CONFIG_SYS_NUM_FM1_10GEC 1 331 #define CONFIG_NUM_DDR_CONTROLLERS 2 332 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 333 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 334 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 335 #define CONFIG_SYS_FSL_TBCLK_DIV 32 336 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 337 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 338 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 339 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 340 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 341 #define CONFIG_SYS_FSL_ERRATUM_USB14 342 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 343 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 344 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 345 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 346 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 347 #define CONFIG_SYS_FSL_ERRATUM_A004510 348 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 349 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 350 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 351 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 352 #define CONFIG_SYS_FSL_ERRATUM_A006261 353 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 354 355 #elif defined(CONFIG_ARCH_P5040) 356 #define CONFIG_SYS_PPC64 357 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 358 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 359 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 360 #define CONFIG_SYS_NUM_FMAN 2 361 #define CONFIG_SYS_NUM_FM1_DTSEC 5 362 #define CONFIG_SYS_NUM_FM1_10GEC 1 363 #define CONFIG_SYS_NUM_FM2_DTSEC 5 364 #define CONFIG_SYS_NUM_FM2_10GEC 1 365 #define CONFIG_NUM_DDR_CONTROLLERS 2 366 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 367 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 368 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 369 #define CONFIG_SYS_FSL_TBCLK_DIV 16 370 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 371 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 372 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 373 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 374 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 375 #define CONFIG_SYS_FSL_ERRATUM_USB14 376 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 377 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 378 #define CONFIG_SYS_FSL_ERRATUM_A004699 379 #define CONFIG_SYS_FSL_ERRATUM_A004510 380 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 381 #define CONFIG_SYS_FSL_ERRATUM_A006261 382 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 383 #define CONFIG_SYS_FSL_ERRATUM_A005812 384 385 #elif defined(CONFIG_ARCH_BSC9131) 386 #define CONFIG_FSL_SDHC_V2_3 387 #define CONFIG_TSECV2 388 #define CONFIG_NUM_DDR_CONTROLLERS 1 389 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 390 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 391 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 392 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 393 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 394 #define CONFIG_NAND_FSL_IFC 395 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 396 #define CONFIG_SYS_FSL_ERRATUM_A005125 397 #define CONFIG_SYS_FSL_ERRATUM_A004477 398 #define CONFIG_ESDHC_HC_BLK_ADDR 399 400 #elif defined(CONFIG_ARCH_BSC9132) 401 #define CONFIG_FSL_SDHC_V2_3 402 #define CONFIG_TSECV2 403 #define CONFIG_NUM_DDR_CONTROLLERS 2 404 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 405 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 406 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 407 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 408 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 409 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 410 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 411 #define CONFIG_NAND_FSL_IFC 412 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 413 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 414 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 415 #define CONFIG_SYS_FSL_ERRATUM_A005125 416 #define CONFIG_SYS_FSL_ERRATUM_A005434 417 #define CONFIG_SYS_FSL_ERRATUM_A004477 418 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 419 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 420 #define CONFIG_ESDHC_HC_BLK_ADDR 421 422 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) 423 #define CONFIG_E6500 424 #define CONFIG_SYS_PPC64 /* 64-bit core */ 425 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 426 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 427 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 428 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 429 #ifdef CONFIG_ARCH_T4240 430 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 431 #define CONFIG_SYS_NUM_FM1_DTSEC 8 432 #define CONFIG_SYS_NUM_FM1_10GEC 2 433 #define CONFIG_SYS_NUM_FM2_DTSEC 8 434 #define CONFIG_SYS_NUM_FM2_10GEC 2 435 #define CONFIG_NUM_DDR_CONTROLLERS 3 436 #define CONFIG_SYS_FSL_ERRATUM_A006261 437 #else 438 #define CONFIG_SYS_NUM_FM1_DTSEC 6 439 #define CONFIG_SYS_NUM_FM1_10GEC 1 440 #define CONFIG_SYS_NUM_FM2_DTSEC 8 441 #define CONFIG_SYS_NUM_FM2_10GEC 1 442 #define CONFIG_NUM_DDR_CONTROLLERS 2 443 #if defined(CONFIG_ARCH_T4160) 444 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 445 #endif 446 #endif 447 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 448 #define CONFIG_SYS_FSL_SRDS_1 449 #define CONFIG_SYS_FSL_SRDS_2 450 #define CONFIG_SYS_FSL_SRDS_3 451 #define CONFIG_SYS_FSL_SRDS_4 452 #define CONFIG_SYS_NUM_FMAN 2 453 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 454 #define CONFIG_SYS_PME_CLK 0 455 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 456 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 457 #define CONFIG_SYS_FMAN_V3 458 #define CONFIG_SYS_FM1_CLK 3 459 #define CONFIG_SYS_FM2_CLK 3 460 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 461 #define CONFIG_SYS_FSL_TBCLK_DIV 16 462 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 463 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 464 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 465 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 466 #define CONFIG_SYS_FSL_SRIO_LIODN 467 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 468 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 469 #define CONFIG_SYS_FSL_ERRATUM_A004468 470 #define CONFIG_SYS_FSL_ERRATUM_A005871 471 #define CONFIG_SYS_FSL_ERRATUM_A006379 472 #define CONFIG_SYS_FSL_ERRATUM_A007186 473 #define CONFIG_SYS_FSL_ERRATUM_A006593 474 #define CONFIG_SYS_FSL_ERRATUM_A007798 475 #define CONFIG_SYS_FSL_ERRATUM_A009942 476 #define CONFIG_SYS_FSL_SFP_VER_3_0 477 #define CONFIG_SYS_FSL_PCI_VER_3_X 478 479 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) 480 #define CONFIG_E6500 481 #define CONFIG_SYS_PPC64 /* 64-bit core */ 482 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 483 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 484 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 485 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 486 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 487 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 488 #define CONFIG_SYS_FSL_SRDS_1 489 #define CONFIG_SYS_FSL_SRDS_2 490 #define CONFIG_SYS_MAPLE 491 #define CONFIG_SYS_CPRI 492 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 493 #define CONFIG_SYS_NUM_FMAN 1 494 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 495 #define CONFIG_SYS_FM1_CLK 0 496 #define CONFIG_SYS_CPRI_CLK 3 497 #define CONFIG_SYS_ULB_CLK 4 498 #define CONFIG_SYS_ETVPE_CLK 1 499 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 500 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 501 #define CONFIG_SYS_FMAN_V3 502 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 503 #define CONFIG_SYS_FSL_TBCLK_DIV 16 504 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 505 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 506 #define CONFIG_SYS_FSL_ERRATUM_A005871 507 #define CONFIG_SYS_FSL_ERRATUM_A006379 508 #define CONFIG_SYS_FSL_ERRATUM_A007186 509 #define CONFIG_SYS_FSL_ERRATUM_A006593 510 #define CONFIG_SYS_FSL_ERRATUM_A007075 511 #define CONFIG_SYS_FSL_ERRATUM_A006475 512 #define CONFIG_SYS_FSL_ERRATUM_A006384 513 #define CONFIG_SYS_FSL_ERRATUM_A007212 514 #define CONFIG_SYS_FSL_ERRATUM_A004477 515 #define CONFIG_SYS_FSL_ERRATUM_A009942 516 #define CONFIG_SYS_FSL_SFP_VER_3_0 517 518 #ifdef CONFIG_ARCH_B4860 519 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 520 #define CONFIG_MAX_DSP_CPUS 12 521 #define CONFIG_NUM_DSP_CPUS 6 522 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 523 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 524 #define CONFIG_SYS_NUM_FM1_DTSEC 6 525 #define CONFIG_SYS_NUM_FM1_10GEC 2 526 #define CONFIG_NUM_DDR_CONTROLLERS 2 527 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 528 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 529 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 530 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 531 #define CONFIG_SYS_FSL_SRIO_LIODN 532 #else 533 #define CONFIG_MAX_DSP_CPUS 2 534 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 535 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 536 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 537 #define CONFIG_SYS_NUM_FM1_DTSEC 4 538 #define CONFIG_SYS_NUM_FM1_10GEC 0 539 #define CONFIG_NUM_DDR_CONTROLLERS 1 540 #endif 541 542 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\ 543 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 544 #define CONFIG_E5500 545 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 546 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 547 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 548 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 549 #ifdef CONFIG_SYS_FSL_DDR4 550 #define CONFIG_SYS_FSL_DDRC_GEN4 551 #endif 552 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 553 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 554 #define CONFIG_SYS_FSL_SRDS_1 555 #define CONFIG_SYS_NUM_FMAN 1 556 #define CONFIG_SYS_NUM_FM1_DTSEC 5 557 #define CONFIG_NUM_DDR_CONTROLLERS 1 558 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 559 #define CONFIG_PME_PLAT_CLK_DIV 2 560 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 561 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 562 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 563 #define CONFIG_SYS_FSL_ERRATUM_A008044 564 #define CONFIG_SYS_FMAN_V3 565 #define CONFIG_FM_PLAT_CLK_DIV 1 566 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 567 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 568 per rcw field value */ 569 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 570 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 571 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 572 #define CONFIG_SYS_FSL_TBCLK_DIV 16 573 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 574 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 575 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 576 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 577 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 578 #define QE_MURAM_SIZE 0x6000UL 579 #define MAX_QE_RISC 1 580 #define QE_NUM_OF_SNUM 28 581 #define CONFIG_SYS_FSL_SFP_VER_3_0 582 #define CONFIG_SYS_FSL_ERRATUM_A008378 583 #define CONFIG_SYS_FSL_ERRATUM_A009663 584 #define CONFIG_SYS_FSL_ERRATUM_A009942 585 586 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\ 587 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 588 #define CONFIG_E5500 589 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 590 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 591 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 592 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 593 #define CONFIG_SYS_FMAN_V3 594 #ifdef CONFIG_SYS_FSL_DDR4 595 #define CONFIG_SYS_FSL_DDRC_GEN4 596 #endif 597 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 598 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 599 #define CONFIG_SYS_FSL_SRDS_1 600 #define CONFIG_SYS_NUM_FMAN 1 601 #define CONFIG_SYS_NUM_FM1_DTSEC 4 602 #define CONFIG_SYS_NUM_FM1_10GEC 1 603 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 604 #define CONFIG_NUM_DDR_CONTROLLERS 1 605 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 606 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 607 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 608 #define CONFIG_SYS_FM1_CLK 0 609 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 610 per rcw field value */ 611 #define CONFIG_QBMAN_CLK_DIV 1 612 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 613 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 614 #define CONFIG_SYS_FSL_TBCLK_DIV 16 615 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 616 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 617 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 618 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 619 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 620 #define QE_MURAM_SIZE 0x6000UL 621 #define MAX_QE_RISC 1 622 #define QE_NUM_OF_SNUM 28 623 #define CONFIG_SYS_FSL_SFP_VER_3_0 624 #define CONFIG_SYS_FSL_ERRATUM_A008378 625 #define CONFIG_SYS_FSL_ERRATUM_A009663 626 #define CONFIG_SYS_FSL_ERRATUM_A009942 627 628 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) 629 #define CONFIG_E6500 630 #define CONFIG_SYS_PPC64 /* 64-bit core */ 631 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 632 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 633 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 634 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 635 #define CONFIG_SYS_FSL_QMAN_V3 636 #define CONFIG_SYS_NUM_FMAN 1 637 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 638 #define CONFIG_SYS_FSL_SRDS_1 639 #define CONFIG_SYS_FSL_PCI_VER_3_X 640 #if defined(CONFIG_ARCH_T2080) 641 #define CONFIG_SYS_NUM_FM1_DTSEC 8 642 #define CONFIG_SYS_NUM_FM1_10GEC 4 643 #define CONFIG_SYS_FSL_SRDS_2 644 #define CONFIG_SYS_FSL_SRIO_LIODN 645 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 646 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 647 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 648 #elif defined(CONFIG_ARCH_T2081) 649 #define CONFIG_SYS_NUM_FM1_DTSEC 6 650 #define CONFIG_SYS_NUM_FM1_10GEC 2 651 #endif 652 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 653 #define CONFIG_NUM_DDR_CONTROLLERS 1 654 #define CONFIG_PME_PLAT_CLK_DIV 1 655 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 656 #define CONFIG_SYS_FM1_CLK 0 657 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 658 per rcw field value */ 659 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 660 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 661 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 662 #define CONFIG_SYS_FMAN_V3 663 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 664 #define CONFIG_SYS_FSL_TBCLK_DIV 16 665 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 666 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 667 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 668 #define CONFIG_SYS_FSL_ERRATUM_A007212 669 #define CONFIG_SYS_FSL_SFP_VER_3_0 670 #define CONFIG_SYS_FSL_ISBC_VER 2 671 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 672 #define CONFIG_SYS_FSL_ERRATUM_A006593 673 #define CONFIG_SYS_FSL_ERRATUM_A007186 674 #define CONFIG_SYS_FSL_ERRATUM_A006379 675 #define CONFIG_SYS_FSL_ERRATUM_A009942 676 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 677 #define CONFIG_SYS_FSL_SFP_VER_3_0 678 679 680 #elif defined(CONFIG_ARCH_C29X) 681 #define CONFIG_FSL_SDHC_V2_3 682 #define CONFIG_TSECV2_1 683 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 684 #define CONFIG_NUM_DDR_CONTROLLERS 1 685 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 686 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 687 #define CONFIG_SYS_FSL_ERRATUM_A005125 688 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 689 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 690 691 #elif defined(CONFIG_ARCH_QEMU_E500) 692 693 #else 694 #error Processor type not defined for this platform 695 #endif 696 697 #ifdef CONFIG_E6500 698 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 699 #else 700 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 701 #endif 702 703 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 704 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 705 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ 706 !defined(CONFIG_SYS_FSL_DDRC_GEN4) 707 #define CONFIG_SYS_FSL_DDRC_GEN3 708 #endif 709 710 #if !defined(CONFIG_ARCH_C29X) 711 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 712 #endif 713 714 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 715