1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 28 #endif 29 30 /* 31 * This macro should be removed when we no longer care about backwards 32 * compatibility with older operating systems. 33 */ 34 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 35 36 #define FSL_DDR_VER_4_7 47 37 38 /* Number of TLB CAM entries we have on FSL Book-E chips */ 39 #if defined(CONFIG_E500MC) 40 #define CONFIG_SYS_NUM_TLBCAMS 64 41 #elif defined(CONFIG_E500) 42 #define CONFIG_SYS_NUM_TLBCAMS 16 43 #endif 44 45 #if defined(CONFIG_MPC8536) 46 #define CONFIG_MAX_CPUS 1 47 #define CONFIG_SYS_FSL_NUM_LAWS 12 48 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 49 #define CONFIG_SYS_FSL_SEC_COMPAT 2 50 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 51 52 #elif defined(CONFIG_MPC8540) 53 #define CONFIG_MAX_CPUS 1 54 #define CONFIG_SYS_FSL_NUM_LAWS 8 55 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 56 57 #elif defined(CONFIG_MPC8541) 58 #define CONFIG_MAX_CPUS 1 59 #define CONFIG_SYS_FSL_NUM_LAWS 8 60 #define CONFIG_SYS_FSL_SEC_COMPAT 2 61 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 62 63 #elif defined(CONFIG_MPC8544) 64 #define CONFIG_MAX_CPUS 1 65 #define CONFIG_SYS_FSL_NUM_LAWS 10 66 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 67 #define CONFIG_SYS_FSL_SEC_COMPAT 2 68 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 69 70 #elif defined(CONFIG_MPC8548) 71 #define CONFIG_MAX_CPUS 1 72 #define CONFIG_SYS_FSL_NUM_LAWS 10 73 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 74 #define CONFIG_SYS_FSL_SEC_COMPAT 2 75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 76 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 77 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 78 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 79 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 80 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 81 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 82 #define CONFIG_SYS_FSL_RMU 83 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 84 85 #elif defined(CONFIG_MPC8555) 86 #define CONFIG_MAX_CPUS 1 87 #define CONFIG_SYS_FSL_NUM_LAWS 8 88 #define CONFIG_SYS_FSL_SEC_COMPAT 2 89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 90 91 #elif defined(CONFIG_MPC8560) 92 #define CONFIG_MAX_CPUS 1 93 #define CONFIG_SYS_FSL_NUM_LAWS 8 94 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 95 96 #elif defined(CONFIG_MPC8568) 97 #define CONFIG_MAX_CPUS 1 98 #define CONFIG_SYS_FSL_NUM_LAWS 10 99 #define CONFIG_SYS_FSL_SEC_COMPAT 2 100 #define QE_MURAM_SIZE 0x10000UL 101 #define MAX_QE_RISC 2 102 #define QE_NUM_OF_SNUM 28 103 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 104 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 105 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 106 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 107 #define CONFIG_SYS_FSL_RMU 108 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 109 110 #elif defined(CONFIG_MPC8569) 111 #define CONFIG_MAX_CPUS 1 112 #define CONFIG_SYS_FSL_NUM_LAWS 10 113 #define CONFIG_SYS_FSL_SEC_COMPAT 2 114 #define QE_MURAM_SIZE 0x20000UL 115 #define MAX_QE_RISC 4 116 #define QE_NUM_OF_SNUM 46 117 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 118 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 119 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 120 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 121 #define CONFIG_SYS_FSL_RMU 122 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 123 124 #elif defined(CONFIG_MPC8572) 125 #define CONFIG_MAX_CPUS 2 126 #define CONFIG_SYS_FSL_NUM_LAWS 12 127 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 128 #define CONFIG_SYS_FSL_SEC_COMPAT 2 129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 130 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 131 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 132 133 #elif defined(CONFIG_P1010) 134 #define CONFIG_MAX_CPUS 1 135 #define CONFIG_FSL_SDHC_V2_3 136 #define CONFIG_SYS_FSL_NUM_LAWS 12 137 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 138 #define CONFIG_TSECV2 139 #define CONFIG_SYS_FSL_SEC_COMPAT 4 140 #define CONFIG_FSL_SATA_V2 141 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 142 #define CONFIG_NUM_DDR_CONTROLLERS 1 143 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 144 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 145 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 146 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 147 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 148 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 149 150 /* P1011 is single core version of P1020 */ 151 #elif defined(CONFIG_P1011) 152 #define CONFIG_MAX_CPUS 1 153 #define CONFIG_SYS_FSL_NUM_LAWS 12 154 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 155 #define CONFIG_TSECV2 156 #define CONFIG_FSL_PCIE_DISABLE_ASPM 157 #define CONFIG_SYS_FSL_SEC_COMPAT 2 158 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 159 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 160 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 161 162 /* P1012 is single core version of P1021 */ 163 #elif defined(CONFIG_P1012) 164 #define CONFIG_MAX_CPUS 1 165 #define CONFIG_SYS_FSL_NUM_LAWS 12 166 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 167 #define CONFIG_TSECV2 168 #define CONFIG_FSL_PCIE_DISABLE_ASPM 169 #define CONFIG_SYS_FSL_SEC_COMPAT 2 170 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 171 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 172 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 173 #define QE_MURAM_SIZE 0x6000UL 174 #define MAX_QE_RISC 1 175 #define QE_NUM_OF_SNUM 28 176 177 /* P1013 is single core version of P1022 */ 178 #elif defined(CONFIG_P1013) 179 #define CONFIG_MAX_CPUS 1 180 #define CONFIG_SYS_FSL_NUM_LAWS 12 181 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 182 #define CONFIG_TSECV2 183 #define CONFIG_SYS_FSL_SEC_COMPAT 2 184 #define CONFIG_FSL_SATA_V2 185 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 186 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 187 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 188 #define CONFIG_FSL_SATA_ERRATUM_A001 189 190 #elif defined(CONFIG_P1014) 191 #define CONFIG_MAX_CPUS 1 192 #define CONFIG_FSL_SDHC_V2_3 193 #define CONFIG_SYS_FSL_NUM_LAWS 12 194 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 195 #define CONFIG_TSECV2 196 #define CONFIG_SYS_FSL_SEC_COMPAT 4 197 #define CONFIG_FSL_SATA_V2 198 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 199 #define CONFIG_NUM_DDR_CONTROLLERS 1 200 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 201 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 202 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 203 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 204 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 205 206 /* P1017 is single core version of P1023 */ 207 #elif defined(CONFIG_P1017) 208 #define CONFIG_MAX_CPUS 1 209 #define CONFIG_SYS_FSL_NUM_LAWS 12 210 #define CONFIG_SYS_FSL_SEC_COMPAT 4 211 #define CONFIG_SYS_NUM_FMAN 1 212 #define CONFIG_SYS_NUM_FM1_DTSEC 2 213 #define CONFIG_NUM_DDR_CONTROLLERS 1 214 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 215 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 216 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 217 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 218 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 219 220 #elif defined(CONFIG_P1020) 221 #define CONFIG_MAX_CPUS 2 222 #define CONFIG_SYS_FSL_NUM_LAWS 12 223 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 224 #define CONFIG_TSECV2 225 #define CONFIG_FSL_PCIE_DISABLE_ASPM 226 #define CONFIG_SYS_FSL_SEC_COMPAT 2 227 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 228 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 229 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 230 231 #elif defined(CONFIG_P1021) 232 #define CONFIG_MAX_CPUS 2 233 #define CONFIG_SYS_FSL_NUM_LAWS 12 234 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 235 #define CONFIG_TSECV2 236 #define CONFIG_FSL_PCIE_DISABLE_ASPM 237 #define CONFIG_SYS_FSL_SEC_COMPAT 2 238 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 239 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 240 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 241 #define QE_MURAM_SIZE 0x6000UL 242 #define MAX_QE_RISC 1 243 #define QE_NUM_OF_SNUM 28 244 245 #elif defined(CONFIG_P1022) 246 #define CONFIG_MAX_CPUS 2 247 #define CONFIG_SYS_FSL_NUM_LAWS 12 248 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 249 #define CONFIG_TSECV2 250 #define CONFIG_SYS_FSL_SEC_COMPAT 2 251 #define CONFIG_FSL_SATA_V2 252 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 253 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 254 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 255 #define CONFIG_FSL_SATA_ERRATUM_A001 256 257 #elif defined(CONFIG_P1023) 258 #define CONFIG_MAX_CPUS 2 259 #define CONFIG_SYS_FSL_NUM_LAWS 12 260 #define CONFIG_SYS_FSL_SEC_COMPAT 4 261 #define CONFIG_SYS_NUM_FMAN 1 262 #define CONFIG_SYS_NUM_FM1_DTSEC 2 263 #define CONFIG_NUM_DDR_CONTROLLERS 1 264 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 265 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 266 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 267 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 268 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 269 270 /* P1024 is lower end variant of P1020 */ 271 #elif defined(CONFIG_P1024) 272 #define CONFIG_MAX_CPUS 2 273 #define CONFIG_SYS_FSL_NUM_LAWS 12 274 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 275 #define CONFIG_TSECV2 276 #define CONFIG_FSL_PCIE_DISABLE_ASPM 277 #define CONFIG_SYS_FSL_SEC_COMPAT 2 278 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 279 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 280 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 281 282 /* P1025 is lower end variant of P1021 */ 283 #elif defined(CONFIG_P1025) 284 #define CONFIG_MAX_CPUS 2 285 #define CONFIG_SYS_FSL_NUM_LAWS 12 286 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 287 #define CONFIG_TSECV2 288 #define CONFIG_FSL_PCIE_DISABLE_ASPM 289 #define CONFIG_SYS_FSL_SEC_COMPAT 2 290 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 291 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 292 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 293 #define QE_MURAM_SIZE 0x6000UL 294 #define MAX_QE_RISC 1 295 #define QE_NUM_OF_SNUM 28 296 297 /* P2010 is single core version of P2020 */ 298 #elif defined(CONFIG_P2010) 299 #define CONFIG_MAX_CPUS 1 300 #define CONFIG_SYS_FSL_NUM_LAWS 12 301 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 302 #define CONFIG_SYS_FSL_SEC_COMPAT 2 303 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 304 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 305 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 306 307 #elif defined(CONFIG_P2020) 308 #define CONFIG_MAX_CPUS 2 309 #define CONFIG_SYS_FSL_NUM_LAWS 12 310 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 311 #define CONFIG_SYS_FSL_SEC_COMPAT 2 312 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 313 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 314 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 315 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 316 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 317 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 318 #define CONFIG_SYS_FSL_RMU 319 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 320 321 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 322 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 323 #define CONFIG_MAX_CPUS 4 324 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 325 #define CONFIG_SYS_FSL_NUM_LAWS 32 326 #define CONFIG_SYS_FSL_SEC_COMPAT 4 327 #define CONFIG_FSL_SATA_V2 328 #define CONFIG_SYS_NUM_FMAN 1 329 #define CONFIG_SYS_NUM_FM1_DTSEC 5 330 #define CONFIG_SYS_NUM_FM1_10GEC 1 331 #define CONFIG_NUM_DDR_CONTROLLERS 1 332 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 333 #define CONFIG_SYS_FSL_TBCLK_DIV 32 334 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 335 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 336 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 337 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 338 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 339 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 340 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 341 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 342 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 343 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 344 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 345 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 346 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 347 #define CONFIG_SYS_FSL_ERRATUM_A004510 348 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 349 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 350 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 351 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 352 #define CONFIG_SYS_FSL_ERRATUM_A004849 353 354 #elif defined(CONFIG_PPC_P3041) 355 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 356 #define CONFIG_MAX_CPUS 4 357 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 358 #define CONFIG_SYS_FSL_NUM_LAWS 32 359 #define CONFIG_SYS_FSL_SEC_COMPAT 4 360 #define CONFIG_FSL_SATA_V2 361 #define CONFIG_SYS_NUM_FMAN 1 362 #define CONFIG_SYS_NUM_FM1_DTSEC 5 363 #define CONFIG_SYS_NUM_FM1_10GEC 1 364 #define CONFIG_NUM_DDR_CONTROLLERS 1 365 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 366 #define CONFIG_SYS_FSL_TBCLK_DIV 32 367 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 368 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 369 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 370 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 371 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 372 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 373 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 374 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 375 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 376 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 377 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 378 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 379 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 380 #define CONFIG_SYS_FSL_ERRATUM_A004510 381 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 382 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 383 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 384 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 385 #define CONFIG_SYS_FSL_ERRATUM_A004849 386 387 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 388 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 389 #define CONFIG_MAX_CPUS 8 390 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 391 #define CONFIG_SYS_FSL_NUM_LAWS 32 392 #define CONFIG_SYS_FSL_SEC_COMPAT 4 393 #define CONFIG_SYS_NUM_FMAN 2 394 #define CONFIG_SYS_NUM_FM1_DTSEC 4 395 #define CONFIG_SYS_NUM_FM2_DTSEC 4 396 #define CONFIG_SYS_NUM_FM1_10GEC 1 397 #define CONFIG_SYS_NUM_FM2_10GEC 1 398 #define CONFIG_NUM_DDR_CONTROLLERS 2 399 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 400 #define CONFIG_SYS_FSL_TBCLK_DIV 16 401 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 402 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 403 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 404 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 405 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 406 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 407 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 408 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 409 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 410 #define CONFIG_SYS_P4080_ERRATUM_CPU22 411 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 412 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 413 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 414 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 415 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 416 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 417 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 418 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 419 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 420 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 421 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 422 #define CONFIG_SYS_FSL_RMU 423 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 424 #define CONFIG_SYS_FSL_ERRATUM_A004510 425 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 426 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 427 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 428 #define CONFIG_SYS_FSL_ERRATUM_A004849 429 430 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 431 #define CONFIG_SYS_PPC64 /* 64-bit core */ 432 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 433 #define CONFIG_MAX_CPUS 2 434 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 435 #define CONFIG_SYS_FSL_NUM_LAWS 32 436 #define CONFIG_SYS_FSL_SEC_COMPAT 4 437 #define CONFIG_FSL_SATA_V2 438 #define CONFIG_SYS_NUM_FMAN 1 439 #define CONFIG_SYS_NUM_FM1_DTSEC 5 440 #define CONFIG_SYS_NUM_FM1_10GEC 1 441 #define CONFIG_NUM_DDR_CONTROLLERS 2 442 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 443 #define CONFIG_SYS_FSL_TBCLK_DIV 32 444 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 445 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 446 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 447 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 448 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 449 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 450 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 451 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 452 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 453 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 454 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 455 #define CONFIG_SYS_FSL_ERRATUM_A004510 456 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 457 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 458 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 459 460 #elif defined(CONFIG_PPC_P5040) 461 #define CONFIG_SYS_PPC64 462 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 463 #define CONFIG_MAX_CPUS 4 464 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 465 #define CONFIG_SYS_FSL_NUM_LAWS 32 466 #define CONFIG_SYS_FSL_SEC_COMPAT 4 467 #define CONFIG_SYS_NUM_FMAN 2 468 #define CONFIG_SYS_NUM_FM1_DTSEC 5 469 #define CONFIG_SYS_NUM_FM1_10GEC 1 470 #define CONFIG_SYS_NUM_FM2_DTSEC 5 471 #define CONFIG_SYS_NUM_FM2_10GEC 1 472 #define CONFIG_NUM_DDR_CONTROLLERS 2 473 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 474 #define CONFIG_SYS_FSL_TBCLK_DIV 16 475 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 476 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 477 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 478 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 479 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 480 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 481 #define CONFIG_SYS_FSL_ERRATUM_USB138 482 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 483 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 484 #define CONFIG_SYS_FSL_ERRATUM_A004699 485 #define CONFIG_SYS_FSL_ERRATUM_A004510 486 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 487 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 488 489 #elif defined(CONFIG_BSC9131) 490 #define CONFIG_MAX_CPUS 1 491 #define CONFIG_FSL_SDHC_V2_3 492 #define CONFIG_SYS_FSL_NUM_LAWS 12 493 #define CONFIG_TSECV2 494 #define CONFIG_SYS_FSL_SEC_COMPAT 4 495 #define CONFIG_NUM_DDR_CONTROLLERS 1 496 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 497 #define CONFIG_NAND_FSL_IFC 498 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 499 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 500 501 #elif defined(CONFIG_PPC_T4240) 502 #define CONFIG_SYS_PPC64 /* 64-bit core */ 503 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 504 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 505 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 506 #define CONFIG_MAX_CPUS 12 507 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 508 #define CONFIG_SYS_FSL_NUM_LAWS 32 509 #define CONFIG_SYS_FSL_SRDS_3 510 #define CONFIG_SYS_FSL_SRDS_4 511 #define CONFIG_SYS_FSL_SEC_COMPAT 4 512 #define CONFIG_SYS_NUM_FMAN 2 513 #define CONFIG_SYS_NUM_FM1_DTSEC 8 514 #define CONFIG_SYS_NUM_FM1_10GEC 2 515 #define CONFIG_SYS_NUM_FM2_DTSEC 8 516 #define CONFIG_SYS_NUM_FM2_10GEC 2 517 #define CONFIG_NUM_DDR_CONTROLLERS 3 518 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 519 #define CONFIG_SYS_FMAN_V3 520 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 521 #define CONFIG_SYS_FSL_TBCLK_DIV 16 522 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 523 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 524 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 525 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 526 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 527 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 528 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 529 #define CONFIG_SYS_FSL_ERRATUM_A004468 530 #define CONFIG_SYS_FSL_ERRATUM_A_004934 531 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 532 533 #elif defined(CONFIG_PPC_B4860) 534 #define CONFIG_SYS_PPC64 /* 64-bit core */ 535 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 536 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 537 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 538 #define CONFIG_MAX_CPUS 4 539 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 540 #define CONFIG_SYS_FSL_NUM_LAWS 32 541 #define CONFIG_SYS_FSL_SEC_COMPAT 4 542 #define CONFIG_SYS_NUM_FMAN 1 543 #define CONFIG_SYS_NUM_FM1_DTSEC 6 544 #define CONFIG_SYS_NUM_FM1_10GEC 2 545 #define CONFIG_NUM_DDR_CONTROLLERS 1 546 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 547 #define CONFIG_SYS_FMAN_V3 548 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 549 #define CONFIG_SYS_FSL_TBCLK_DIV 16 550 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 551 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 552 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 553 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 554 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 555 #define CONFIG_SYS_FSL_ERRATUM_A_004934 556 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 557 558 #else 559 #error Processor type not defined for this platform 560 #endif 561 562 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 563 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 564 #endif 565 566 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 567