1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 /* 13 * This macro should be removed when we no longer care about backwards 14 * compatibility with older operating systems. 15 */ 16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 17 18 #include <fsl_ddrc_version.h> 19 20 /* IP endianness */ 21 #define CONFIG_SYS_FSL_IFC_BE 22 #define CONFIG_SYS_FSL_SFP_BE 23 #define CONFIG_SYS_FSL_SEC_MON_BE 24 25 #if defined(CONFIG_ARCH_MPC8536) 26 27 #elif defined(CONFIG_ARCH_MPC8540) 28 29 #elif defined(CONFIG_ARCH_MPC8541) 30 31 #elif defined(CONFIG_ARCH_MPC8544) 32 33 #elif defined(CONFIG_ARCH_MPC8548) 34 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 35 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 36 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 37 #define CONFIG_SYS_FSL_RMU 38 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 39 40 #elif defined(CONFIG_ARCH_MPC8555) 41 42 #elif defined(CONFIG_ARCH_MPC8560) 43 44 #elif defined(CONFIG_ARCH_MPC8568) 45 #define QE_MURAM_SIZE 0x10000UL 46 #define MAX_QE_RISC 2 47 #define QE_NUM_OF_SNUM 28 48 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 49 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 50 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 51 #define CONFIG_SYS_FSL_RMU 52 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 53 54 #elif defined(CONFIG_ARCH_MPC8569) 55 #define QE_MURAM_SIZE 0x20000UL 56 #define MAX_QE_RISC 4 57 #define QE_NUM_OF_SNUM 46 58 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 59 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 60 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 61 #define CONFIG_SYS_FSL_RMU 62 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 63 64 #elif defined(CONFIG_ARCH_MPC8572) 65 66 #elif defined(CONFIG_ARCH_P1010) 67 #define CONFIG_FSL_SDHC_V2_3 68 #define CONFIG_TSECV2 69 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 70 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 71 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 72 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 73 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 74 #define CONFIG_ESDHC_HC_BLK_ADDR 75 76 /* P1011 is single core version of P1020 */ 77 #elif defined(CONFIG_ARCH_P1011) 78 #define CONFIG_TSECV2 79 #define CONFIG_FSL_PCIE_DISABLE_ASPM 80 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 81 82 #elif defined(CONFIG_ARCH_P1020) 83 #define CONFIG_TSECV2 84 #define CONFIG_FSL_PCIE_DISABLE_ASPM 85 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 86 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 87 #endif 88 89 #elif defined(CONFIG_ARCH_P1021) 90 #define CONFIG_TSECV2 91 #define CONFIG_FSL_PCIE_DISABLE_ASPM 92 #define QE_MURAM_SIZE 0x6000UL 93 #define MAX_QE_RISC 1 94 #define QE_NUM_OF_SNUM 28 95 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 96 97 #elif defined(CONFIG_ARCH_P1022) 98 #define CONFIG_TSECV2 99 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 100 101 #elif defined(CONFIG_ARCH_P1023) 102 #define CONFIG_SYS_NUM_FMAN 1 103 #define CONFIG_SYS_NUM_FM1_DTSEC 2 104 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 105 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 106 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 107 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 108 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 109 110 /* P1024 is lower end variant of P1020 */ 111 #elif defined(CONFIG_ARCH_P1024) 112 #define CONFIG_TSECV2 113 #define CONFIG_FSL_PCIE_DISABLE_ASPM 114 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 115 116 /* P1025 is lower end variant of P1021 */ 117 #elif defined(CONFIG_ARCH_P1025) 118 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 119 #define CONFIG_TSECV2 120 #define CONFIG_FSL_PCIE_DISABLE_ASPM 121 #define QE_MURAM_SIZE 0x6000UL 122 #define MAX_QE_RISC 1 123 #define QE_NUM_OF_SNUM 28 124 125 #elif defined(CONFIG_ARCH_P2020) 126 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 127 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 128 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 129 #define CONFIG_SYS_FSL_RMU 130 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 131 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 132 133 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ 134 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 135 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 136 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 137 #define CONFIG_SYS_NUM_FMAN 1 138 #define CONFIG_SYS_NUM_FM1_DTSEC 5 139 #define CONFIG_SYS_NUM_FM1_10GEC 1 140 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 141 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 142 #define CONFIG_SYS_FSL_TBCLK_DIV 32 143 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 144 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 145 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 146 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 147 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 148 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 149 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 150 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 151 152 #elif defined(CONFIG_ARCH_P3041) 153 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 154 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 155 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 156 #define CONFIG_SYS_NUM_FMAN 1 157 #define CONFIG_SYS_NUM_FM1_DTSEC 5 158 #define CONFIG_SYS_NUM_FM1_10GEC 1 159 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 160 #define CONFIG_SYS_FSL_TBCLK_DIV 32 161 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 162 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 163 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 164 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 165 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 166 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 167 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 168 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 169 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 170 171 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ 172 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 173 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 174 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 175 #define CONFIG_SYS_NUM_FMAN 2 176 #define CONFIG_SYS_NUM_FM1_DTSEC 4 177 #define CONFIG_SYS_NUM_FM2_DTSEC 4 178 #define CONFIG_SYS_NUM_FM1_10GEC 1 179 #define CONFIG_SYS_NUM_FM2_10GEC 1 180 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 181 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 182 #define CONFIG_SYS_FSL_TBCLK_DIV 16 183 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 184 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 185 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 186 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 187 #define CONFIG_SYS_FSL_RMU 188 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 189 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 190 191 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ 192 #define CONFIG_SYS_PPC64 /* 64-bit core */ 193 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 194 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 195 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 196 #define CONFIG_SYS_NUM_FMAN 1 197 #define CONFIG_SYS_NUM_FM1_DTSEC 5 198 #define CONFIG_SYS_NUM_FM1_10GEC 1 199 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 200 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 201 #define CONFIG_SYS_FSL_TBCLK_DIV 32 202 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 203 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 204 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 205 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 206 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 207 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 208 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 209 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 210 211 #elif defined(CONFIG_ARCH_P5040) 212 #define CONFIG_SYS_PPC64 213 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 214 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 215 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 216 #define CONFIG_SYS_NUM_FMAN 2 217 #define CONFIG_SYS_NUM_FM1_DTSEC 5 218 #define CONFIG_SYS_NUM_FM1_10GEC 1 219 #define CONFIG_SYS_NUM_FM2_DTSEC 5 220 #define CONFIG_SYS_NUM_FM2_10GEC 1 221 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 222 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 223 #define CONFIG_SYS_FSL_TBCLK_DIV 16 224 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 225 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 226 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 227 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 228 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 229 230 #elif defined(CONFIG_ARCH_BSC9131) 231 #define CONFIG_FSL_SDHC_V2_3 232 #define CONFIG_TSECV2 233 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 234 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 235 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 236 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 237 #define CONFIG_NAND_FSL_IFC 238 #define CONFIG_ESDHC_HC_BLK_ADDR 239 240 #elif defined(CONFIG_ARCH_BSC9132) 241 #define CONFIG_FSL_SDHC_V2_3 242 #define CONFIG_TSECV2 243 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 244 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 245 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 246 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 247 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 248 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 249 #define CONFIG_NAND_FSL_IFC 250 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 251 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 252 #define CONFIG_ESDHC_HC_BLK_ADDR 253 254 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) 255 #define CONFIG_E6500 256 #define CONFIG_SYS_PPC64 /* 64-bit core */ 257 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 258 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 259 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 260 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 261 #ifdef CONFIG_ARCH_T4240 262 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 263 #define CONFIG_SYS_NUM_FM1_DTSEC 8 264 #define CONFIG_SYS_NUM_FM1_10GEC 2 265 #define CONFIG_SYS_NUM_FM2_DTSEC 8 266 #define CONFIG_SYS_NUM_FM2_10GEC 2 267 #else 268 #define CONFIG_SYS_NUM_FM1_DTSEC 6 269 #define CONFIG_SYS_NUM_FM1_10GEC 1 270 #define CONFIG_SYS_NUM_FM2_DTSEC 8 271 #define CONFIG_SYS_NUM_FM2_10GEC 1 272 #if defined(CONFIG_ARCH_T4160) 273 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 274 #endif 275 #endif 276 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 277 #define CONFIG_SYS_FSL_SRDS_1 278 #define CONFIG_SYS_FSL_SRDS_2 279 #define CONFIG_SYS_FSL_SRDS_3 280 #define CONFIG_SYS_FSL_SRDS_4 281 #define CONFIG_SYS_NUM_FMAN 2 282 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 283 #define CONFIG_SYS_PME_CLK 0 284 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 285 #define CONFIG_SYS_FMAN_V3 286 #define CONFIG_SYS_FM1_CLK 3 287 #define CONFIG_SYS_FM2_CLK 3 288 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 289 #define CONFIG_SYS_FSL_TBCLK_DIV 16 290 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 291 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 292 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 293 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 294 #define CONFIG_SYS_FSL_SRIO_LIODN 295 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 296 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 297 #define CONFIG_SYS_FSL_SFP_VER_3_0 298 #define CONFIG_SYS_FSL_PCI_VER_3_X 299 300 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) 301 #define CONFIG_E6500 302 #define CONFIG_SYS_PPC64 /* 64-bit core */ 303 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 304 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 305 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 306 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 307 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 308 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 309 #define CONFIG_SYS_FSL_SRDS_1 310 #define CONFIG_SYS_FSL_SRDS_2 311 #define CONFIG_SYS_MAPLE 312 #define CONFIG_SYS_CPRI 313 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 314 #define CONFIG_SYS_NUM_FMAN 1 315 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 316 #define CONFIG_SYS_FM1_CLK 0 317 #define CONFIG_SYS_CPRI_CLK 3 318 #define CONFIG_SYS_ULB_CLK 4 319 #define CONFIG_SYS_ETVPE_CLK 1 320 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 321 #define CONFIG_SYS_FMAN_V3 322 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 323 #define CONFIG_SYS_FSL_TBCLK_DIV 16 324 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 325 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 326 #define CONFIG_SYS_FSL_SFP_VER_3_0 327 328 #ifdef CONFIG_ARCH_B4860 329 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 330 #define CONFIG_MAX_DSP_CPUS 12 331 #define CONFIG_NUM_DSP_CPUS 6 332 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 333 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 334 #define CONFIG_SYS_NUM_FM1_DTSEC 6 335 #define CONFIG_SYS_NUM_FM1_10GEC 2 336 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 337 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 338 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 339 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 340 #define CONFIG_SYS_FSL_SRIO_LIODN 341 #else 342 #define CONFIG_MAX_DSP_CPUS 2 343 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 344 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 345 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 346 #define CONFIG_SYS_NUM_FM1_DTSEC 4 347 #define CONFIG_SYS_NUM_FM1_10GEC 0 348 #endif 349 350 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) 351 #define CONFIG_E5500 352 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 353 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 354 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 355 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 356 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 357 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 358 #define CONFIG_SYS_FSL_SRDS_1 359 #define CONFIG_SYS_NUM_FMAN 1 360 #define CONFIG_SYS_NUM_FM1_DTSEC 5 361 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 362 #define CONFIG_PME_PLAT_CLK_DIV 2 363 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 364 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 365 #define CONFIG_SYS_FMAN_V3 366 #define CONFIG_FM_PLAT_CLK_DIV 1 367 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 368 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 369 per rcw field value */ 370 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 371 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 372 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 373 #define CONFIG_SYS_FSL_TBCLK_DIV 16 374 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 375 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 376 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 377 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 378 #define QE_MURAM_SIZE 0x6000UL 379 #define MAX_QE_RISC 1 380 #define QE_NUM_OF_SNUM 28 381 #define CONFIG_SYS_FSL_SFP_VER_3_0 382 383 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) 384 #define CONFIG_E5500 385 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 386 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 387 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 388 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 389 #define CONFIG_SYS_FMAN_V3 390 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 391 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 392 #define CONFIG_SYS_FSL_SRDS_1 393 #define CONFIG_SYS_NUM_FMAN 1 394 #define CONFIG_SYS_NUM_FM1_DTSEC 4 395 #define CONFIG_SYS_NUM_FM1_10GEC 1 396 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 397 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 398 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 399 #define CONFIG_SYS_FM1_CLK 0 400 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 401 per rcw field value */ 402 #define CONFIG_QBMAN_CLK_DIV 1 403 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 404 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 405 #define CONFIG_SYS_FSL_TBCLK_DIV 16 406 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 407 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 408 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 409 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 410 #define QE_MURAM_SIZE 0x6000UL 411 #define MAX_QE_RISC 1 412 #define QE_NUM_OF_SNUM 28 413 #define CONFIG_SYS_FSL_SFP_VER_3_0 414 415 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) 416 #define CONFIG_E6500 417 #define CONFIG_SYS_PPC64 /* 64-bit core */ 418 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 419 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 420 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 421 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 422 #define CONFIG_SYS_FSL_QMAN_V3 423 #define CONFIG_SYS_NUM_FMAN 1 424 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 425 #define CONFIG_SYS_FSL_SRDS_1 426 #define CONFIG_SYS_FSL_PCI_VER_3_X 427 #if defined(CONFIG_ARCH_T2080) 428 #define CONFIG_SYS_NUM_FM1_DTSEC 8 429 #define CONFIG_SYS_NUM_FM1_10GEC 4 430 #define CONFIG_SYS_FSL_SRDS_2 431 #define CONFIG_SYS_FSL_SRIO_LIODN 432 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 433 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 434 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 435 #elif defined(CONFIG_ARCH_T2081) 436 #define CONFIG_SYS_NUM_FM1_DTSEC 6 437 #define CONFIG_SYS_NUM_FM1_10GEC 2 438 #endif 439 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 440 #define CONFIG_PME_PLAT_CLK_DIV 1 441 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 442 #define CONFIG_SYS_FM1_CLK 0 443 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 444 per rcw field value */ 445 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 446 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 447 #define CONFIG_SYS_FMAN_V3 448 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 449 #define CONFIG_SYS_FSL_TBCLK_DIV 16 450 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 451 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 452 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 453 #define CONFIG_SYS_FSL_SFP_VER_3_0 454 #define CONFIG_SYS_FSL_ISBC_VER 2 455 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 456 #define CONFIG_SYS_FSL_SFP_VER_3_0 457 458 459 #elif defined(CONFIG_ARCH_C29X) 460 #define CONFIG_FSL_SDHC_V2_3 461 #define CONFIG_TSECV2_1 462 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 463 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 464 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 465 466 #elif defined(CONFIG_ARCH_QEMU_E500) 467 468 #else 469 #error Processor type not defined for this platform 470 #endif 471 472 #ifdef CONFIG_E6500 473 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 474 #else 475 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 476 #endif 477 478 #if !defined(CONFIG_ARCH_C29X) 479 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 480 #endif 481 482 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 483