1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 /* Number of TLB CAM entries we have on FSL Book-E chips */ 27 #if defined(CONFIG_E500MC) 28 #define CONFIG_SYS_NUM_TLBCAMS 64 29 #elif defined(CONFIG_E500) 30 #define CONFIG_SYS_NUM_TLBCAMS 16 31 #endif 32 33 #if defined(CONFIG_MPC8536) 34 #define CONFIG_MAX_CPUS 1 35 #define CONFIG_SYS_FSL_NUM_LAWS 12 36 #define CONFIG_SYS_FSL_SEC_COMPAT 2 37 38 #elif defined(CONFIG_MPC8540) 39 #define CONFIG_MAX_CPUS 1 40 #define CONFIG_SYS_FSL_NUM_LAWS 8 41 42 #elif defined(CONFIG_MPC8541) 43 #define CONFIG_MAX_CPUS 1 44 #define CONFIG_SYS_FSL_NUM_LAWS 8 45 #define CONFIG_SYS_FSL_SEC_COMPAT 2 46 47 #elif defined(CONFIG_MPC8544) 48 #define CONFIG_MAX_CPUS 1 49 #define CONFIG_SYS_FSL_NUM_LAWS 10 50 #define CONFIG_SYS_FSL_SEC_COMPAT 2 51 52 #elif defined(CONFIG_MPC8548) 53 #define CONFIG_MAX_CPUS 1 54 #define CONFIG_SYS_FSL_NUM_LAWS 10 55 #define CONFIG_SYS_FSL_SEC_COMPAT 2 56 57 #elif defined(CONFIG_MPC8555) 58 #define CONFIG_MAX_CPUS 1 59 #define CONFIG_SYS_FSL_NUM_LAWS 8 60 #define CONFIG_SYS_FSL_SEC_COMPAT 2 61 62 #elif defined(CONFIG_MPC8560) 63 #define CONFIG_MAX_CPUS 1 64 #define CONFIG_SYS_FSL_NUM_LAWS 8 65 66 #elif defined(CONFIG_MPC8568) 67 #define CONFIG_MAX_CPUS 1 68 #define CONFIG_SYS_FSL_NUM_LAWS 10 69 #define CONFIG_SYS_FSL_SEC_COMPAT 2 70 #define QE_MURAM_SIZE 0x10000UL 71 #define MAX_QE_RISC 2 72 #define QE_NUM_OF_SNUM 28 73 74 #elif defined(CONFIG_MPC8569) 75 #define CONFIG_MAX_CPUS 1 76 #define CONFIG_SYS_FSL_NUM_LAWS 10 77 #define CONFIG_SYS_FSL_SEC_COMPAT 2 78 #define QE_MURAM_SIZE 0x20000UL 79 #define MAX_QE_RISC 4 80 #define QE_NUM_OF_SNUM 46 81 82 #elif defined(CONFIG_MPC8572) 83 #define CONFIG_MAX_CPUS 2 84 #define CONFIG_SYS_FSL_NUM_LAWS 12 85 #define CONFIG_SYS_FSL_SEC_COMPAT 2 86 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 87 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 88 89 #elif defined(CONFIG_P1010) 90 #define CONFIG_MAX_CPUS 1 91 #define CONFIG_FSL_SDHC_V2_3 92 #define CONFIG_SYS_FSL_NUM_LAWS 12 93 #define CONFIG_TSECV2 94 #define CONFIG_SYS_FSL_SEC_COMPAT 4 95 #define CONFIG_FSL_SATA_V2 96 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 97 #define CONFIG_NUM_DDR_CONTROLLERS 1 98 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 99 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 100 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 101 102 /* P1011 is single core version of P1020 */ 103 #elif defined(CONFIG_P1011) 104 #define CONFIG_MAX_CPUS 1 105 #define CONFIG_SYS_FSL_NUM_LAWS 12 106 #define CONFIG_TSECV2 107 #define CONFIG_FSL_PCIE_DISABLE_ASPM 108 #define CONFIG_SYS_FSL_SEC_COMPAT 2 109 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 110 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 111 112 /* P1012 is single core version of P1021 */ 113 #elif defined(CONFIG_P1012) 114 #define CONFIG_MAX_CPUS 1 115 #define CONFIG_SYS_FSL_NUM_LAWS 12 116 #define CONFIG_TSECV2 117 #define CONFIG_FSL_PCIE_DISABLE_ASPM 118 #define CONFIG_SYS_FSL_SEC_COMPAT 2 119 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 120 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 121 #define QE_MURAM_SIZE 0x6000UL 122 #define MAX_QE_RISC 1 123 #define QE_NUM_OF_SNUM 28 124 125 /* P1013 is single core version of P1022 */ 126 #elif defined(CONFIG_P1013) 127 #define CONFIG_MAX_CPUS 1 128 #define CONFIG_SYS_FSL_NUM_LAWS 12 129 #define CONFIG_TSECV2 130 #define CONFIG_SYS_FSL_SEC_COMPAT 2 131 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 132 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 133 #define CONFIG_FSL_SATA_ERRATUM_A001 134 135 #elif defined(CONFIG_P1014) 136 #define CONFIG_MAX_CPUS 1 137 #define CONFIG_FSL_SDHC_V2_3 138 #define CONFIG_SYS_FSL_NUM_LAWS 12 139 #define CONFIG_TSECV2 140 #define CONFIG_SYS_FSL_SEC_COMPAT 4 141 #define CONFIG_FSL_SATA_V2 142 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 143 #define CONFIG_NUM_DDR_CONTROLLERS 1 144 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 145 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 146 147 /* P1015 is single core version of P1024 */ 148 #elif defined(CONFIG_P1015) 149 #define CONFIG_MAX_CPUS 1 150 #define CONFIG_SYS_FSL_NUM_LAWS 12 151 #define CONFIG_TSECV2 152 #define CONFIG_FSL_PCIE_DISABLE_ASPM 153 #define CONFIG_SYS_FSL_SEC_COMPAT 2 154 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 155 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 156 157 /* P1016 is single core version of P1025 */ 158 #elif defined(CONFIG_P1016) 159 #define CONFIG_MAX_CPUS 1 160 #define CONFIG_SYS_FSL_NUM_LAWS 12 161 #define CONFIG_TSECV2 162 #define CONFIG_FSL_PCIE_DISABLE_ASPM 163 #define CONFIG_SYS_FSL_SEC_COMPAT 2 164 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 165 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 166 #define QE_MURAM_SIZE 0x6000UL 167 #define MAX_QE_RISC 1 168 #define QE_NUM_OF_SNUM 28 169 170 /* P1017 is single core version of P1023 */ 171 #elif defined(CONFIG_P1017) 172 #define CONFIG_MAX_CPUS 1 173 #define CONFIG_SYS_FSL_NUM_LAWS 12 174 #define CONFIG_SYS_FSL_SEC_COMPAT 4 175 #define CONFIG_SYS_NUM_FMAN 1 176 #define CONFIG_SYS_NUM_FM1_DTSEC 2 177 #define CONFIG_NUM_DDR_CONTROLLERS 1 178 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 179 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 180 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 181 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 182 183 #elif defined(CONFIG_P1020) 184 #define CONFIG_MAX_CPUS 2 185 #define CONFIG_SYS_FSL_NUM_LAWS 12 186 #define CONFIG_TSECV2 187 #define CONFIG_FSL_PCIE_DISABLE_ASPM 188 #define CONFIG_SYS_FSL_SEC_COMPAT 2 189 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 190 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 191 192 #elif defined(CONFIG_P1021) 193 #define CONFIG_MAX_CPUS 2 194 #define CONFIG_SYS_FSL_NUM_LAWS 12 195 #define CONFIG_TSECV2 196 #define CONFIG_FSL_PCIE_DISABLE_ASPM 197 #define CONFIG_SYS_FSL_SEC_COMPAT 2 198 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 199 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 200 #define QE_MURAM_SIZE 0x6000UL 201 #define MAX_QE_RISC 1 202 #define QE_NUM_OF_SNUM 28 203 204 #elif defined(CONFIG_P1022) 205 #define CONFIG_MAX_CPUS 2 206 #define CONFIG_SYS_FSL_NUM_LAWS 12 207 #define CONFIG_TSECV2 208 #define CONFIG_SYS_FSL_SEC_COMPAT 2 209 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 210 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 211 #define CONFIG_FSL_SATA_ERRATUM_A001 212 213 #elif defined(CONFIG_P1023) 214 #define CONFIG_MAX_CPUS 2 215 #define CONFIG_SYS_FSL_NUM_LAWS 12 216 #define CONFIG_SYS_FSL_SEC_COMPAT 4 217 #define CONFIG_SYS_NUM_FMAN 1 218 #define CONFIG_SYS_NUM_FM1_DTSEC 2 219 #define CONFIG_NUM_DDR_CONTROLLERS 1 220 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 221 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 222 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 223 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 224 225 /* P1024 is lower end variant of P1020 */ 226 #elif defined(CONFIG_P1024) 227 #define CONFIG_MAX_CPUS 2 228 #define CONFIG_SYS_FSL_NUM_LAWS 12 229 #define CONFIG_TSECV2 230 #define CONFIG_FSL_PCIE_DISABLE_ASPM 231 #define CONFIG_SYS_FSL_SEC_COMPAT 2 232 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 233 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 234 235 /* P1025 is lower end variant of P1021 */ 236 #elif defined(CONFIG_P1025) 237 #define CONFIG_MAX_CPUS 2 238 #define CONFIG_SYS_FSL_NUM_LAWS 12 239 #define CONFIG_TSECV2 240 #define CONFIG_FSL_PCIE_DISABLE_ASPM 241 #define CONFIG_SYS_FSL_SEC_COMPAT 2 242 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 243 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 244 #define QE_MURAM_SIZE 0x6000UL 245 #define MAX_QE_RISC 1 246 #define QE_NUM_OF_SNUM 28 247 248 /* P2010 is single core version of P2020 */ 249 #elif defined(CONFIG_P2010) 250 #define CONFIG_MAX_CPUS 1 251 #define CONFIG_SYS_FSL_NUM_LAWS 12 252 #define CONFIG_SYS_FSL_SEC_COMPAT 2 253 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 254 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 255 256 #elif defined(CONFIG_P2020) 257 #define CONFIG_MAX_CPUS 2 258 #define CONFIG_SYS_FSL_NUM_LAWS 12 259 #define CONFIG_SYS_FSL_SEC_COMPAT 2 260 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 261 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 262 263 #elif defined(CONFIG_PPC_P2040) 264 #define CONFIG_MAX_CPUS 4 265 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 266 #define CONFIG_SYS_FSL_NUM_LAWS 32 267 #define CONFIG_SYS_FSL_SEC_COMPAT 4 268 #define CONFIG_SYS_NUM_FMAN 1 269 #define CONFIG_SYS_NUM_FM1_DTSEC 5 270 #define CONFIG_NUM_DDR_CONTROLLERS 1 271 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 272 #define CONFIG_SYS_FSL_TBCLK_DIV 32 273 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 274 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 275 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 276 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 277 278 #elif defined(CONFIG_PPC_P2041) 279 #define CONFIG_MAX_CPUS 4 280 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 281 #define CONFIG_SYS_FSL_NUM_LAWS 32 282 #define CONFIG_SYS_FSL_SEC_COMPAT 4 283 #define CONFIG_SYS_NUM_FMAN 1 284 #define CONFIG_SYS_NUM_FM1_DTSEC 5 285 #define CONFIG_SYS_NUM_FM1_10GEC 1 286 #define CONFIG_NUM_DDR_CONTROLLERS 1 287 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 288 #define CONFIG_SYS_FSL_TBCLK_DIV 32 289 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 290 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 291 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 292 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 293 294 #elif defined(CONFIG_PPC_P3041) 295 #define CONFIG_MAX_CPUS 4 296 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 297 #define CONFIG_SYS_FSL_NUM_LAWS 32 298 #define CONFIG_SYS_FSL_SEC_COMPAT 4 299 #define CONFIG_SYS_NUM_FMAN 1 300 #define CONFIG_SYS_NUM_FM1_DTSEC 5 301 #define CONFIG_SYS_NUM_FM1_10GEC 1 302 #define CONFIG_NUM_DDR_CONTROLLERS 1 303 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 304 #define CONFIG_SYS_FSL_TBCLK_DIV 32 305 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 306 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 307 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 308 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 309 310 #elif defined(CONFIG_PPC_P4040) 311 #define CONFIG_MAX_CPUS 4 312 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 313 #define CONFIG_SYS_FSL_NUM_LAWS 32 314 #define CONFIG_SYS_FSL_SEC_COMPAT 4 315 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 316 #define CONFIG_SYS_FSL_TBCLK_DIV 16 317 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 318 319 #elif defined(CONFIG_PPC_P4080) 320 #define CONFIG_MAX_CPUS 8 321 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 322 #define CONFIG_SYS_FSL_NUM_LAWS 32 323 #define CONFIG_SYS_FSL_SEC_COMPAT 4 324 #define CONFIG_SYS_NUM_FMAN 2 325 #define CONFIG_SYS_NUM_FM1_DTSEC 4 326 #define CONFIG_SYS_NUM_FM2_DTSEC 4 327 #define CONFIG_SYS_NUM_FM1_10GEC 1 328 #define CONFIG_SYS_NUM_FM2_10GEC 1 329 #define CONFIG_NUM_DDR_CONTROLLERS 2 330 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 331 #define CONFIG_SYS_FSL_TBCLK_DIV 16 332 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 333 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 334 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 335 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 336 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 337 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 338 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 339 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 340 #define CONFIG_SYS_P4080_ERRATUM_CPU22 341 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 342 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 343 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 344 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 345 346 /* P5010 is single core version of P5020 */ 347 #elif defined(CONFIG_PPC_P5010) 348 #define CONFIG_MAX_CPUS 1 349 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 350 #define CONFIG_SYS_FSL_NUM_LAWS 32 351 #define CONFIG_SYS_FSL_SEC_COMPAT 4 352 #define CONFIG_SYS_NUM_FMAN 1 353 #define CONFIG_SYS_NUM_FM1_DTSEC 5 354 #define CONFIG_SYS_NUM_FM1_10GEC 1 355 #define CONFIG_NUM_DDR_CONTROLLERS 1 356 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 357 #define CONFIG_SYS_FSL_TBCLK_DIV 32 358 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 359 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 360 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 361 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 362 363 #elif defined(CONFIG_PPC_P5020) 364 #define CONFIG_MAX_CPUS 2 365 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 366 #define CONFIG_SYS_FSL_NUM_LAWS 32 367 #define CONFIG_SYS_FSL_SEC_COMPAT 4 368 #define CONFIG_SYS_NUM_FMAN 1 369 #define CONFIG_SYS_NUM_FM1_DTSEC 5 370 #define CONFIG_SYS_NUM_FM1_10GEC 1 371 #define CONFIG_NUM_DDR_CONTROLLERS 2 372 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 373 #define CONFIG_SYS_FSL_TBCLK_DIV 32 374 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 375 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 376 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 377 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 378 379 #else 380 #error Processor type not defined for this platform 381 #endif 382 383 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 384