1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 28 #endif 29 30 /* Number of TLB CAM entries we have on FSL Book-E chips */ 31 #if defined(CONFIG_E500MC) 32 #define CONFIG_SYS_NUM_TLBCAMS 64 33 #elif defined(CONFIG_E500) 34 #define CONFIG_SYS_NUM_TLBCAMS 16 35 #endif 36 37 #if defined(CONFIG_MPC8536) 38 #define CONFIG_MAX_CPUS 1 39 #define CONFIG_SYS_FSL_NUM_LAWS 12 40 #define CONFIG_SYS_FSL_SEC_COMPAT 2 41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 42 43 #elif defined(CONFIG_MPC8540) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 47 48 #elif defined(CONFIG_MPC8541) 49 #define CONFIG_MAX_CPUS 1 50 #define CONFIG_SYS_FSL_NUM_LAWS 8 51 #define CONFIG_SYS_FSL_SEC_COMPAT 2 52 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 53 54 #elif defined(CONFIG_MPC8544) 55 #define CONFIG_MAX_CPUS 1 56 #define CONFIG_SYS_FSL_NUM_LAWS 10 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_MPC8548) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2 64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 65 66 #elif defined(CONFIG_MPC8555) 67 #define CONFIG_MAX_CPUS 1 68 #define CONFIG_SYS_FSL_NUM_LAWS 8 69 #define CONFIG_SYS_FSL_SEC_COMPAT 2 70 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 71 72 #elif defined(CONFIG_MPC8560) 73 #define CONFIG_MAX_CPUS 1 74 #define CONFIG_SYS_FSL_NUM_LAWS 8 75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 76 77 #elif defined(CONFIG_MPC8568) 78 #define CONFIG_MAX_CPUS 1 79 #define CONFIG_SYS_FSL_NUM_LAWS 10 80 #define CONFIG_SYS_FSL_SEC_COMPAT 2 81 #define QE_MURAM_SIZE 0x10000UL 82 #define MAX_QE_RISC 2 83 #define QE_NUM_OF_SNUM 28 84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 85 86 #elif defined(CONFIG_MPC8569) 87 #define CONFIG_MAX_CPUS 1 88 #define CONFIG_SYS_FSL_NUM_LAWS 10 89 #define CONFIG_SYS_FSL_SEC_COMPAT 2 90 #define QE_MURAM_SIZE 0x20000UL 91 #define MAX_QE_RISC 4 92 #define QE_NUM_OF_SNUM 46 93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 94 95 #elif defined(CONFIG_MPC8572) 96 #define CONFIG_MAX_CPUS 2 97 #define CONFIG_SYS_FSL_NUM_LAWS 12 98 #define CONFIG_SYS_FSL_SEC_COMPAT 2 99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 100 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 101 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 102 103 #elif defined(CONFIG_P1010) 104 #define CONFIG_MAX_CPUS 1 105 #define CONFIG_FSL_SDHC_V2_3 106 #define CONFIG_SYS_FSL_NUM_LAWS 12 107 #define CONFIG_TSECV2 108 #define CONFIG_SYS_FSL_SEC_COMPAT 4 109 #define CONFIG_FSL_SATA_V2 110 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 111 #define CONFIG_NUM_DDR_CONTROLLERS 1 112 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 113 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 114 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 115 116 /* P1011 is single core version of P1020 */ 117 #elif defined(CONFIG_P1011) 118 #define CONFIG_MAX_CPUS 1 119 #define CONFIG_SYS_FSL_NUM_LAWS 12 120 #define CONFIG_TSECV2 121 #define CONFIG_FSL_PCIE_DISABLE_ASPM 122 #define CONFIG_SYS_FSL_SEC_COMPAT 2 123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 124 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 125 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 126 127 /* P1012 is single core version of P1021 */ 128 #elif defined(CONFIG_P1012) 129 #define CONFIG_MAX_CPUS 1 130 #define CONFIG_SYS_FSL_NUM_LAWS 12 131 #define CONFIG_TSECV2 132 #define CONFIG_FSL_PCIE_DISABLE_ASPM 133 #define CONFIG_SYS_FSL_SEC_COMPAT 2 134 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 135 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 136 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 137 #define QE_MURAM_SIZE 0x6000UL 138 #define MAX_QE_RISC 1 139 #define QE_NUM_OF_SNUM 28 140 141 /* P1013 is single core version of P1022 */ 142 #elif defined(CONFIG_P1013) 143 #define CONFIG_MAX_CPUS 1 144 #define CONFIG_SYS_FSL_NUM_LAWS 12 145 #define CONFIG_TSECV2 146 #define CONFIG_SYS_FSL_SEC_COMPAT 2 147 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 148 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 149 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 150 #define CONFIG_FSL_SATA_ERRATUM_A001 151 152 #elif defined(CONFIG_P1014) 153 #define CONFIG_MAX_CPUS 1 154 #define CONFIG_FSL_SDHC_V2_3 155 #define CONFIG_SYS_FSL_NUM_LAWS 12 156 #define CONFIG_TSECV2 157 #define CONFIG_SYS_FSL_SEC_COMPAT 4 158 #define CONFIG_FSL_SATA_V2 159 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 160 #define CONFIG_NUM_DDR_CONTROLLERS 1 161 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 162 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 163 164 /* P1015 is single core version of P1024 */ 165 #elif defined(CONFIG_P1015) 166 #define CONFIG_MAX_CPUS 1 167 #define CONFIG_SYS_FSL_NUM_LAWS 12 168 #define CONFIG_TSECV2 169 #define CONFIG_FSL_PCIE_DISABLE_ASPM 170 #define CONFIG_SYS_FSL_SEC_COMPAT 2 171 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 172 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 173 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 174 175 /* P1016 is single core version of P1025 */ 176 #elif defined(CONFIG_P1016) 177 #define CONFIG_MAX_CPUS 1 178 #define CONFIG_SYS_FSL_NUM_LAWS 12 179 #define CONFIG_TSECV2 180 #define CONFIG_FSL_PCIE_DISABLE_ASPM 181 #define CONFIG_SYS_FSL_SEC_COMPAT 2 182 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 183 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 184 #define QE_MURAM_SIZE 0x6000UL 185 #define MAX_QE_RISC 1 186 #define QE_NUM_OF_SNUM 28 187 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 188 189 /* P1017 is single core version of P1023 */ 190 #elif defined(CONFIG_P1017) 191 #define CONFIG_MAX_CPUS 1 192 #define CONFIG_SYS_FSL_NUM_LAWS 12 193 #define CONFIG_SYS_FSL_SEC_COMPAT 4 194 #define CONFIG_SYS_NUM_FMAN 1 195 #define CONFIG_SYS_NUM_FM1_DTSEC 2 196 #define CONFIG_NUM_DDR_CONTROLLERS 1 197 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 198 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 199 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 200 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 201 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 202 203 #elif defined(CONFIG_P1020) 204 #define CONFIG_MAX_CPUS 2 205 #define CONFIG_SYS_FSL_NUM_LAWS 12 206 #define CONFIG_TSECV2 207 #define CONFIG_FSL_PCIE_DISABLE_ASPM 208 #define CONFIG_SYS_FSL_SEC_COMPAT 2 209 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 210 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 211 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 212 213 #elif defined(CONFIG_P1021) 214 #define CONFIG_MAX_CPUS 2 215 #define CONFIG_SYS_FSL_NUM_LAWS 12 216 #define CONFIG_TSECV2 217 #define CONFIG_FSL_PCIE_DISABLE_ASPM 218 #define CONFIG_SYS_FSL_SEC_COMPAT 2 219 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 220 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 221 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 222 #define QE_MURAM_SIZE 0x6000UL 223 #define MAX_QE_RISC 1 224 #define QE_NUM_OF_SNUM 28 225 226 #elif defined(CONFIG_P1022) 227 #define CONFIG_MAX_CPUS 2 228 #define CONFIG_SYS_FSL_NUM_LAWS 12 229 #define CONFIG_TSECV2 230 #define CONFIG_SYS_FSL_SEC_COMPAT 2 231 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 232 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 233 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 234 #define CONFIG_FSL_SATA_ERRATUM_A001 235 236 #elif defined(CONFIG_P1023) 237 #define CONFIG_MAX_CPUS 2 238 #define CONFIG_SYS_FSL_NUM_LAWS 12 239 #define CONFIG_SYS_FSL_SEC_COMPAT 4 240 #define CONFIG_SYS_NUM_FMAN 1 241 #define CONFIG_SYS_NUM_FM1_DTSEC 2 242 #define CONFIG_NUM_DDR_CONTROLLERS 1 243 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 244 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 245 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 246 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 247 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 248 249 /* P1024 is lower end variant of P1020 */ 250 #elif defined(CONFIG_P1024) 251 #define CONFIG_MAX_CPUS 2 252 #define CONFIG_SYS_FSL_NUM_LAWS 12 253 #define CONFIG_TSECV2 254 #define CONFIG_FSL_PCIE_DISABLE_ASPM 255 #define CONFIG_SYS_FSL_SEC_COMPAT 2 256 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 257 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 258 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 259 260 /* P1025 is lower end variant of P1021 */ 261 #elif defined(CONFIG_P1025) 262 #define CONFIG_MAX_CPUS 2 263 #define CONFIG_SYS_FSL_NUM_LAWS 12 264 #define CONFIG_TSECV2 265 #define CONFIG_FSL_PCIE_DISABLE_ASPM 266 #define CONFIG_SYS_FSL_SEC_COMPAT 2 267 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 268 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 269 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 270 #define QE_MURAM_SIZE 0x6000UL 271 #define MAX_QE_RISC 1 272 #define QE_NUM_OF_SNUM 28 273 274 /* P2010 is single core version of P2020 */ 275 #elif defined(CONFIG_P2010) 276 #define CONFIG_MAX_CPUS 1 277 #define CONFIG_SYS_FSL_NUM_LAWS 12 278 #define CONFIG_SYS_FSL_SEC_COMPAT 2 279 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 280 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 281 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 282 283 #elif defined(CONFIG_P2020) 284 #define CONFIG_MAX_CPUS 2 285 #define CONFIG_SYS_FSL_NUM_LAWS 12 286 #define CONFIG_SYS_FSL_SEC_COMPAT 2 287 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 288 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 289 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 290 291 #elif defined(CONFIG_PPC_P2040) 292 #define CONFIG_MAX_CPUS 4 293 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 294 #define CONFIG_SYS_FSL_NUM_LAWS 32 295 #define CONFIG_SYS_FSL_SEC_COMPAT 4 296 #define CONFIG_SYS_NUM_FMAN 1 297 #define CONFIG_SYS_NUM_FM1_DTSEC 5 298 #define CONFIG_NUM_DDR_CONTROLLERS 1 299 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 300 #define CONFIG_SYS_FSL_TBCLK_DIV 32 301 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 302 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 303 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 304 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 305 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 306 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 307 308 #elif defined(CONFIG_PPC_P2041) 309 #define CONFIG_MAX_CPUS 4 310 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 311 #define CONFIG_SYS_FSL_NUM_LAWS 32 312 #define CONFIG_SYS_FSL_SEC_COMPAT 4 313 #define CONFIG_SYS_NUM_FMAN 1 314 #define CONFIG_SYS_NUM_FM1_DTSEC 5 315 #define CONFIG_SYS_NUM_FM1_10GEC 1 316 #define CONFIG_NUM_DDR_CONTROLLERS 1 317 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 318 #define CONFIG_SYS_FSL_TBCLK_DIV 32 319 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 320 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 321 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 322 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 323 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 324 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 325 326 #elif defined(CONFIG_PPC_P3041) 327 #define CONFIG_MAX_CPUS 4 328 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 329 #define CONFIG_SYS_FSL_NUM_LAWS 32 330 #define CONFIG_SYS_FSL_SEC_COMPAT 4 331 #define CONFIG_SYS_NUM_FMAN 1 332 #define CONFIG_SYS_NUM_FM1_DTSEC 5 333 #define CONFIG_SYS_NUM_FM1_10GEC 1 334 #define CONFIG_NUM_DDR_CONTROLLERS 1 335 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 336 #define CONFIG_SYS_FSL_TBCLK_DIV 32 337 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 338 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 339 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 340 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 341 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 342 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 343 344 #elif defined(CONFIG_PPC_P4040) 345 #define CONFIG_MAX_CPUS 4 346 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 347 #define CONFIG_SYS_FSL_NUM_LAWS 32 348 #define CONFIG_SYS_FSL_SEC_COMPAT 4 349 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 350 #define CONFIG_SYS_FSL_TBCLK_DIV 16 351 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 352 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 353 354 #elif defined(CONFIG_PPC_P4080) 355 #define CONFIG_MAX_CPUS 8 356 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 357 #define CONFIG_SYS_FSL_NUM_LAWS 32 358 #define CONFIG_SYS_FSL_SEC_COMPAT 4 359 #define CONFIG_SYS_NUM_FMAN 2 360 #define CONFIG_SYS_NUM_FM1_DTSEC 4 361 #define CONFIG_SYS_NUM_FM2_DTSEC 4 362 #define CONFIG_SYS_NUM_FM1_10GEC 1 363 #define CONFIG_SYS_NUM_FM2_10GEC 1 364 #define CONFIG_NUM_DDR_CONTROLLERS 2 365 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 366 #define CONFIG_SYS_FSL_TBCLK_DIV 16 367 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 368 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 369 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 370 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 371 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 372 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 373 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 374 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 375 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 376 #define CONFIG_SYS_P4080_ERRATUM_CPU22 377 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 378 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 379 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 380 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 381 382 /* P5010 is single core version of P5020 */ 383 #elif defined(CONFIG_PPC_P5010) 384 #define CONFIG_MAX_CPUS 1 385 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 386 #define CONFIG_SYS_FSL_NUM_LAWS 32 387 #define CONFIG_SYS_FSL_SEC_COMPAT 4 388 #define CONFIG_SYS_NUM_FMAN 1 389 #define CONFIG_SYS_NUM_FM1_DTSEC 5 390 #define CONFIG_SYS_NUM_FM1_10GEC 1 391 #define CONFIG_NUM_DDR_CONTROLLERS 1 392 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 393 #define CONFIG_SYS_FSL_TBCLK_DIV 32 394 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 395 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 396 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 397 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 398 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 399 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 400 401 #elif defined(CONFIG_PPC_P5020) 402 #define CONFIG_MAX_CPUS 2 403 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 404 #define CONFIG_SYS_FSL_NUM_LAWS 32 405 #define CONFIG_SYS_FSL_SEC_COMPAT 4 406 #define CONFIG_SYS_NUM_FMAN 1 407 #define CONFIG_SYS_NUM_FM1_DTSEC 5 408 #define CONFIG_SYS_NUM_FM1_10GEC 1 409 #define CONFIG_NUM_DDR_CONTROLLERS 2 410 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 411 #define CONFIG_SYS_FSL_TBCLK_DIV 32 412 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 413 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 414 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 415 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 416 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 417 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 418 419 #else 420 #error Processor type not defined for this platform 421 #endif 422 423 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 424 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 425 #endif 426 427 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 428