1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_CONFIG_H_ 8 #define _ASM_CONFIG_H_ 9 10 #ifdef CONFIG_MPC85xx 11 #include <asm/config_mpc85xx.h> 12 #define CONFIG_SYS_FSL_DDR 13 #endif 14 15 #ifdef CONFIG_MPC86xx 16 #include <asm/config_mpc86xx.h> 17 #define CONFIG_SYS_FSL_DDR 18 #endif 19 20 #ifdef CONFIG_MPC83xx 21 #define CONFIG_SYS_FSL_DDR 22 #endif 23 24 #ifndef HWCONFIG_BUFFER_SIZE 25 #define HWCONFIG_BUFFER_SIZE 256 26 #endif 27 28 /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ 29 #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) 30 # ifndef CONFIG_HARD_SPI 31 # define CONFIG_HARD_SPI 32 # endif 33 #endif 34 35 #define CONFIG_LMB 36 #define CONFIG_SYS_BOOT_RAMDISK_HIGH 37 #define CONFIG_SYS_BOOT_GET_CMDLINE 38 #define CONFIG_SYS_BOOT_GET_KBD 39 40 #ifndef CONFIG_MAX_MEM_MAPPED 41 #if defined(CONFIG_4xx) || \ 42 defined(CONFIG_E500) || \ 43 defined(CONFIG_MPC86xx) || \ 44 defined(CONFIG_E300) 45 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 46 #else 47 #define CONFIG_MAX_MEM_MAPPED (256 << 20) 48 #endif 49 #endif 50 51 /* Check if boards need to enable FSL DMA engine for SDRAM init */ 52 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 53 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 54 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 55 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 56 #define CONFIG_FSL_DMA 57 #endif 58 #endif 59 60 /* 61 * Provide a default boot page translation virtual address that lines up with 62 * Freescale's default e500 reset page. 63 */ 64 #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 65 #ifndef CONFIG_BPTR_VIRT_ADDR 66 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 67 #endif 68 #endif 69 70 /* 71 * SEC (crypto unit) major compatible version determination 72 */ 73 #if defined(CONFIG_MPC83xx) 74 #define CONFIG_SYS_FSL_SEC_BE 75 #endif 76 77 /* Since so many PPC SOCs have a semi-common LBC, define this here */ 78 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 79 defined(CONFIG_MPC83xx) 80 #if !defined(CONFIG_FSL_IFC) 81 #define CONFIG_FSL_LBC 82 #endif 83 #endif 84 85 /* The TSEC driver uses the PHYLIB infrastructure */ 86 #ifndef CONFIG_PHYLIB 87 #if defined(CONFIG_TSEC_ENET) 88 #define CONFIG_PHYLIB 89 90 #include <config_phylib_all_drivers.h> 91 #endif /* TSEC_ENET */ 92 #endif /* !CONFIG_PHYLIB */ 93 94 /* The FMAN driver uses the PHYLIB infrastructure */ 95 #if defined(CONFIG_FMAN_ENET) 96 #define CONFIG_PHYLIB 97 #endif 98 99 /* All PPC boards must swap IDE bytes */ 100 #define CONFIG_IDE_SWAP_IO 101 102 #if defined(CONFIG_DM_SERIAL) 103 /* 104 * TODO: Convert this to a clock driver exists that can give us the UART 105 * clock here. 106 */ 107 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 108 #endif 109 110 #endif /* _ASM_CONFIG_H_ */ 111