1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * include/asm-ppc/cache.h 3*a47a12beSStefan Roese */ 4*a47a12beSStefan Roese #ifndef __ARCH_PPC_CACHE_H 5*a47a12beSStefan Roese #define __ARCH_PPC_CACHE_H 6*a47a12beSStefan Roese 7*a47a12beSStefan Roese #include <linux/config.h> 8*a47a12beSStefan Roese #include <asm/processor.h> 9*a47a12beSStefan Roese 10*a47a12beSStefan Roese /* bytes per L1 cache line */ 11*a47a12beSStefan Roese #if defined(CONFIG_8xx) || defined(CONFIG_IOP480) 12*a47a12beSStefan Roese #define L1_CACHE_SHIFT 4 13*a47a12beSStefan Roese #elif defined(CONFIG_PPC64BRIDGE) 14*a47a12beSStefan Roese #define L1_CACHE_SHIFT 7 15*a47a12beSStefan Roese #elif defined(CONFIG_E500MC) 16*a47a12beSStefan Roese #define L1_CACHE_SHIFT 6 17*a47a12beSStefan Roese #else 18*a47a12beSStefan Roese #define L1_CACHE_SHIFT 5 19*a47a12beSStefan Roese #endif 20*a47a12beSStefan Roese 21*a47a12beSStefan Roese #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 22*a47a12beSStefan Roese 23*a47a12beSStefan Roese /* 24*a47a12beSStefan Roese * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too 25*a47a12beSStefan Roese */ 26*a47a12beSStefan Roese #ifndef CONFIG_SYS_CACHELINE_SIZE 27*a47a12beSStefan Roese #define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES 28*a47a12beSStefan Roese #endif 29*a47a12beSStefan Roese 30*a47a12beSStefan Roese #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) 31*a47a12beSStefan Roese #define L1_CACHE_PAGES 8 32*a47a12beSStefan Roese 33*a47a12beSStefan Roese #define SMP_CACHE_BYTES L1_CACHE_BYTES 34*a47a12beSStefan Roese 35*a47a12beSStefan Roese #ifdef MODULE 36*a47a12beSStefan Roese #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) 37*a47a12beSStefan Roese #else 38*a47a12beSStefan Roese #define __cacheline_aligned \ 39*a47a12beSStefan Roese __attribute__((__aligned__(L1_CACHE_BYTES), \ 40*a47a12beSStefan Roese __section__(".data.cacheline_aligned"))) 41*a47a12beSStefan Roese #endif 42*a47a12beSStefan Roese 43*a47a12beSStefan Roese #if defined(__KERNEL__) && !defined(__ASSEMBLY__) 44*a47a12beSStefan Roese extern void flush_dcache_range(unsigned long start, unsigned long stop); 45*a47a12beSStefan Roese extern void clean_dcache_range(unsigned long start, unsigned long stop); 46*a47a12beSStefan Roese extern void invalidate_dcache_range(unsigned long start, unsigned long stop); 47*a47a12beSStefan Roese extern void flush_dcache(void); 48*a47a12beSStefan Roese extern void invalidate_dcache(void); 49*a47a12beSStefan Roese extern void invalidate_icache(void); 50*a47a12beSStefan Roese #ifdef CONFIG_SYS_INIT_RAM_LOCK 51*a47a12beSStefan Roese extern void unlock_ram_in_cache(void); 52*a47a12beSStefan Roese #endif /* CONFIG_SYS_INIT_RAM_LOCK */ 53*a47a12beSStefan Roese #endif /* __ASSEMBLY__ */ 54*a47a12beSStefan Roese 55*a47a12beSStefan Roese /* prep registers for L2 */ 56*a47a12beSStefan Roese #define CACHECRBA 0x80000823 /* Cache configuration register address */ 57*a47a12beSStefan Roese #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ 58*a47a12beSStefan Roese #define L2CACHE_512KB 0x00 /* 512KB */ 59*a47a12beSStefan Roese #define L2CACHE_256KB 0x01 /* 256KB */ 60*a47a12beSStefan Roese #define L2CACHE_1MB 0x02 /* 1MB */ 61*a47a12beSStefan Roese #define L2CACHE_NONE 0x03 /* NONE */ 62*a47a12beSStefan Roese #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ 63*a47a12beSStefan Roese 64*a47a12beSStefan Roese #ifdef CONFIG_8xx 65*a47a12beSStefan Roese /* Cache control on the MPC8xx is provided through some additional 66*a47a12beSStefan Roese * special purpose registers. 67*a47a12beSStefan Roese */ 68*a47a12beSStefan Roese #define IC_CST 560 /* Instruction cache control/status */ 69*a47a12beSStefan Roese #define IC_ADR 561 /* Address needed for some commands */ 70*a47a12beSStefan Roese #define IC_DAT 562 /* Read-only data register */ 71*a47a12beSStefan Roese #define DC_CST 568 /* Data cache control/status */ 72*a47a12beSStefan Roese #define DC_ADR 569 /* Address needed for some commands */ 73*a47a12beSStefan Roese #define DC_DAT 570 /* Read-only data register */ 74*a47a12beSStefan Roese 75*a47a12beSStefan Roese /* Commands. Only the first few are available to the instruction cache. 76*a47a12beSStefan Roese */ 77*a47a12beSStefan Roese #define IDC_ENABLE 0x02000000 /* Cache enable */ 78*a47a12beSStefan Roese #define IDC_DISABLE 0x04000000 /* Cache disable */ 79*a47a12beSStefan Roese #define IDC_LDLCK 0x06000000 /* Load and lock */ 80*a47a12beSStefan Roese #define IDC_UNLINE 0x08000000 /* Unlock line */ 81*a47a12beSStefan Roese #define IDC_UNALL 0x0a000000 /* Unlock all */ 82*a47a12beSStefan Roese #define IDC_INVALL 0x0c000000 /* Invalidate all */ 83*a47a12beSStefan Roese 84*a47a12beSStefan Roese #define DC_FLINE 0x0e000000 /* Flush data cache line */ 85*a47a12beSStefan Roese #define DC_SFWT 0x01000000 /* Set forced writethrough mode */ 86*a47a12beSStefan Roese #define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ 87*a47a12beSStefan Roese #define DC_SLES 0x05000000 /* Set little endian swap mode */ 88*a47a12beSStefan Roese #define DC_CLES 0x07000000 /* Clear little endian swap mode */ 89*a47a12beSStefan Roese 90*a47a12beSStefan Roese /* Status. 91*a47a12beSStefan Roese */ 92*a47a12beSStefan Roese #define IDC_ENABLED 0x80000000 /* Cache is enabled */ 93*a47a12beSStefan Roese #define IDC_CERR1 0x00200000 /* Cache error 1 */ 94*a47a12beSStefan Roese #define IDC_CERR2 0x00100000 /* Cache error 2 */ 95*a47a12beSStefan Roese #define IDC_CERR3 0x00080000 /* Cache error 3 */ 96*a47a12beSStefan Roese 97*a47a12beSStefan Roese #define DC_DFWT 0x40000000 /* Data cache is forced write through */ 98*a47a12beSStefan Roese #define DC_LES 0x20000000 /* Caches are little endian mode */ 99*a47a12beSStefan Roese #endif /* CONFIG_8xx */ 100*a47a12beSStefan Roese 101*a47a12beSStefan Roese #endif 102