1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * include/asm-ppc/cache.h 3a47a12beSStefan Roese */ 4a47a12beSStefan Roese #ifndef __ARCH_PPC_CACHE_H 5a47a12beSStefan Roese #define __ARCH_PPC_CACHE_H 6a47a12beSStefan Roese 7a47a12beSStefan Roese #include <linux/config.h> 8a47a12beSStefan Roese #include <asm/processor.h> 9a47a12beSStefan Roese 10a47a12beSStefan Roese /* bytes per L1 cache line */ 11a47a12beSStefan Roese #if defined(CONFIG_8xx) || defined(CONFIG_IOP480) 12a47a12beSStefan Roese #define L1_CACHE_SHIFT 4 13a47a12beSStefan Roese #elif defined(CONFIG_PPC64BRIDGE) 14a47a12beSStefan Roese #define L1_CACHE_SHIFT 7 15a47a12beSStefan Roese #elif defined(CONFIG_E500MC) 16a47a12beSStefan Roese #define L1_CACHE_SHIFT 6 17a47a12beSStefan Roese #else 18a47a12beSStefan Roese #define L1_CACHE_SHIFT 5 19a47a12beSStefan Roese #endif 20a47a12beSStefan Roese 21a47a12beSStefan Roese #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 22a47a12beSStefan Roese 23a47a12beSStefan Roese /* 24*0991701aSAnton Staaf * Use the L1 data cache line size value for the minimum DMA buffer alignment 25*0991701aSAnton Staaf * on PowerPC. 26*0991701aSAnton Staaf */ 27*0991701aSAnton Staaf #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 28*0991701aSAnton Staaf 29*0991701aSAnton Staaf /* 30a47a12beSStefan Roese * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too 31a47a12beSStefan Roese */ 32a47a12beSStefan Roese #ifndef CONFIG_SYS_CACHELINE_SIZE 33a47a12beSStefan Roese #define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES 34a47a12beSStefan Roese #endif 35a47a12beSStefan Roese 36a47a12beSStefan Roese #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) 37a47a12beSStefan Roese #define L1_CACHE_PAGES 8 38a47a12beSStefan Roese 39a47a12beSStefan Roese #define SMP_CACHE_BYTES L1_CACHE_BYTES 40a47a12beSStefan Roese 41a47a12beSStefan Roese #ifdef MODULE 42a47a12beSStefan Roese #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) 43a47a12beSStefan Roese #else 44a47a12beSStefan Roese #define __cacheline_aligned \ 45a47a12beSStefan Roese __attribute__((__aligned__(L1_CACHE_BYTES), \ 46a47a12beSStefan Roese __section__(".data.cacheline_aligned"))) 47a47a12beSStefan Roese #endif 48a47a12beSStefan Roese 49a47a12beSStefan Roese #if defined(__KERNEL__) && !defined(__ASSEMBLY__) 50a47a12beSStefan Roese extern void flush_dcache_range(unsigned long start, unsigned long stop); 51a47a12beSStefan Roese extern void clean_dcache_range(unsigned long start, unsigned long stop); 52a47a12beSStefan Roese extern void invalidate_dcache_range(unsigned long start, unsigned long stop); 53a47a12beSStefan Roese extern void flush_dcache(void); 54a47a12beSStefan Roese extern void invalidate_dcache(void); 55a47a12beSStefan Roese extern void invalidate_icache(void); 56a47a12beSStefan Roese #ifdef CONFIG_SYS_INIT_RAM_LOCK 57a47a12beSStefan Roese extern void unlock_ram_in_cache(void); 58a47a12beSStefan Roese #endif /* CONFIG_SYS_INIT_RAM_LOCK */ 59a47a12beSStefan Roese #endif /* __ASSEMBLY__ */ 60a47a12beSStefan Roese 61a47a12beSStefan Roese /* prep registers for L2 */ 62a47a12beSStefan Roese #define CACHECRBA 0x80000823 /* Cache configuration register address */ 63a47a12beSStefan Roese #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ 64a47a12beSStefan Roese #define L2CACHE_512KB 0x00 /* 512KB */ 65a47a12beSStefan Roese #define L2CACHE_256KB 0x01 /* 256KB */ 66a47a12beSStefan Roese #define L2CACHE_1MB 0x02 /* 1MB */ 67a47a12beSStefan Roese #define L2CACHE_NONE 0x03 /* NONE */ 68a47a12beSStefan Roese #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ 69a47a12beSStefan Roese 70a47a12beSStefan Roese #ifdef CONFIG_8xx 71a47a12beSStefan Roese /* Cache control on the MPC8xx is provided through some additional 72a47a12beSStefan Roese * special purpose registers. 73a47a12beSStefan Roese */ 74a47a12beSStefan Roese #define IC_CST 560 /* Instruction cache control/status */ 75a47a12beSStefan Roese #define IC_ADR 561 /* Address needed for some commands */ 76a47a12beSStefan Roese #define IC_DAT 562 /* Read-only data register */ 77a47a12beSStefan Roese #define DC_CST 568 /* Data cache control/status */ 78a47a12beSStefan Roese #define DC_ADR 569 /* Address needed for some commands */ 79a47a12beSStefan Roese #define DC_DAT 570 /* Read-only data register */ 80a47a12beSStefan Roese 81a47a12beSStefan Roese /* Commands. Only the first few are available to the instruction cache. 82a47a12beSStefan Roese */ 83a47a12beSStefan Roese #define IDC_ENABLE 0x02000000 /* Cache enable */ 84a47a12beSStefan Roese #define IDC_DISABLE 0x04000000 /* Cache disable */ 85a47a12beSStefan Roese #define IDC_LDLCK 0x06000000 /* Load and lock */ 86a47a12beSStefan Roese #define IDC_UNLINE 0x08000000 /* Unlock line */ 87a47a12beSStefan Roese #define IDC_UNALL 0x0a000000 /* Unlock all */ 88a47a12beSStefan Roese #define IDC_INVALL 0x0c000000 /* Invalidate all */ 89a47a12beSStefan Roese 90a47a12beSStefan Roese #define DC_FLINE 0x0e000000 /* Flush data cache line */ 91a47a12beSStefan Roese #define DC_SFWT 0x01000000 /* Set forced writethrough mode */ 92a47a12beSStefan Roese #define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ 93a47a12beSStefan Roese #define DC_SLES 0x05000000 /* Set little endian swap mode */ 94a47a12beSStefan Roese #define DC_CLES 0x07000000 /* Clear little endian swap mode */ 95a47a12beSStefan Roese 96a47a12beSStefan Roese /* Status. 97a47a12beSStefan Roese */ 98a47a12beSStefan Roese #define IDC_ENABLED 0x80000000 /* Cache is enabled */ 99a47a12beSStefan Roese #define IDC_CERR1 0x00200000 /* Cache error 1 */ 100a47a12beSStefan Roese #define IDC_CERR2 0x00100000 /* Cache error 2 */ 101a47a12beSStefan Roese #define IDC_CERR3 0x00080000 /* Cache error 3 */ 102a47a12beSStefan Roese 103a47a12beSStefan Roese #define DC_DFWT 0x40000000 /* Data cache is forced write through */ 104a47a12beSStefan Roese #define DC_LES 0x20000000 /* Caches are little endian mode */ 105a47a12beSStefan Roese #endif /* CONFIG_8xx */ 106a47a12beSStefan Roese 107a47a12beSStefan Roese #endif 108