1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and 5 * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains 6 * cpu specific common code for 85xx/86xx processors. 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <config.h> 27 #include <common.h> 28 #include <command.h> 29 #include <tsec.h> 30 #include <netdev.h> 31 #include <asm/cache.h> 32 #include <asm/io.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 struct cpu_type cpu_type_list [] = { 37 #if defined(CONFIG_MPC85xx) 38 CPU_TYPE_ENTRY(8533, 8533, 1), 39 CPU_TYPE_ENTRY(8533, 8533_E, 1), 40 CPU_TYPE_ENTRY(8535, 8535, 1), 41 CPU_TYPE_ENTRY(8535, 8535_E, 1), 42 CPU_TYPE_ENTRY(8536, 8536, 1), 43 CPU_TYPE_ENTRY(8536, 8536_E, 1), 44 CPU_TYPE_ENTRY(8540, 8540, 1), 45 CPU_TYPE_ENTRY(8541, 8541, 1), 46 CPU_TYPE_ENTRY(8541, 8541_E, 1), 47 CPU_TYPE_ENTRY(8543, 8543, 1), 48 CPU_TYPE_ENTRY(8543, 8543_E, 1), 49 CPU_TYPE_ENTRY(8544, 8544, 1), 50 CPU_TYPE_ENTRY(8544, 8544_E, 1), 51 CPU_TYPE_ENTRY(8545, 8545, 1), 52 CPU_TYPE_ENTRY(8545, 8545_E, 1), 53 CPU_TYPE_ENTRY(8547, 8547_E, 1), 54 CPU_TYPE_ENTRY(8548, 8548, 1), 55 CPU_TYPE_ENTRY(8548, 8548_E, 1), 56 CPU_TYPE_ENTRY(8555, 8555, 1), 57 CPU_TYPE_ENTRY(8555, 8555_E, 1), 58 CPU_TYPE_ENTRY(8560, 8560, 1), 59 CPU_TYPE_ENTRY(8567, 8567, 1), 60 CPU_TYPE_ENTRY(8567, 8567_E, 1), 61 CPU_TYPE_ENTRY(8568, 8568, 1), 62 CPU_TYPE_ENTRY(8568, 8568_E, 1), 63 CPU_TYPE_ENTRY(8569, 8569, 1), 64 CPU_TYPE_ENTRY(8569, 8569_E, 1), 65 CPU_TYPE_ENTRY(8572, 8572, 2), 66 CPU_TYPE_ENTRY(8572, 8572_E, 2), 67 CPU_TYPE_ENTRY(P1010, P1010, 1), 68 CPU_TYPE_ENTRY(P1010, P1010_E, 1), 69 CPU_TYPE_ENTRY(P1011, P1011, 1), 70 CPU_TYPE_ENTRY(P1011, P1011_E, 1), 71 CPU_TYPE_ENTRY(P1012, P1012, 1), 72 CPU_TYPE_ENTRY(P1012, P1012_E, 1), 73 CPU_TYPE_ENTRY(P1013, P1013, 1), 74 CPU_TYPE_ENTRY(P1013, P1013_E, 1), 75 CPU_TYPE_ENTRY(P1014, P1014_E, 1), 76 CPU_TYPE_ENTRY(P1014, P1014, 1), 77 CPU_TYPE_ENTRY(P1017, P1017, 1), 78 CPU_TYPE_ENTRY(P1017, P1017, 1), 79 CPU_TYPE_ENTRY(P1020, P1020, 2), 80 CPU_TYPE_ENTRY(P1020, P1020_E, 2), 81 CPU_TYPE_ENTRY(P1021, P1021, 2), 82 CPU_TYPE_ENTRY(P1021, P1021_E, 2), 83 CPU_TYPE_ENTRY(P1022, P1022, 2), 84 CPU_TYPE_ENTRY(P1022, P1022_E, 2), 85 CPU_TYPE_ENTRY(P1023, P1023, 2), 86 CPU_TYPE_ENTRY(P1023, P1023_E, 2), 87 CPU_TYPE_ENTRY(P2010, P2010, 1), 88 CPU_TYPE_ENTRY(P2010, P2010_E, 1), 89 CPU_TYPE_ENTRY(P2020, P2020, 2), 90 CPU_TYPE_ENTRY(P2020, P2020_E, 2), 91 CPU_TYPE_ENTRY(P2040, P2040, 4), 92 CPU_TYPE_ENTRY(P2040, P2040_E, 4), 93 CPU_TYPE_ENTRY(P3041, P3041, 4), 94 CPU_TYPE_ENTRY(P3041, P3041_E, 4), 95 CPU_TYPE_ENTRY(P4040, P4040, 4), 96 CPU_TYPE_ENTRY(P4040, P4040_E, 4), 97 CPU_TYPE_ENTRY(P4080, P4080, 8), 98 CPU_TYPE_ENTRY(P4080, P4080_E, 8), 99 CPU_TYPE_ENTRY(P5010, P5010, 1), 100 CPU_TYPE_ENTRY(P5010, P5010_E, 1), 101 CPU_TYPE_ENTRY(P5020, P5020, 2), 102 CPU_TYPE_ENTRY(P5020, P5020_E, 2), 103 #elif defined(CONFIG_MPC86xx) 104 CPU_TYPE_ENTRY(8610, 8610, 1), 105 CPU_TYPE_ENTRY(8641, 8641, 2), 106 CPU_TYPE_ENTRY(8641D, 8641D, 2), 107 #endif 108 }; 109 110 struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1); 111 112 struct cpu_type *identify_cpu(u32 ver) 113 { 114 int i; 115 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) { 116 if (cpu_type_list[i].soc_ver == ver) 117 return &cpu_type_list[i]; 118 } 119 return &cpu_type_unknown; 120 } 121 122 int cpu_numcores() { 123 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; 124 struct cpu_type *cpu = gd->cpu; 125 126 /* better to query feature reporting register than just assume 1 */ 127 #define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 128 #define MPC8xxx_PICFRR_NCPU_SHIFT 8 129 if (cpu == &cpu_type_unknown) 130 return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> 131 MPC8xxx_PICFRR_NCPU_SHIFT) + 1; 132 133 return cpu->num_cores; 134 } 135 136 int probecpu (void) 137 { 138 uint svr; 139 uint ver; 140 141 svr = get_svr(); 142 ver = SVR_SOC_VER(svr); 143 144 gd->cpu = identify_cpu(ver); 145 146 return 0; 147 } 148 149 /* 150 * Initializes on-chip ethernet controllers. 151 * to override, implement board_eth_init() 152 */ 153 int cpu_eth_init(bd_t *bis) 154 { 155 #if defined(CONFIG_ETHER_ON_FCC) 156 fec_initialize(bis); 157 #endif 158 159 #if defined(CONFIG_UEC_ETH) 160 uec_standard_init(bis); 161 #endif 162 163 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) 164 tsec_standard_init(bis); 165 #endif 166 167 return 0; 168 } 169