1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * Copyright 2009-2010 Freescale Semiconductor, Inc. 3*a47a12beSStefan Roese * 4*a47a12beSStefan Roese * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and 5*a47a12beSStefan Roese * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains 6*a47a12beSStefan Roese * cpu specific common code for 85xx/86xx processors. 7*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 8*a47a12beSStefan Roese * project. 9*a47a12beSStefan Roese * 10*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 11*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 12*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 13*a47a12beSStefan Roese * the License, or (at your option) any later version. 14*a47a12beSStefan Roese * 15*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 16*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*a47a12beSStefan Roese * GNU General Public License for more details. 19*a47a12beSStefan Roese * 20*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 21*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 22*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23*a47a12beSStefan Roese * MA 02111-1307 USA 24*a47a12beSStefan Roese */ 25*a47a12beSStefan Roese 26*a47a12beSStefan Roese #include <config.h> 27*a47a12beSStefan Roese #include <common.h> 28*a47a12beSStefan Roese #include <command.h> 29*a47a12beSStefan Roese #include <tsec.h> 30*a47a12beSStefan Roese #include <netdev.h> 31*a47a12beSStefan Roese #include <asm/cache.h> 32*a47a12beSStefan Roese #include <asm/io.h> 33*a47a12beSStefan Roese 34*a47a12beSStefan Roese DECLARE_GLOBAL_DATA_PTR; 35*a47a12beSStefan Roese 36*a47a12beSStefan Roese struct cpu_type cpu_type_list [] = { 37*a47a12beSStefan Roese #if defined(CONFIG_MPC85xx) 38*a47a12beSStefan Roese CPU_TYPE_ENTRY(8533, 8533, 1), 39*a47a12beSStefan Roese CPU_TYPE_ENTRY(8533, 8533_E, 1), 40*a47a12beSStefan Roese CPU_TYPE_ENTRY(8535, 8535, 1), 41*a47a12beSStefan Roese CPU_TYPE_ENTRY(8535, 8535_E, 1), 42*a47a12beSStefan Roese CPU_TYPE_ENTRY(8536, 8536, 1), 43*a47a12beSStefan Roese CPU_TYPE_ENTRY(8536, 8536_E, 1), 44*a47a12beSStefan Roese CPU_TYPE_ENTRY(8540, 8540, 1), 45*a47a12beSStefan Roese CPU_TYPE_ENTRY(8541, 8541, 1), 46*a47a12beSStefan Roese CPU_TYPE_ENTRY(8541, 8541_E, 1), 47*a47a12beSStefan Roese CPU_TYPE_ENTRY(8543, 8543, 1), 48*a47a12beSStefan Roese CPU_TYPE_ENTRY(8543, 8543_E, 1), 49*a47a12beSStefan Roese CPU_TYPE_ENTRY(8544, 8544, 1), 50*a47a12beSStefan Roese CPU_TYPE_ENTRY(8544, 8544_E, 1), 51*a47a12beSStefan Roese CPU_TYPE_ENTRY(8545, 8545, 1), 52*a47a12beSStefan Roese CPU_TYPE_ENTRY(8545, 8545_E, 1), 53*a47a12beSStefan Roese CPU_TYPE_ENTRY(8547, 8547_E, 1), 54*a47a12beSStefan Roese CPU_TYPE_ENTRY(8548, 8548, 1), 55*a47a12beSStefan Roese CPU_TYPE_ENTRY(8548, 8548_E, 1), 56*a47a12beSStefan Roese CPU_TYPE_ENTRY(8555, 8555, 1), 57*a47a12beSStefan Roese CPU_TYPE_ENTRY(8555, 8555_E, 1), 58*a47a12beSStefan Roese CPU_TYPE_ENTRY(8560, 8560, 1), 59*a47a12beSStefan Roese CPU_TYPE_ENTRY(8567, 8567, 1), 60*a47a12beSStefan Roese CPU_TYPE_ENTRY(8567, 8567_E, 1), 61*a47a12beSStefan Roese CPU_TYPE_ENTRY(8568, 8568, 1), 62*a47a12beSStefan Roese CPU_TYPE_ENTRY(8568, 8568_E, 1), 63*a47a12beSStefan Roese CPU_TYPE_ENTRY(8569, 8569, 1), 64*a47a12beSStefan Roese CPU_TYPE_ENTRY(8569, 8569_E, 1), 65*a47a12beSStefan Roese CPU_TYPE_ENTRY(8572, 8572, 2), 66*a47a12beSStefan Roese CPU_TYPE_ENTRY(8572, 8572_E, 2), 67*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1011, P1011, 1), 68*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1011, P1011_E, 1), 69*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1012, P1012, 1), 70*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1012, P1012_E, 1), 71*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1013, P1013, 1), 72*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1013, P1013_E, 1), 73*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1020, P1020, 2), 74*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1020, P1020_E, 2), 75*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1021, P1021, 2), 76*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1021, P1021_E, 2), 77*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1022, P1022, 2), 78*a47a12beSStefan Roese CPU_TYPE_ENTRY(P1022, P1022_E, 2), 79*a47a12beSStefan Roese CPU_TYPE_ENTRY(P2010, P2010, 1), 80*a47a12beSStefan Roese CPU_TYPE_ENTRY(P2010, P2010_E, 1), 81*a47a12beSStefan Roese CPU_TYPE_ENTRY(P2020, P2020, 2), 82*a47a12beSStefan Roese CPU_TYPE_ENTRY(P2020, P2020_E, 2), 83*a47a12beSStefan Roese CPU_TYPE_ENTRY(P4040, P4040, 4), 84*a47a12beSStefan Roese CPU_TYPE_ENTRY(P4040, P4040_E, 4), 85*a47a12beSStefan Roese CPU_TYPE_ENTRY(P4080, P4080, 8), 86*a47a12beSStefan Roese CPU_TYPE_ENTRY(P4080, P4080_E, 8), 87*a47a12beSStefan Roese #elif defined(CONFIG_MPC86xx) 88*a47a12beSStefan Roese CPU_TYPE_ENTRY(8610, 8610, 1), 89*a47a12beSStefan Roese CPU_TYPE_ENTRY(8641, 8641, 2), 90*a47a12beSStefan Roese CPU_TYPE_ENTRY(8641D, 8641D, 2), 91*a47a12beSStefan Roese #endif 92*a47a12beSStefan Roese }; 93*a47a12beSStefan Roese 94*a47a12beSStefan Roese struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1); 95*a47a12beSStefan Roese 96*a47a12beSStefan Roese struct cpu_type *identify_cpu(u32 ver) 97*a47a12beSStefan Roese { 98*a47a12beSStefan Roese int i; 99*a47a12beSStefan Roese for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) { 100*a47a12beSStefan Roese if (cpu_type_list[i].soc_ver == ver) 101*a47a12beSStefan Roese return &cpu_type_list[i]; 102*a47a12beSStefan Roese } 103*a47a12beSStefan Roese return &cpu_type_unknown; 104*a47a12beSStefan Roese } 105*a47a12beSStefan Roese 106*a47a12beSStefan Roese int cpu_numcores() { 107*a47a12beSStefan Roese struct cpu_type *cpu; 108*a47a12beSStefan Roese cpu = gd->cpu; 109*a47a12beSStefan Roese return cpu->num_cores; 110*a47a12beSStefan Roese } 111*a47a12beSStefan Roese 112*a47a12beSStefan Roese int probecpu (void) 113*a47a12beSStefan Roese { 114*a47a12beSStefan Roese uint svr; 115*a47a12beSStefan Roese uint ver; 116*a47a12beSStefan Roese 117*a47a12beSStefan Roese svr = get_svr(); 118*a47a12beSStefan Roese ver = SVR_SOC_VER(svr); 119*a47a12beSStefan Roese 120*a47a12beSStefan Roese gd->cpu = identify_cpu(ver); 121*a47a12beSStefan Roese 122*a47a12beSStefan Roese return 0; 123*a47a12beSStefan Roese } 124*a47a12beSStefan Roese 125*a47a12beSStefan Roese /* 126*a47a12beSStefan Roese * Initializes on-chip ethernet controllers. 127*a47a12beSStefan Roese * to override, implement board_eth_init() 128*a47a12beSStefan Roese */ 129*a47a12beSStefan Roese int cpu_eth_init(bd_t *bis) 130*a47a12beSStefan Roese { 131*a47a12beSStefan Roese #if defined(CONFIG_ETHER_ON_FCC) 132*a47a12beSStefan Roese fec_initialize(bis); 133*a47a12beSStefan Roese #endif 134*a47a12beSStefan Roese 135*a47a12beSStefan Roese #if defined(CONFIG_UEC_ETH) 136*a47a12beSStefan Roese uec_standard_init(bis); 137*a47a12beSStefan Roese #endif 138*a47a12beSStefan Roese 139*a47a12beSStefan Roese #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) 140*a47a12beSStefan Roese tsec_standard_init(bis); 141*a47a12beSStefan Roese #endif 142*a47a12beSStefan Roese 143*a47a12beSStefan Roese return 0; 144*a47a12beSStefan Roese } 145