1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <mpc8xx.h> 10 #include <asm/processor.h> 11 #include <asm/io.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 void get_brgclk(uint sccr) 16 { 17 uint divider = 0; 18 19 switch((sccr&SCCR_DFBRG11)>>11){ 20 case 0: 21 divider = 1; 22 break; 23 case 1: 24 divider = 4; 25 break; 26 case 2: 27 divider = 16; 28 break; 29 case 3: 30 divider = 64; 31 break; 32 } 33 gd->arch.brg_clk = gd->cpu_clk/divider; 34 } 35 36 /* 37 * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ 38 */ 39 int get_clocks (void) 40 { 41 uint immr = get_immr (0); /* Return full IMMR contents */ 42 immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000); 43 uint sccr = in_be32(&immap->im_clkrst.car_sccr); 44 /* 45 * If for some reason measuring the gclk frequency won't 46 * work, we return the hardwired value. 47 * (For example, the cogent CMA286-60 CPU module has no 48 * separate oscillator for PITRTCLK) 49 */ 50 gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; 51 52 if ((sccr & SCCR_EBDF11) == 0) { 53 /* No Bus Divider active */ 54 gd->bus_clk = gd->cpu_clk; 55 } else { 56 /* The MPC8xx has only one BDF: half clock speed */ 57 gd->bus_clk = gd->cpu_clk / 2; 58 } 59 60 get_brgclk(sccr); 61 62 return (0); 63 } 64