1 /* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <watchdog.h> 10 11 #include <mpc8xx.h> 12 #include <commproc.h> 13 #include <asm/io.h> 14 15 /* 16 * Breath some life into the CPU... 17 * 18 * Set up the memory map, 19 * initialize a bunch of registers, 20 * initialize the UPM's 21 */ 22 void cpu_init_f(immap_t __iomem *immr) 23 { 24 memctl8xx_t __iomem *memctl = &immr->im_memctl; 25 ulong reg; 26 27 /* SYPCR - contains watchdog control (11-9) */ 28 29 out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR); 30 31 #if defined(CONFIG_WATCHDOG) 32 reset_8xx_watchdog (immr); 33 #endif /* CONFIG_WATCHDOG */ 34 35 /* SIUMCR - contains debug pin configuration (11-6) */ 36 setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR); 37 /* initialize timebase status and control register (11-26) */ 38 /* unlock TBSCRK */ 39 40 out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY); 41 out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR); 42 43 /* initialize the PIT (11-31) */ 44 45 out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY); 46 out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR); 47 48 /* System integration timers. Don't change EBDF! (15-27) */ 49 50 out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY); 51 clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK, 52 CONFIG_SYS_SCCR); 53 54 /* PLL (CPU clock) settings (15-30) */ 55 56 out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY); 57 58 /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to 59 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, 60 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF 61 * field value. 62 * 63 * For newer (starting MPC866) chips PLPRCR layout is different. 64 */ 65 #ifdef CONFIG_SYS_PLPRCR 66 if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/ 67 out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR); 68 else /* isolate MF-related fields and reset control bits */ 69 clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK, 70 CONFIG_SYS_PLPRCR); 71 #endif 72 73 /* 74 * Memory Controller: 75 */ 76 77 /* Clear everything except Port Size bits & add the "Bank Valid" bit */ 78 clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V); 79 80 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at 81 * preliminary addresses - these have to be modified later 82 * when FLASH size has been determined 83 * 84 * Depending on the size of the memory region defined by 85 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the 86 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't 87 * map CONFIG_SYS_MONITOR_BASE. 88 * 89 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is 90 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000. 91 * 92 * If BR0 wasn't loaded with address base 0xff000000, then BR0's 93 * base address remains as 0x00000000. However, the address mask 94 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped 95 * into the Bank0. 96 * 97 * This is why CONFIG_IVMS8 and similar boards must load BR0 with 98 * CONFIG_SYS_BR0_PRELIM in advance. 99 * 100 * [Thanks to Michael Liao for this explanation. 101 * I owe him a free beer. - wd] 102 */ 103 104 #if defined(CONFIG_SYS_OR0_REMAP) 105 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP); 106 #endif 107 #if defined(CONFIG_SYS_OR1_REMAP) 108 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP); 109 #endif 110 #if defined(CONFIG_SYS_OR5_REMAP) 111 out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP); 112 #endif 113 114 /* now restrict to preliminary range */ 115 out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM); 116 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM); 117 118 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) 119 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM); 120 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM); 121 #endif 122 123 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 124 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM); 125 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM); 126 #endif 127 128 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) 129 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM); 130 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM); 131 #endif 132 133 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) 134 out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM); 135 out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM); 136 #endif 137 138 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) 139 out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM); 140 out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM); 141 #endif 142 143 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) 144 out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM); 145 out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM); 146 #endif 147 148 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) 149 out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM); 150 out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM); 151 #endif 152 153 /* 154 * Reset CPM 155 */ 156 out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG); 157 /* Spin until command processed */ 158 while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG) 159 ; 160 } 161 162 /* 163 * initialize higher level parts of CPU like timers 164 */ 165 int cpu_init_r (void) 166 { 167 return (0); 168 } 169