xref: /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/Kconfig (revision b1e41d1ceedf0fe90c7873bf9dfddd3690ccc11d)
1menu "mpc8xx CPU"
2	depends on 8xx
3
4config SYS_CPU
5	default "mpc8xx"
6
7choice
8	prompt "Target select"
9	optional
10
11endchoice
12
13choice
14	prompt "CPU select"
15	default MPC866
16
17config MPC866
18	bool "MPC866"
19
20config MPC885
21	bool "MPC885"
22
23endchoice
24
25config 8xx_GCLK_FREQ
26	int "CPU GCLK Frequency"
27
28comment "Specific commands"
29
30config CMD_IMMAP
31	bool "Enable various commands to dump IMMR information"
32	help
33	  This enables various commands such as:
34
35	    siuinfo - print System Interface Unit (SIU) registers
36	    memcinfo - print Memory Controller registers
37
38comment "Configuration Registers"
39
40config SYS_SIUMCR
41	hex "SIUMCR register"
42	help
43	  SIU Module Configuration (11-6)
44
45config SYS_SYPCR
46	hex "SYPCR register"
47	help
48	  System Protection Control (11-9)
49
50config SYS_TBSCR
51	hex "TBSCR register"
52	help
53	  Time Base Status and Control (11-26)
54
55config SYS_PISCR
56	hex "PISCR register"
57	help
58	  Periodic Interrupt Status and Control (11-31)
59
60config SYS_PLPRCR_BOOL
61	bool "Customise PLPRCR"
62
63config SYS_PLPRCR
64	hex "PLPRCR register"
65	depends on SYS_PLPRCR_BOOL
66	help
67	  PLL, Low-Power, and Reset Control Register (15-30)
68
69config SYS_SCCR
70	hex "SCCR register"
71	help
72	  System Clock and reset Control Register (15-27)
73
74config SYS_SCCR_MASK
75	hex "MASK for setting SCCR register"
76
77config SYS_DER
78	hex "DER register"
79	help
80	  Debug Event Register (37-47)
81
82comment "Memory mapping"
83
84config SYS_BR0_PRELIM
85	hex "Preliminary value for BR0"
86
87config SYS_OR0_PRELIM
88	hex "Preliminary value for OR0"
89
90config SYS_BR1_PRELIM_BOOL
91	bool "Define Bank 1"
92
93config SYS_BR1_PRELIM
94	hex "Preliminary value for BR1"
95	depends on SYS_BR1_PRELIM_BOOL
96
97config SYS_OR1_PRELIM
98	hex "Preliminary value for OR1"
99	depends on SYS_BR1_PRELIM_BOOL
100
101config SYS_BR2_PRELIM_BOOL
102	bool "Define Bank 2"
103
104config SYS_BR2_PRELIM
105	hex "Preliminary value for BR2"
106	depends on SYS_BR2_PRELIM_BOOL
107
108config SYS_OR2_PRELIM
109	hex "Preliminary value for OR2"
110	depends on SYS_BR2_PRELIM_BOOL
111
112config SYS_BR3_PRELIM_BOOL
113	bool "Define Bank 3"
114
115config SYS_BR3_PRELIM
116	hex "Preliminary value for BR3"
117	depends on SYS_BR3_PRELIM_BOOL
118
119config SYS_OR3_PRELIM
120	hex "Preliminary value for OR3"
121	depends on SYS_BR3_PRELIM_BOOL
122
123config SYS_BR4_PRELIM_BOOL
124	bool "Define Bank 4"
125
126config SYS_BR4_PRELIM
127	hex "Preliminary value for BR4"
128	depends on SYS_BR4_PRELIM_BOOL
129
130config SYS_OR4_PRELIM
131	hex "Preliminary value for OR4"
132	depends on SYS_BR4_PRELIM_BOOL
133
134config SYS_BR5_PRELIM_BOOL
135	bool "Define Bank 5"
136
137config SYS_BR5_PRELIM
138	hex "Preliminary value for BR5"
139	depends on SYS_BR5_PRELIM_BOOL
140
141config SYS_OR5_PRELIM
142	hex "Preliminary value for OR5"
143	depends on SYS_BR5_PRELIM_BOOL
144
145config SYS_BR6_PRELIM_BOOL
146	bool "Define Bank 6"
147
148config SYS_BR6_PRELIM
149	hex "Preliminary value for BR6"
150	depends on SYS_BR6_PRELIM_BOOL
151
152config SYS_OR6_PRELIM
153	hex "Preliminary value for OR6"
154	depends on SYS_BR6_PRELIM_BOOL
155
156config SYS_BR7_PRELIM_BOOL
157	bool "Define Bank 7"
158
159config SYS_BR7_PRELIM
160	hex "Preliminary value for BR7"
161	depends on SYS_BR7_PRELIM_BOOL
162
163config SYS_OR7_PRELIM
164	hex "Preliminary value for OR7"
165	depends on SYS_BR7_PRELIM_BOOL
166
167config SYS_IMMR
168	hex "Value for IMMR"
169
170endmenu
171