1a47a12beSStefan Roese/* 2a47a12beSStefan Roese * Copyright 2004, 2007 Freescale Semiconductor. 3a47a12beSStefan Roese * Srikanth Srinivasan <srikanth.srinivaan@freescale.com> 4a47a12beSStefan Roese * 5a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6a47a12beSStefan Roese * project. 7a47a12beSStefan Roese * 8a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11a47a12beSStefan Roese * the License, or (at your option) any later version. 12a47a12beSStefan Roese * 13a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16a47a12beSStefan Roese * GNU General Public License for more details. 17a47a12beSStefan Roese * 18a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21a47a12beSStefan Roese * MA 02111-1307 USA 22a47a12beSStefan Roese */ 23a47a12beSStefan Roese 24a47a12beSStefan Roese/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards 25a47a12beSStefan Roese * 26a47a12beSStefan Roese * 27a47a12beSStefan Roese * The processor starts at 0xfff00100 and the code is executed 28a47a12beSStefan Roese * from flash. The code is organized to be at an other address 29a47a12beSStefan Roese * in memory, but as long we don't jump around before relocating. 30a47a12beSStefan Roese * board_init lies at a quite high address and when the cpu has 31a47a12beSStefan Roese * jumped there, everything is ok. 32a47a12beSStefan Roese */ 33*25ddd1fbSWolfgang Denk#include <asm-offsets.h> 34a47a12beSStefan Roese#include <config.h> 35a47a12beSStefan Roese#include <mpc86xx.h> 36a47a12beSStefan Roese#include <timestamp.h> 37a47a12beSStefan Roese#include <version.h> 38a47a12beSStefan Roese 39a47a12beSStefan Roese#include <ppc_asm.tmpl> 40a47a12beSStefan Roese#include <ppc_defs.h> 41a47a12beSStefan Roese 42a47a12beSStefan Roese#include <asm/cache.h> 43a47a12beSStefan Roese#include <asm/mmu.h> 44d98b0523SPeter Tyser#include <asm/u-boot.h> 45a47a12beSStefan Roese 46a47a12beSStefan Roese#ifndef CONFIG_IDENT_STRING 47a47a12beSStefan Roese#define CONFIG_IDENT_STRING "" 48a47a12beSStefan Roese#endif 49a47a12beSStefan Roese 50a47a12beSStefan Roese/* 51a47a12beSStefan Roese * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions 52a47a12beSStefan Roese */ 53a47a12beSStefan Roese 54a47a12beSStefan Roese/* 55a47a12beSStefan Roese * Set up GOT: Global Offset Table 56a47a12beSStefan Roese * 57a47a12beSStefan Roese * Use r12 to access the GOT 58a47a12beSStefan Roese */ 59a47a12beSStefan Roese START_GOT 60a47a12beSStefan Roese GOT_ENTRY(_GOT2_TABLE_) 61a47a12beSStefan Roese GOT_ENTRY(_FIXUP_TABLE_) 62a47a12beSStefan Roese 63a47a12beSStefan Roese GOT_ENTRY(_start) 64a47a12beSStefan Roese GOT_ENTRY(_start_of_vectors) 65a47a12beSStefan Roese GOT_ENTRY(_end_of_vectors) 66a47a12beSStefan Roese GOT_ENTRY(transfer_to_handler) 67a47a12beSStefan Roese 68a47a12beSStefan Roese GOT_ENTRY(__init_end) 69a47a12beSStefan Roese GOT_ENTRY(_end) 70a47a12beSStefan Roese GOT_ENTRY(__bss_start) 71a47a12beSStefan Roese END_GOT 72a47a12beSStefan Roese 73a47a12beSStefan Roese/* 74a47a12beSStefan Roese * r3 - 1st arg to board_init(): IMMP pointer 75a47a12beSStefan Roese * r4 - 2nd arg to board_init(): boot flag 76a47a12beSStefan Roese */ 77a47a12beSStefan Roese .text 78a47a12beSStefan Roese .long 0x27051956 /* U-Boot Magic Number */ 79a47a12beSStefan Roese .globl version_string 80a47a12beSStefan Roeseversion_string: 81a47a12beSStefan Roese .ascii U_BOOT_VERSION 82a47a12beSStefan Roese .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" 83a47a12beSStefan Roese .ascii CONFIG_IDENT_STRING, "\0" 84a47a12beSStefan Roese 85a47a12beSStefan Roese . = EXC_OFF_SYS_RESET 86a47a12beSStefan Roese .globl _start 87a47a12beSStefan Roese_start: 88a47a12beSStefan Roese b boot_cold 89a47a12beSStefan Roese 90a47a12beSStefan Roese /* the boot code is located below the exception table */ 91a47a12beSStefan Roese 92a47a12beSStefan Roese .globl _start_of_vectors 93a47a12beSStefan Roese_start_of_vectors: 94a47a12beSStefan Roese 95a47a12beSStefan Roese/* Machine check */ 96a47a12beSStefan Roese STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 97a47a12beSStefan Roese 98a47a12beSStefan Roese/* Data Storage exception. */ 99a47a12beSStefan Roese STD_EXCEPTION(0x300, DataStorage, UnknownException) 100a47a12beSStefan Roese 101a47a12beSStefan Roese/* Instruction Storage exception. */ 102a47a12beSStefan Roese STD_EXCEPTION(0x400, InstStorage, UnknownException) 103a47a12beSStefan Roese 104a47a12beSStefan Roese/* External Interrupt exception. */ 105a47a12beSStefan Roese STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 106a47a12beSStefan Roese 107a47a12beSStefan Roese/* Alignment exception. */ 108a47a12beSStefan Roese . = 0x600 109a47a12beSStefan RoeseAlignment: 110a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 111a47a12beSStefan Roese mfspr r4,DAR 112a47a12beSStefan Roese stw r4,_DAR(r21) 113a47a12beSStefan Roese mfspr r5,DSISR 114a47a12beSStefan Roese stw r5,_DSISR(r21) 115a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 116a47a12beSStefan Roese EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 117a47a12beSStefan Roese 118a47a12beSStefan Roese/* Program check exception */ 119a47a12beSStefan Roese . = 0x700 120a47a12beSStefan RoeseProgramCheck: 121a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 122a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 123a47a12beSStefan Roese EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 124a47a12beSStefan Roese MSR_KERNEL, COPY_EE) 125a47a12beSStefan Roese 126a47a12beSStefan Roese STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 127a47a12beSStefan Roese 128a47a12beSStefan Roese /* I guess we could implement decrementer, and may have 129a47a12beSStefan Roese * to someday for timekeeping. 130a47a12beSStefan Roese */ 131a47a12beSStefan Roese STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 132a47a12beSStefan Roese STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 133a47a12beSStefan Roese STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 134a47a12beSStefan Roese STD_EXCEPTION(0xc00, SystemCall, UnknownException) 135a47a12beSStefan Roese STD_EXCEPTION(0xd00, SingleStep, UnknownException) 136a47a12beSStefan Roese STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 137a47a12beSStefan Roese STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 138a47a12beSStefan Roese STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) 139a47a12beSStefan Roese STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) 140a47a12beSStefan Roese STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) 141a47a12beSStefan Roese STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) 142a47a12beSStefan Roese STD_EXCEPTION(0x1400, DataTLBError, UnknownException) 143a47a12beSStefan Roese STD_EXCEPTION(0x1500, Reserved5, UnknownException) 144a47a12beSStefan Roese STD_EXCEPTION(0x1600, Reserved6, UnknownException) 145a47a12beSStefan Roese STD_EXCEPTION(0x1700, Reserved7, UnknownException) 146a47a12beSStefan Roese STD_EXCEPTION(0x1800, Reserved8, UnknownException) 147a47a12beSStefan Roese STD_EXCEPTION(0x1900, Reserved9, UnknownException) 148a47a12beSStefan Roese STD_EXCEPTION(0x1a00, ReservedA, UnknownException) 149a47a12beSStefan Roese STD_EXCEPTION(0x1b00, ReservedB, UnknownException) 150a47a12beSStefan Roese STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) 151a47a12beSStefan Roese STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) 152a47a12beSStefan Roese STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) 153a47a12beSStefan Roese STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) 154a47a12beSStefan Roese 155a47a12beSStefan Roese .globl _end_of_vectors 156a47a12beSStefan Roese_end_of_vectors: 157a47a12beSStefan Roese 158a47a12beSStefan Roese . = 0x2000 159a47a12beSStefan Roese 160a47a12beSStefan Roeseboot_cold: 161a47a12beSStefan Roese /* 162a47a12beSStefan Roese * NOTE: Only Cpu 0 will ever come here. Other cores go to an 163a47a12beSStefan Roese * address specified by the BPTR 164a47a12beSStefan Roese */ 165a47a12beSStefan Roese1: 166a47a12beSStefan Roese#ifdef CONFIG_SYS_RAMBOOT 167a47a12beSStefan Roese /* disable everything */ 168a47a12beSStefan Roese li r0, 0 169a47a12beSStefan Roese mtspr HID0, r0 170a47a12beSStefan Roese sync 171a47a12beSStefan Roese mtmsr 0 172a47a12beSStefan Roese#endif 173a47a12beSStefan Roese 174a47a12beSStefan Roese /* Invalidate BATs */ 175a47a12beSStefan Roese bl invalidate_bats 176a47a12beSStefan Roese sync 177a47a12beSStefan Roese /* Invalidate all of TLB before MMU turn on */ 178a47a12beSStefan Roese bl clear_tlbs 179a47a12beSStefan Roese sync 180a47a12beSStefan Roese 181a47a12beSStefan Roese#ifdef CONFIG_SYS_L2 182a47a12beSStefan Roese /* init the L2 cache */ 183a47a12beSStefan Roese lis r3, L2_INIT@h 184a47a12beSStefan Roese ori r3, r3, L2_INIT@l 185a47a12beSStefan Roese mtspr l2cr, r3 186a47a12beSStefan Roese /* invalidate the L2 cache */ 187a47a12beSStefan Roese bl l2cache_invalidate 188a47a12beSStefan Roese sync 189a47a12beSStefan Roese#endif 190a47a12beSStefan Roese 191a47a12beSStefan Roese /* 192a47a12beSStefan Roese * Calculate absolute address in FLASH and jump there 193a47a12beSStefan Roese *------------------------------------------------------*/ 194a47a12beSStefan Roese lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h 195a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l 196a47a12beSStefan Roese addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET 197a47a12beSStefan Roese mtlr r3 198a47a12beSStefan Roese blr 199a47a12beSStefan Roese 200a47a12beSStefan Roesein_flash: 201a47a12beSStefan Roese /* let the C-code set up the rest */ 202a47a12beSStefan Roese /* */ 203a47a12beSStefan Roese /* Be careful to keep code relocatable ! */ 204a47a12beSStefan Roese /*------------------------------------------------------*/ 205a47a12beSStefan Roese /* perform low-level init */ 206a47a12beSStefan Roese 207a47a12beSStefan Roese /* enable extended addressing */ 208a47a12beSStefan Roese bl enable_ext_addr 209a47a12beSStefan Roese 210a47a12beSStefan Roese /* setup the bats */ 211a47a12beSStefan Roese bl early_bats 212a47a12beSStefan Roese 213a47a12beSStefan Roese /* 214a47a12beSStefan Roese * Cache must be enabled here for stack-in-cache trick. 215a47a12beSStefan Roese * This means we need to enable the BATS. 216a47a12beSStefan Roese * Cache should be turned on after BATs, since by default 217a47a12beSStefan Roese * everything is write-through. 218a47a12beSStefan Roese */ 219a47a12beSStefan Roese 220a47a12beSStefan Roese /* enable address translation */ 221a47a12beSStefan Roese mfmsr r5 222a47a12beSStefan Roese ori r5, r5, (MSR_IR | MSR_DR) 223a47a12beSStefan Roese lis r3,addr_trans_enabled@h 224a47a12beSStefan Roese ori r3, r3, addr_trans_enabled@l 225a47a12beSStefan Roese mtspr SPRN_SRR0,r3 226a47a12beSStefan Roese mtspr SPRN_SRR1,r5 227a47a12beSStefan Roese rfi 228a47a12beSStefan Roese 229a47a12beSStefan Roeseaddr_trans_enabled: 230a47a12beSStefan Roese /* enable and invalidate the data cache */ 231a47a12beSStefan Roese/* bl l1dcache_enable */ 232a47a12beSStefan Roese bl dcache_enable 233a47a12beSStefan Roese sync 234a47a12beSStefan Roese 235a47a12beSStefan Roese#if 1 236a47a12beSStefan Roese bl icache_enable 237a47a12beSStefan Roese#endif 238a47a12beSStefan Roese 239a47a12beSStefan Roese#ifdef CONFIG_SYS_INIT_RAM_LOCK 240a47a12beSStefan Roese bl lock_ram_in_cache 241a47a12beSStefan Roese sync 242a47a12beSStefan Roese#endif 243a47a12beSStefan Roese 244a47a12beSStefan Roese#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 245a47a12beSStefan Roese bl setup_ccsrbar 246a47a12beSStefan Roese#endif 247a47a12beSStefan Roese 248a47a12beSStefan Roese /* set up the stack pointer in our newly created 249a47a12beSStefan Roese * cache-ram (r1) */ 250a47a12beSStefan Roese lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 251a47a12beSStefan Roese ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 252a47a12beSStefan Roese 253a47a12beSStefan Roese li r0, 0 /* Make room for stack frame header and */ 254a47a12beSStefan Roese stwu r0, -4(r1) /* clear final stack frame so that */ 255a47a12beSStefan Roese stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 256a47a12beSStefan Roese 257a47a12beSStefan Roese GET_GOT /* initialize GOT access */ 258a47a12beSStefan Roese 259a47a12beSStefan Roese /* run low-level CPU init code (from Flash) */ 260a47a12beSStefan Roese bl cpu_init_f 261a47a12beSStefan Roese sync 262a47a12beSStefan Roese 263a47a12beSStefan Roese#ifdef RUN_DIAG 264a47a12beSStefan Roese 265a47a12beSStefan Roese /* Load PX_AUX register address in r4 */ 266a47a12beSStefan Roese lis r4, PIXIS_BASE@h 267a47a12beSStefan Roese ori r4, r4, 0x6 268a47a12beSStefan Roese /* Load contents of PX_AUX in r3 bits 24 to 31*/ 269a47a12beSStefan Roese lbz r3, 0(r4) 270a47a12beSStefan Roese 271a47a12beSStefan Roese /* Mask and obtain the bit in r3 */ 272a47a12beSStefan Roese rlwinm. r3, r3, 0, 24, 24 273a47a12beSStefan Roese /* If not zero, jump and continue with u-boot */ 274a47a12beSStefan Roese bne diag_done 275a47a12beSStefan Roese 276a47a12beSStefan Roese /* Load back contents of PX_AUX in r3 bits 24 to 31 */ 277a47a12beSStefan Roese lbz r3, 0(r4) 278a47a12beSStefan Roese /* Set the MSB of the register value */ 279a47a12beSStefan Roese ori r3, r3, 0x80 280a47a12beSStefan Roese /* Write value in r3 back to PX_AUX */ 281a47a12beSStefan Roese stb r3, 0(r4) 282a47a12beSStefan Roese 283a47a12beSStefan Roese /* Get the address to jump to in r3*/ 284a47a12beSStefan Roese lis r3, CONFIG_SYS_DIAG_ADDR@h 285a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DIAG_ADDR@l 286a47a12beSStefan Roese 287a47a12beSStefan Roese /* Load the LR with the branch address */ 288a47a12beSStefan Roese mtlr r3 289a47a12beSStefan Roese 290a47a12beSStefan Roese /* Branch to diagnostic */ 291a47a12beSStefan Roese blr 292a47a12beSStefan Roese 293a47a12beSStefan Roesediag_done: 294a47a12beSStefan Roese#endif 295a47a12beSStefan Roese 296a47a12beSStefan Roese/* bl l2cache_enable */ 297a47a12beSStefan Roese 298a47a12beSStefan Roese /* run 1st part of board init code (from Flash) */ 299a47a12beSStefan Roese bl board_init_f 300a47a12beSStefan Roese sync 301a47a12beSStefan Roese 30252ebd9c1SPeter Tyser /* NOTREACHED - board_init_f() does not return */ 303a47a12beSStefan Roese 304a47a12beSStefan Roese .globl invalidate_bats 305a47a12beSStefan Roeseinvalidate_bats: 306a47a12beSStefan Roese 307a47a12beSStefan Roese li r0, 0 308a47a12beSStefan Roese /* invalidate BATs */ 309a47a12beSStefan Roese mtspr IBAT0U, r0 310a47a12beSStefan Roese mtspr IBAT1U, r0 311a47a12beSStefan Roese mtspr IBAT2U, r0 312a47a12beSStefan Roese mtspr IBAT3U, r0 313a47a12beSStefan Roese mtspr IBAT4U, r0 314a47a12beSStefan Roese mtspr IBAT5U, r0 315a47a12beSStefan Roese mtspr IBAT6U, r0 316a47a12beSStefan Roese mtspr IBAT7U, r0 317a47a12beSStefan Roese 318a47a12beSStefan Roese isync 319a47a12beSStefan Roese mtspr DBAT0U, r0 320a47a12beSStefan Roese mtspr DBAT1U, r0 321a47a12beSStefan Roese mtspr DBAT2U, r0 322a47a12beSStefan Roese mtspr DBAT3U, r0 323a47a12beSStefan Roese mtspr DBAT4U, r0 324a47a12beSStefan Roese mtspr DBAT5U, r0 325a47a12beSStefan Roese mtspr DBAT6U, r0 326a47a12beSStefan Roese mtspr DBAT7U, r0 327a47a12beSStefan Roese 328a47a12beSStefan Roese isync 329a47a12beSStefan Roese sync 330a47a12beSStefan Roese blr 331a47a12beSStefan Roese 332a47a12beSStefan Roese/* 333a47a12beSStefan Roese * early_bats: 334a47a12beSStefan Roese * 335a47a12beSStefan Roese * Set up bats needed early on - this is usually the BAT for the 336a47a12beSStefan Roese * stack-in-cache, the Flash, and CCSR space 337a47a12beSStefan Roese */ 338a47a12beSStefan Roese .globl early_bats 339a47a12beSStefan Roeseearly_bats: 340a47a12beSStefan Roese /* IBAT 3 */ 341a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT3L@h 342a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT3L@l 343a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT3U@h 344a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT3U@l 345a47a12beSStefan Roese mtspr IBAT3L, r4 346a47a12beSStefan Roese mtspr IBAT3U, r3 347a47a12beSStefan Roese isync 348a47a12beSStefan Roese 349a47a12beSStefan Roese /* DBAT 3 */ 350a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT3L@h 351a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT3L@l 352a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT3U@h 353a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT3U@l 354a47a12beSStefan Roese mtspr DBAT3L, r4 355a47a12beSStefan Roese mtspr DBAT3U, r3 356a47a12beSStefan Roese isync 357a47a12beSStefan Roese 358a47a12beSStefan Roese /* IBAT 5 */ 359a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT5L@h 360a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT5L@l 361a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT5U@h 362a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT5U@l 363a47a12beSStefan Roese mtspr IBAT5L, r4 364a47a12beSStefan Roese mtspr IBAT5U, r3 365a47a12beSStefan Roese isync 366a47a12beSStefan Roese 367a47a12beSStefan Roese /* DBAT 5 */ 368a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT5L@h 369a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT5L@l 370a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT5U@h 371a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT5U@l 372a47a12beSStefan Roese mtspr DBAT5L, r4 373a47a12beSStefan Roese mtspr DBAT5U, r3 374a47a12beSStefan Roese isync 375a47a12beSStefan Roese 376a47a12beSStefan Roese /* IBAT 6 */ 377a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT6L_EARLY@h 378a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l 379a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT6U_EARLY@h 380a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l 381a47a12beSStefan Roese mtspr IBAT6L, r4 382a47a12beSStefan Roese mtspr IBAT6U, r3 383a47a12beSStefan Roese isync 384a47a12beSStefan Roese 385a47a12beSStefan Roese /* DBAT 6 */ 386a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT6L_EARLY@h 387a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l 388a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT6U_EARLY@h 389a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l 390a47a12beSStefan Roese mtspr DBAT6L, r4 391a47a12beSStefan Roese mtspr DBAT6U, r3 392a47a12beSStefan Roese isync 393a47a12beSStefan Roese 394a47a12beSStefan Roese#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 395a47a12beSStefan Roese /* IBAT 7 */ 396a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h 397a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l 398a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h 399a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l 400a47a12beSStefan Roese mtspr IBAT7L, r4 401a47a12beSStefan Roese mtspr IBAT7U, r3 402a47a12beSStefan Roese isync 403a47a12beSStefan Roese 404a47a12beSStefan Roese /* DBAT 7 */ 405a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h 406a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l 407a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h 408a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l 409a47a12beSStefan Roese mtspr DBAT7L, r4 410a47a12beSStefan Roese mtspr DBAT7U, r3 411a47a12beSStefan Roese isync 412a47a12beSStefan Roese#endif 413a47a12beSStefan Roese blr 414a47a12beSStefan Roese 415a47a12beSStefan Roese .globl clear_tlbs 416a47a12beSStefan Roeseclear_tlbs: 417a47a12beSStefan Roese addis r3, 0, 0x0000 418a47a12beSStefan Roese addis r5, 0, 0x4 419a47a12beSStefan Roese isync 420a47a12beSStefan Roesetlblp: 421a47a12beSStefan Roese tlbie r3 422a47a12beSStefan Roese sync 423a47a12beSStefan Roese addi r3, r3, 0x1000 424a47a12beSStefan Roese cmp 0, 0, r3, r5 425a47a12beSStefan Roese blt tlblp 426a47a12beSStefan Roese blr 427a47a12beSStefan Roese 428a47a12beSStefan Roese .globl disable_addr_trans 429a47a12beSStefan Roesedisable_addr_trans: 430a47a12beSStefan Roese /* disable address translation */ 431a47a12beSStefan Roese mflr r4 432a47a12beSStefan Roese mfmsr r3 433a47a12beSStefan Roese andi. r0, r3, (MSR_IR | MSR_DR) 434a47a12beSStefan Roese beqlr 435a47a12beSStefan Roese andc r3, r3, r0 436a47a12beSStefan Roese mtspr SRR0, r4 437a47a12beSStefan Roese mtspr SRR1, r3 438a47a12beSStefan Roese rfi 439a47a12beSStefan Roese 440a47a12beSStefan Roese/* 441a47a12beSStefan Roese * This code finishes saving the registers to the exception frame 442a47a12beSStefan Roese * and jumps to the appropriate handler for the exception. 443a47a12beSStefan Roese * Register r21 is pointer into trap frame, r1 has new stack pointer. 444a47a12beSStefan Roese */ 445a47a12beSStefan Roese .globl transfer_to_handler 446a47a12beSStefan Roesetransfer_to_handler: 447a47a12beSStefan Roese stw r22,_NIP(r21) 448a47a12beSStefan Roese lis r22,MSR_POW@h 449a47a12beSStefan Roese andc r23,r23,r22 450a47a12beSStefan Roese stw r23,_MSR(r21) 451a47a12beSStefan Roese SAVE_GPR(7, r21) 452a47a12beSStefan Roese SAVE_4GPRS(8, r21) 453a47a12beSStefan Roese SAVE_8GPRS(12, r21) 454a47a12beSStefan Roese SAVE_8GPRS(24, r21) 455a47a12beSStefan Roese mflr r23 456a47a12beSStefan Roese andi. r24,r23,0x3f00 /* get vector offset */ 457a47a12beSStefan Roese stw r24,TRAP(r21) 458a47a12beSStefan Roese li r22,0 459a47a12beSStefan Roese stw r22,RESULT(r21) 460a47a12beSStefan Roese mtspr SPRG2,r22 /* r1 is now kernel sp */ 461a47a12beSStefan Roese lwz r24,0(r23) /* virtual address of handler */ 462a47a12beSStefan Roese lwz r23,4(r23) /* where to go when done */ 463a47a12beSStefan Roese mtspr SRR0,r24 464a47a12beSStefan Roese mtspr SRR1,r20 465a47a12beSStefan Roese mtlr r23 466a47a12beSStefan Roese SYNC 467a47a12beSStefan Roese rfi /* jump to handler, enable MMU */ 468a47a12beSStefan Roese 469a47a12beSStefan Roeseint_return: 470a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 471a47a12beSStefan Roese li r4,0 472a47a12beSStefan Roese ori r4,r4,MSR_EE 473a47a12beSStefan Roese andc r28,r28,r4 474a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 475a47a12beSStefan Roese mtmsr r28 476a47a12beSStefan Roese SYNC 477a47a12beSStefan Roese lwz r2,_CTR(r1) 478a47a12beSStefan Roese lwz r0,_LINK(r1) 479a47a12beSStefan Roese mtctr r2 480a47a12beSStefan Roese mtlr r0 481a47a12beSStefan Roese lwz r2,_XER(r1) 482a47a12beSStefan Roese lwz r0,_CCR(r1) 483a47a12beSStefan Roese mtspr XER,r2 484a47a12beSStefan Roese mtcrf 0xFF,r0 485a47a12beSStefan Roese REST_10GPRS(3, r1) 486a47a12beSStefan Roese REST_10GPRS(13, r1) 487a47a12beSStefan Roese REST_8GPRS(23, r1) 488a47a12beSStefan Roese REST_GPR(31, r1) 489a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 490a47a12beSStefan Roese lwz r0,_MSR(r1) 491a47a12beSStefan Roese mtspr SRR0,r2 492a47a12beSStefan Roese mtspr SRR1,r0 493a47a12beSStefan Roese lwz r0,GPR0(r1) 494a47a12beSStefan Roese lwz r2,GPR2(r1) 495a47a12beSStefan Roese lwz r1,GPR1(r1) 496a47a12beSStefan Roese SYNC 497a47a12beSStefan Roese rfi 498a47a12beSStefan Roese 499a47a12beSStefan Roese .globl dc_read 500a47a12beSStefan Roesedc_read: 501a47a12beSStefan Roese blr 502a47a12beSStefan Roese 503a47a12beSStefan Roese .globl get_pvr 504a47a12beSStefan Roeseget_pvr: 505a47a12beSStefan Roese mfspr r3, PVR 506a47a12beSStefan Roese blr 507a47a12beSStefan Roese 508a47a12beSStefan Roese .globl get_svr 509a47a12beSStefan Roeseget_svr: 510a47a12beSStefan Roese mfspr r3, SVR 511a47a12beSStefan Roese blr 512a47a12beSStefan Roese 513a47a12beSStefan Roese 514a47a12beSStefan Roese/* 515a47a12beSStefan Roese * Function: in8 516a47a12beSStefan Roese * Description: Input 8 bits 517a47a12beSStefan Roese */ 518a47a12beSStefan Roese .globl in8 519a47a12beSStefan Roesein8: 520a47a12beSStefan Roese lbz r3,0x0000(r3) 521a47a12beSStefan Roese blr 522a47a12beSStefan Roese 523a47a12beSStefan Roese/* 524a47a12beSStefan Roese * Function: out8 525a47a12beSStefan Roese * Description: Output 8 bits 526a47a12beSStefan Roese */ 527a47a12beSStefan Roese .globl out8 528a47a12beSStefan Roeseout8: 529a47a12beSStefan Roese stb r4,0x0000(r3) 530a47a12beSStefan Roese blr 531a47a12beSStefan Roese 532a47a12beSStefan Roese/* 533a47a12beSStefan Roese * Function: out16 534a47a12beSStefan Roese * Description: Output 16 bits 535a47a12beSStefan Roese */ 536a47a12beSStefan Roese .globl out16 537a47a12beSStefan Roeseout16: 538a47a12beSStefan Roese sth r4,0x0000(r3) 539a47a12beSStefan Roese blr 540a47a12beSStefan Roese 541a47a12beSStefan Roese/* 542a47a12beSStefan Roese * Function: out16r 543a47a12beSStefan Roese * Description: Byte reverse and output 16 bits 544a47a12beSStefan Roese */ 545a47a12beSStefan Roese .globl out16r 546a47a12beSStefan Roeseout16r: 547a47a12beSStefan Roese sthbrx r4,r0,r3 548a47a12beSStefan Roese blr 549a47a12beSStefan Roese 550a47a12beSStefan Roese/* 551a47a12beSStefan Roese * Function: out32 552a47a12beSStefan Roese * Description: Output 32 bits 553a47a12beSStefan Roese */ 554a47a12beSStefan Roese .globl out32 555a47a12beSStefan Roeseout32: 556a47a12beSStefan Roese stw r4,0x0000(r3) 557a47a12beSStefan Roese blr 558a47a12beSStefan Roese 559a47a12beSStefan Roese/* 560a47a12beSStefan Roese * Function: out32r 561a47a12beSStefan Roese * Description: Byte reverse and output 32 bits 562a47a12beSStefan Roese */ 563a47a12beSStefan Roese .globl out32r 564a47a12beSStefan Roeseout32r: 565a47a12beSStefan Roese stwbrx r4,r0,r3 566a47a12beSStefan Roese blr 567a47a12beSStefan Roese 568a47a12beSStefan Roese/* 569a47a12beSStefan Roese * Function: in16 570a47a12beSStefan Roese * Description: Input 16 bits 571a47a12beSStefan Roese */ 572a47a12beSStefan Roese .globl in16 573a47a12beSStefan Roesein16: 574a47a12beSStefan Roese lhz r3,0x0000(r3) 575a47a12beSStefan Roese blr 576a47a12beSStefan Roese 577a47a12beSStefan Roese/* 578a47a12beSStefan Roese * Function: in16r 579a47a12beSStefan Roese * Description: Input 16 bits and byte reverse 580a47a12beSStefan Roese */ 581a47a12beSStefan Roese .globl in16r 582a47a12beSStefan Roesein16r: 583a47a12beSStefan Roese lhbrx r3,r0,r3 584a47a12beSStefan Roese blr 585a47a12beSStefan Roese 586a47a12beSStefan Roese/* 587a47a12beSStefan Roese * Function: in32 588a47a12beSStefan Roese * Description: Input 32 bits 589a47a12beSStefan Roese */ 590a47a12beSStefan Roese .globl in32 591a47a12beSStefan Roesein32: 592a47a12beSStefan Roese lwz 3,0x0000(3) 593a47a12beSStefan Roese blr 594a47a12beSStefan Roese 595a47a12beSStefan Roese/* 596a47a12beSStefan Roese * Function: in32r 597a47a12beSStefan Roese * Description: Input 32 bits and byte reverse 598a47a12beSStefan Roese */ 599a47a12beSStefan Roese .globl in32r 600a47a12beSStefan Roesein32r: 601a47a12beSStefan Roese lwbrx r3,r0,r3 602a47a12beSStefan Roese blr 603a47a12beSStefan Roese 604a47a12beSStefan Roese/* 605a47a12beSStefan Roese * void relocate_code (addr_sp, gd, addr_moni) 606a47a12beSStefan Roese * 607a47a12beSStefan Roese * This "function" does not return, instead it continues in RAM 608a47a12beSStefan Roese * after relocating the monitor code. 609a47a12beSStefan Roese * 610a47a12beSStefan Roese * r3 = dest 611a47a12beSStefan Roese * r4 = src 612a47a12beSStefan Roese * r5 = length in bytes 613a47a12beSStefan Roese * r6 = cachelinesize 614a47a12beSStefan Roese */ 615a47a12beSStefan Roese .globl relocate_code 616a47a12beSStefan Roeserelocate_code: 617a47a12beSStefan Roese 618a47a12beSStefan Roese mr r1, r3 /* Set new stack pointer */ 619a47a12beSStefan Roese mr r9, r4 /* Save copy of Global Data pointer */ 620a47a12beSStefan Roese mr r10, r5 /* Save copy of Destination Address */ 621a47a12beSStefan Roese 622a47a12beSStefan Roese GET_GOT 623a47a12beSStefan Roese mr r3, r5 /* Destination Address */ 624a47a12beSStefan Roese lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 625a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 626a47a12beSStefan Roese lwz r5, GOT(__init_end) 627a47a12beSStefan Roese sub r5, r5, r4 628a47a12beSStefan Roese li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 629a47a12beSStefan Roese 630a47a12beSStefan Roese /* 631a47a12beSStefan Roese * Fix GOT pointer: 632a47a12beSStefan Roese * 633a47a12beSStefan Roese * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 634a47a12beSStefan Roese * 635a47a12beSStefan Roese * Offset: 636a47a12beSStefan Roese */ 637a47a12beSStefan Roese sub r15, r10, r4 638a47a12beSStefan Roese 639a47a12beSStefan Roese /* First our own GOT */ 640a47a12beSStefan Roese add r12, r12, r15 641a47a12beSStefan Roese /* then the one used by the C code */ 642a47a12beSStefan Roese add r30, r30, r15 643a47a12beSStefan Roese 644a47a12beSStefan Roese /* 645a47a12beSStefan Roese * Now relocate code 646a47a12beSStefan Roese */ 647a47a12beSStefan Roese cmplw cr1,r3,r4 648a47a12beSStefan Roese addi r0,r5,3 649a47a12beSStefan Roese srwi. r0,r0,2 650a47a12beSStefan Roese beq cr1,4f /* In place copy is not necessary */ 651a47a12beSStefan Roese beq 7f /* Protect against 0 count */ 652a47a12beSStefan Roese mtctr r0 653a47a12beSStefan Roese bge cr1,2f 654a47a12beSStefan Roese 655a47a12beSStefan Roese la r8,-4(r4) 656a47a12beSStefan Roese la r7,-4(r3) 657a47a12beSStefan Roese1: lwzu r0,4(r8) 658a47a12beSStefan Roese stwu r0,4(r7) 659a47a12beSStefan Roese bdnz 1b 660a47a12beSStefan Roese b 4f 661a47a12beSStefan Roese 662a47a12beSStefan Roese2: slwi r0,r0,2 663a47a12beSStefan Roese add r8,r4,r0 664a47a12beSStefan Roese add r7,r3,r0 665a47a12beSStefan Roese3: lwzu r0,-4(r8) 666a47a12beSStefan Roese stwu r0,-4(r7) 667a47a12beSStefan Roese bdnz 3b 668a47a12beSStefan Roese/* 669a47a12beSStefan Roese * Now flush the cache: note that we must start from a cache aligned 670a47a12beSStefan Roese * address. Otherwise we might miss one cache line. 671a47a12beSStefan Roese */ 672a47a12beSStefan Roese4: cmpwi r6,0 673a47a12beSStefan Roese add r5,r3,r5 674a47a12beSStefan Roese beq 7f /* Always flush prefetch queue in any case */ 675a47a12beSStefan Roese subi r0,r6,1 676a47a12beSStefan Roese andc r3,r3,r0 677a47a12beSStefan Roese mr r4,r3 678a47a12beSStefan Roese5: dcbst 0,r4 679a47a12beSStefan Roese add r4,r4,r6 680a47a12beSStefan Roese cmplw r4,r5 681a47a12beSStefan Roese blt 5b 682a47a12beSStefan Roese sync /* Wait for all dcbst to complete on bus */ 683a47a12beSStefan Roese mr r4,r3 684a47a12beSStefan Roese6: icbi 0,r4 685a47a12beSStefan Roese add r4,r4,r6 686a47a12beSStefan Roese cmplw r4,r5 687a47a12beSStefan Roese blt 6b 688a47a12beSStefan Roese7: sync /* Wait for all icbi to complete on bus */ 689a47a12beSStefan Roese isync 690a47a12beSStefan Roese 691a47a12beSStefan Roese/* 692a47a12beSStefan Roese * We are done. Do not return, instead branch to second part of board 693a47a12beSStefan Roese * initialization, now running from RAM. 694a47a12beSStefan Roese */ 695a47a12beSStefan Roese addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 696a47a12beSStefan Roese mtlr r0 697a47a12beSStefan Roese blr 698a47a12beSStefan Roese 699a47a12beSStefan Roesein_ram: 700a47a12beSStefan Roese /* 701a47a12beSStefan Roese * Relocation Function, r12 point to got2+0x8000 702a47a12beSStefan Roese * 703a47a12beSStefan Roese * Adjust got2 pointers, no need to check for 0, this code 704a47a12beSStefan Roese * already puts a few entries in the table. 705a47a12beSStefan Roese */ 706a47a12beSStefan Roese li r0,__got2_entries@sectoff@l 707a47a12beSStefan Roese la r3,GOT(_GOT2_TABLE_) 708a47a12beSStefan Roese lwz r11,GOT(_GOT2_TABLE_) 709a47a12beSStefan Roese mtctr r0 710a47a12beSStefan Roese sub r11,r3,r11 711a47a12beSStefan Roese addi r3,r3,-4 712a47a12beSStefan Roese1: lwzu r0,4(r3) 713a47a12beSStefan Roese cmpwi r0,0 714a47a12beSStefan Roese beq- 2f 715a47a12beSStefan Roese add r0,r0,r11 716a47a12beSStefan Roese stw r0,0(r3) 717a47a12beSStefan Roese2: bdnz 1b 718a47a12beSStefan Roese 719a47a12beSStefan Roese /* 720a47a12beSStefan Roese * Now adjust the fixups and the pointers to the fixups 721a47a12beSStefan Roese * in case we need to move ourselves again. 722a47a12beSStefan Roese */ 723a47a12beSStefan Roese li r0,__fixup_entries@sectoff@l 724a47a12beSStefan Roese lwz r3,GOT(_FIXUP_TABLE_) 725a47a12beSStefan Roese cmpwi r0,0 726a47a12beSStefan Roese mtctr r0 727a47a12beSStefan Roese addi r3,r3,-4 728a47a12beSStefan Roese beq 4f 729a47a12beSStefan Roese3: lwzu r4,4(r3) 730a47a12beSStefan Roese lwzux r0,r4,r11 731d1e0b10aSJoakim Tjernlund cmpwi r0,0 732a47a12beSStefan Roese add r0,r0,r11 733a47a12beSStefan Roese stw r10,0(r3) 734d1e0b10aSJoakim Tjernlund beq- 5f 735a47a12beSStefan Roese stw r0,0(r4) 736d1e0b10aSJoakim Tjernlund5: bdnz 3b 737a47a12beSStefan Roese4: 738a47a12beSStefan Roese/* clear_bss: */ 739a47a12beSStefan Roese /* 740a47a12beSStefan Roese * Now clear BSS segment 741a47a12beSStefan Roese */ 742a47a12beSStefan Roese lwz r3,GOT(__bss_start) 743a47a12beSStefan Roese lwz r4,GOT(_end) 744a47a12beSStefan Roese 745a47a12beSStefan Roese cmplw 0, r3, r4 746a47a12beSStefan Roese beq 6f 747a47a12beSStefan Roese 748a47a12beSStefan Roese li r0, 0 749a47a12beSStefan Roese5: 750a47a12beSStefan Roese stw r0, 0(r3) 751a47a12beSStefan Roese addi r3, r3, 4 752a47a12beSStefan Roese cmplw 0, r3, r4 753a47a12beSStefan Roese bne 5b 754a47a12beSStefan Roese6: 755a47a12beSStefan Roese mr r3, r9 /* Init Date pointer */ 756a47a12beSStefan Roese mr r4, r10 /* Destination Address */ 757a47a12beSStefan Roese bl board_init_r 758a47a12beSStefan Roese 759a47a12beSStefan Roese /* not reached - end relocate_code */ 760a47a12beSStefan Roese/*-----------------------------------------------------------------------*/ 761a47a12beSStefan Roese 762a47a12beSStefan Roese /* 763a47a12beSStefan Roese * Copy exception vector code to low memory 764a47a12beSStefan Roese * 765a47a12beSStefan Roese * r3: dest_addr 766a47a12beSStefan Roese * r7: source address, r8: end address, r9: target address 767a47a12beSStefan Roese */ 768a47a12beSStefan Roese .globl trap_init 769a47a12beSStefan Roesetrap_init: 770a47a12beSStefan Roese mflr r4 /* save link register */ 771a47a12beSStefan Roese GET_GOT 772a47a12beSStefan Roese lwz r7, GOT(_start) 773a47a12beSStefan Roese lwz r8, GOT(_end_of_vectors) 774a47a12beSStefan Roese 775a47a12beSStefan Roese li r9, 0x100 /* reset vector always at 0x100 */ 776a47a12beSStefan Roese 777a47a12beSStefan Roese cmplw 0, r7, r8 778a47a12beSStefan Roese bgelr /* return if r7>=r8 - just in case */ 779a47a12beSStefan Roese1: 780a47a12beSStefan Roese lwz r0, 0(r7) 781a47a12beSStefan Roese stw r0, 0(r9) 782a47a12beSStefan Roese addi r7, r7, 4 783a47a12beSStefan Roese addi r9, r9, 4 784a47a12beSStefan Roese cmplw 0, r7, r8 785a47a12beSStefan Roese bne 1b 786a47a12beSStefan Roese 787a47a12beSStefan Roese /* 788a47a12beSStefan Roese * relocate `hdlr' and `int_return' entries 789a47a12beSStefan Roese */ 790a47a12beSStefan Roese li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 791a47a12beSStefan Roese li r8, Alignment - _start + EXC_OFF_SYS_RESET 792a47a12beSStefan Roese2: 793a47a12beSStefan Roese bl trap_reloc 794a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 795a47a12beSStefan Roese cmplw 0, r7, r8 796a47a12beSStefan Roese blt 2b 797a47a12beSStefan Roese 798a47a12beSStefan Roese li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 799a47a12beSStefan Roese bl trap_reloc 800a47a12beSStefan Roese 801a47a12beSStefan Roese li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 802a47a12beSStefan Roese bl trap_reloc 803a47a12beSStefan Roese 804a47a12beSStefan Roese li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 805a47a12beSStefan Roese li r8, SystemCall - _start + EXC_OFF_SYS_RESET 806a47a12beSStefan Roese3: 807a47a12beSStefan Roese bl trap_reloc 808a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 809a47a12beSStefan Roese cmplw 0, r7, r8 810a47a12beSStefan Roese blt 3b 811a47a12beSStefan Roese 812a47a12beSStefan Roese li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 813a47a12beSStefan Roese li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 814a47a12beSStefan Roese4: 815a47a12beSStefan Roese bl trap_reloc 816a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 817a47a12beSStefan Roese cmplw 0, r7, r8 818a47a12beSStefan Roese blt 4b 819a47a12beSStefan Roese 820a47a12beSStefan Roese /* enable execptions from RAM vectors */ 821a47a12beSStefan Roese mfmsr r7 822a47a12beSStefan Roese li r8,MSR_IP 823a47a12beSStefan Roese andc r7,r7,r8 824a47a12beSStefan Roese ori r7,r7,MSR_ME /* Enable Machine Check */ 825a47a12beSStefan Roese mtmsr r7 826a47a12beSStefan Roese 827a47a12beSStefan Roese mtlr r4 /* restore link register */ 828a47a12beSStefan Roese blr 829a47a12beSStefan Roese 830a47a12beSStefan Roese.globl enable_ext_addr 831a47a12beSStefan Roeseenable_ext_addr: 832a47a12beSStefan Roese mfspr r0, HID0 833a47a12beSStefan Roese lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h 834a47a12beSStefan Roese ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l 835a47a12beSStefan Roese mtspr HID0, r0 836a47a12beSStefan Roese sync 837a47a12beSStefan Roese isync 838a47a12beSStefan Roese blr 839a47a12beSStefan Roese 840a47a12beSStefan Roese#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 841a47a12beSStefan Roese.globl setup_ccsrbar 842a47a12beSStefan Roesesetup_ccsrbar: 843a47a12beSStefan Roese /* Special sequence needed to update CCSRBAR itself */ 844a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h 845a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l 846a47a12beSStefan Roese 847a47a12beSStefan Roese lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 848a47a12beSStefan Roese ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 849a47a12beSStefan Roese srwi r5,r5,12 850a47a12beSStefan Roese li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 851a47a12beSStefan Roese rlwimi r5,r6,20,8,11 852a47a12beSStefan Roese stw r5, 0(r4) /* Store physical value of CCSR */ 853a47a12beSStefan Roese isync 854a47a12beSStefan Roese 85514d0a02aSWolfgang Denk lis r5, CONFIG_SYS_TEXT_BASE@h 85614d0a02aSWolfgang Denk ori r5,r5,CONFIG_SYS_TEXT_BASE@l 857a47a12beSStefan Roese lwz r5, 0(r5) 858a47a12beSStefan Roese isync 859a47a12beSStefan Roese 860a47a12beSStefan Roese /* Use VA of CCSR to do read */ 861a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSRBAR@h 862a47a12beSStefan Roese lwz r5, CONFIG_SYS_CCSRBAR@l(r3) 863a47a12beSStefan Roese isync 864a47a12beSStefan Roese 865a47a12beSStefan Roese blr 866a47a12beSStefan Roese#endif 867a47a12beSStefan Roese 868a47a12beSStefan Roese#ifdef CONFIG_SYS_INIT_RAM_LOCK 869a47a12beSStefan Roeselock_ram_in_cache: 870a47a12beSStefan Roese /* Allocate Initial RAM in data cache. 871a47a12beSStefan Roese */ 872a47a12beSStefan Roese lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 873a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 874553f0982SWolfgang Denk li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 875a47a12beSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 876a47a12beSStefan Roese mtctr r4 877a47a12beSStefan Roese1: 878a47a12beSStefan Roese dcbz r0, r3 879a47a12beSStefan Roese addi r3, r3, 32 880a47a12beSStefan Roese bdnz 1b 881a47a12beSStefan Roese#if 1 882a47a12beSStefan Roese/* Lock the data cache */ 883a47a12beSStefan Roese mfspr r0, HID0 884a47a12beSStefan Roese ori r0, r0, 0x1000 885a47a12beSStefan Roese sync 886a47a12beSStefan Roese mtspr HID0, r0 887a47a12beSStefan Roese sync 888a47a12beSStefan Roese blr 889a47a12beSStefan Roese#endif 890a47a12beSStefan Roese#if 0 891a47a12beSStefan Roese /* Lock the first way of the data cache */ 892a47a12beSStefan Roese mfspr r0, LDSTCR 893a47a12beSStefan Roese ori r0, r0, 0x0080 894a47a12beSStefan Roese#if defined(CONFIG_ALTIVEC) 895a47a12beSStefan Roese dssall 896a47a12beSStefan Roese#endif 897a47a12beSStefan Roese sync 898a47a12beSStefan Roese mtspr LDSTCR, r0 899a47a12beSStefan Roese sync 900a47a12beSStefan Roese isync 901a47a12beSStefan Roese blr 902a47a12beSStefan Roese#endif 903a47a12beSStefan Roese 904a47a12beSStefan Roese.globl unlock_ram_in_cache 905a47a12beSStefan Roeseunlock_ram_in_cache: 906a47a12beSStefan Roese /* invalidate the INIT_RAM section */ 907a47a12beSStefan Roese lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 908a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 909553f0982SWolfgang Denk li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 910a47a12beSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 911a47a12beSStefan Roese mtctr r4 912a47a12beSStefan Roese1: icbi r0, r3 913a47a12beSStefan Roese addi r3, r3, 32 914a47a12beSStefan Roese bdnz 1b 915a47a12beSStefan Roese sync /* Wait for all icbi to complete on bus */ 916a47a12beSStefan Roese isync 917a47a12beSStefan Roese#if 1 918a47a12beSStefan Roese/* Unlock the data cache and invalidate it */ 919a47a12beSStefan Roese mfspr r0, HID0 920a47a12beSStefan Roese li r3,0x1000 921a47a12beSStefan Roese andc r0,r0,r3 922a47a12beSStefan Roese li r3,0x0400 923a47a12beSStefan Roese or r0,r0,r3 924a47a12beSStefan Roese sync 925a47a12beSStefan Roese mtspr HID0, r0 926a47a12beSStefan Roese sync 927a47a12beSStefan Roese blr 928a47a12beSStefan Roese#endif 929a47a12beSStefan Roese#if 0 930a47a12beSStefan Roese /* Unlock the first way of the data cache */ 931a47a12beSStefan Roese mfspr r0, LDSTCR 932a47a12beSStefan Roese li r3,0x0080 933a47a12beSStefan Roese andc r0,r0,r3 934a47a12beSStefan Roese#ifdef CONFIG_ALTIVEC 935a47a12beSStefan Roese dssall 936a47a12beSStefan Roese#endif 937a47a12beSStefan Roese sync 938a47a12beSStefan Roese mtspr LDSTCR, r0 939a47a12beSStefan Roese sync 940a47a12beSStefan Roese isync 941a47a12beSStefan Roese li r3,0x0400 942a47a12beSStefan Roese or r0,r0,r3 943a47a12beSStefan Roese sync 944a47a12beSStefan Roese mtspr HID0, r0 945a47a12beSStefan Roese sync 946a47a12beSStefan Roese blr 947a47a12beSStefan Roese#endif 948a47a12beSStefan Roese#endif 949