1a47a12beSStefan Roese/* 2a47a12beSStefan Roese * Copyright 2004, 2007 Freescale Semiconductor. 3a47a12beSStefan Roese * Srikanth Srinivasan <srikanth.srinivaan@freescale.com> 4a47a12beSStefan Roese * 5a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6a47a12beSStefan Roese * project. 7a47a12beSStefan Roese * 8a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11a47a12beSStefan Roese * the License, or (at your option) any later version. 12a47a12beSStefan Roese * 13a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16a47a12beSStefan Roese * GNU General Public License for more details. 17a47a12beSStefan Roese * 18a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21a47a12beSStefan Roese * MA 02111-1307 USA 22a47a12beSStefan Roese */ 23a47a12beSStefan Roese 24a47a12beSStefan Roese/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards 25a47a12beSStefan Roese * 26a47a12beSStefan Roese * 27a47a12beSStefan Roese * The processor starts at 0xfff00100 and the code is executed 28a47a12beSStefan Roese * from flash. The code is organized to be at an other address 29a47a12beSStefan Roese * in memory, but as long we don't jump around before relocating. 30a47a12beSStefan Roese * board_init lies at a quite high address and when the cpu has 31a47a12beSStefan Roese * jumped there, everything is ok. 32a47a12beSStefan Roese */ 33a47a12beSStefan Roese#include <config.h> 34a47a12beSStefan Roese#include <mpc86xx.h> 35a47a12beSStefan Roese#include <timestamp.h> 36a47a12beSStefan Roese#include <version.h> 37a47a12beSStefan Roese 38a47a12beSStefan Roese#include <ppc_asm.tmpl> 39a47a12beSStefan Roese#include <ppc_defs.h> 40a47a12beSStefan Roese 41a47a12beSStefan Roese#include <asm/cache.h> 42a47a12beSStefan Roese#include <asm/mmu.h> 43a47a12beSStefan Roese 44a47a12beSStefan Roese#ifndef CONFIG_IDENT_STRING 45a47a12beSStefan Roese#define CONFIG_IDENT_STRING "" 46a47a12beSStefan Roese#endif 47a47a12beSStefan Roese 48a47a12beSStefan Roese/* 49a47a12beSStefan Roese * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions 50a47a12beSStefan Roese */ 51a47a12beSStefan Roese 52a47a12beSStefan Roese/* 53a47a12beSStefan Roese * Set up GOT: Global Offset Table 54a47a12beSStefan Roese * 55a47a12beSStefan Roese * Use r12 to access the GOT 56a47a12beSStefan Roese */ 57a47a12beSStefan Roese START_GOT 58a47a12beSStefan Roese GOT_ENTRY(_GOT2_TABLE_) 59a47a12beSStefan Roese GOT_ENTRY(_FIXUP_TABLE_) 60a47a12beSStefan Roese 61a47a12beSStefan Roese GOT_ENTRY(_start) 62a47a12beSStefan Roese GOT_ENTRY(_start_of_vectors) 63a47a12beSStefan Roese GOT_ENTRY(_end_of_vectors) 64a47a12beSStefan Roese GOT_ENTRY(transfer_to_handler) 65a47a12beSStefan Roese 66a47a12beSStefan Roese GOT_ENTRY(__init_end) 67a47a12beSStefan Roese GOT_ENTRY(_end) 68a47a12beSStefan Roese GOT_ENTRY(__bss_start) 69a47a12beSStefan Roese END_GOT 70a47a12beSStefan Roese 71a47a12beSStefan Roese/* 72a47a12beSStefan Roese * r3 - 1st arg to board_init(): IMMP pointer 73a47a12beSStefan Roese * r4 - 2nd arg to board_init(): boot flag 74a47a12beSStefan Roese */ 75a47a12beSStefan Roese .text 76a47a12beSStefan Roese .long 0x27051956 /* U-Boot Magic Number */ 77a47a12beSStefan Roese .globl version_string 78a47a12beSStefan Roeseversion_string: 79a47a12beSStefan Roese .ascii U_BOOT_VERSION 80a47a12beSStefan Roese .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" 81a47a12beSStefan Roese .ascii CONFIG_IDENT_STRING, "\0" 82a47a12beSStefan Roese 83a47a12beSStefan Roese . = EXC_OFF_SYS_RESET 84a47a12beSStefan Roese .globl _start 85a47a12beSStefan Roese_start: 86a47a12beSStefan Roese b boot_cold 87a47a12beSStefan Roese 88a47a12beSStefan Roese /* the boot code is located below the exception table */ 89a47a12beSStefan Roese 90a47a12beSStefan Roese .globl _start_of_vectors 91a47a12beSStefan Roese_start_of_vectors: 92a47a12beSStefan Roese 93a47a12beSStefan Roese/* Machine check */ 94a47a12beSStefan Roese STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 95a47a12beSStefan Roese 96a47a12beSStefan Roese/* Data Storage exception. */ 97a47a12beSStefan Roese STD_EXCEPTION(0x300, DataStorage, UnknownException) 98a47a12beSStefan Roese 99a47a12beSStefan Roese/* Instruction Storage exception. */ 100a47a12beSStefan Roese STD_EXCEPTION(0x400, InstStorage, UnknownException) 101a47a12beSStefan Roese 102a47a12beSStefan Roese/* External Interrupt exception. */ 103a47a12beSStefan Roese STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 104a47a12beSStefan Roese 105a47a12beSStefan Roese/* Alignment exception. */ 106a47a12beSStefan Roese . = 0x600 107a47a12beSStefan RoeseAlignment: 108a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 109a47a12beSStefan Roese mfspr r4,DAR 110a47a12beSStefan Roese stw r4,_DAR(r21) 111a47a12beSStefan Roese mfspr r5,DSISR 112a47a12beSStefan Roese stw r5,_DSISR(r21) 113a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 114a47a12beSStefan Roese EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 115a47a12beSStefan Roese 116a47a12beSStefan Roese/* Program check exception */ 117a47a12beSStefan Roese . = 0x700 118a47a12beSStefan RoeseProgramCheck: 119a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 120a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 121a47a12beSStefan Roese EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 122a47a12beSStefan Roese MSR_KERNEL, COPY_EE) 123a47a12beSStefan Roese 124a47a12beSStefan Roese STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 125a47a12beSStefan Roese 126a47a12beSStefan Roese /* I guess we could implement decrementer, and may have 127a47a12beSStefan Roese * to someday for timekeeping. 128a47a12beSStefan Roese */ 129a47a12beSStefan Roese STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 130a47a12beSStefan Roese STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 131a47a12beSStefan Roese STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 132a47a12beSStefan Roese STD_EXCEPTION(0xc00, SystemCall, UnknownException) 133a47a12beSStefan Roese STD_EXCEPTION(0xd00, SingleStep, UnknownException) 134a47a12beSStefan Roese STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 135a47a12beSStefan Roese STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 136a47a12beSStefan Roese STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) 137a47a12beSStefan Roese STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) 138a47a12beSStefan Roese STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) 139a47a12beSStefan Roese STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) 140a47a12beSStefan Roese STD_EXCEPTION(0x1400, DataTLBError, UnknownException) 141a47a12beSStefan Roese STD_EXCEPTION(0x1500, Reserved5, UnknownException) 142a47a12beSStefan Roese STD_EXCEPTION(0x1600, Reserved6, UnknownException) 143a47a12beSStefan Roese STD_EXCEPTION(0x1700, Reserved7, UnknownException) 144a47a12beSStefan Roese STD_EXCEPTION(0x1800, Reserved8, UnknownException) 145a47a12beSStefan Roese STD_EXCEPTION(0x1900, Reserved9, UnknownException) 146a47a12beSStefan Roese STD_EXCEPTION(0x1a00, ReservedA, UnknownException) 147a47a12beSStefan Roese STD_EXCEPTION(0x1b00, ReservedB, UnknownException) 148a47a12beSStefan Roese STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) 149a47a12beSStefan Roese STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) 150a47a12beSStefan Roese STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) 151a47a12beSStefan Roese STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) 152a47a12beSStefan Roese 153a47a12beSStefan Roese .globl _end_of_vectors 154a47a12beSStefan Roese_end_of_vectors: 155a47a12beSStefan Roese 156a47a12beSStefan Roese . = 0x2000 157a47a12beSStefan Roese 158a47a12beSStefan Roeseboot_cold: 159a47a12beSStefan Roese /* 160a47a12beSStefan Roese * NOTE: Only Cpu 0 will ever come here. Other cores go to an 161a47a12beSStefan Roese * address specified by the BPTR 162a47a12beSStefan Roese */ 163a47a12beSStefan Roese1: 164a47a12beSStefan Roese#ifdef CONFIG_SYS_RAMBOOT 165a47a12beSStefan Roese /* disable everything */ 166a47a12beSStefan Roese li r0, 0 167a47a12beSStefan Roese mtspr HID0, r0 168a47a12beSStefan Roese sync 169a47a12beSStefan Roese mtmsr 0 170a47a12beSStefan Roese#endif 171a47a12beSStefan Roese 172a47a12beSStefan Roese /* Invalidate BATs */ 173a47a12beSStefan Roese bl invalidate_bats 174a47a12beSStefan Roese sync 175a47a12beSStefan Roese /* Invalidate all of TLB before MMU turn on */ 176a47a12beSStefan Roese bl clear_tlbs 177a47a12beSStefan Roese sync 178a47a12beSStefan Roese 179a47a12beSStefan Roese#ifdef CONFIG_SYS_L2 180a47a12beSStefan Roese /* init the L2 cache */ 181a47a12beSStefan Roese lis r3, L2_INIT@h 182a47a12beSStefan Roese ori r3, r3, L2_INIT@l 183a47a12beSStefan Roese mtspr l2cr, r3 184a47a12beSStefan Roese /* invalidate the L2 cache */ 185a47a12beSStefan Roese bl l2cache_invalidate 186a47a12beSStefan Roese sync 187a47a12beSStefan Roese#endif 188a47a12beSStefan Roese 189a47a12beSStefan Roese /* 190a47a12beSStefan Roese * Calculate absolute address in FLASH and jump there 191a47a12beSStefan Roese *------------------------------------------------------*/ 192a47a12beSStefan Roese lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h 193a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l 194a47a12beSStefan Roese addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET 195a47a12beSStefan Roese mtlr r3 196a47a12beSStefan Roese blr 197a47a12beSStefan Roese 198a47a12beSStefan Roesein_flash: 199a47a12beSStefan Roese /* let the C-code set up the rest */ 200a47a12beSStefan Roese /* */ 201a47a12beSStefan Roese /* Be careful to keep code relocatable ! */ 202a47a12beSStefan Roese /*------------------------------------------------------*/ 203a47a12beSStefan Roese /* perform low-level init */ 204a47a12beSStefan Roese 205a47a12beSStefan Roese /* enable extended addressing */ 206a47a12beSStefan Roese bl enable_ext_addr 207a47a12beSStefan Roese 208a47a12beSStefan Roese /* setup the bats */ 209a47a12beSStefan Roese bl early_bats 210a47a12beSStefan Roese 211a47a12beSStefan Roese /* 212a47a12beSStefan Roese * Cache must be enabled here for stack-in-cache trick. 213a47a12beSStefan Roese * This means we need to enable the BATS. 214a47a12beSStefan Roese * Cache should be turned on after BATs, since by default 215a47a12beSStefan Roese * everything is write-through. 216a47a12beSStefan Roese */ 217a47a12beSStefan Roese 218a47a12beSStefan Roese /* enable address translation */ 219a47a12beSStefan Roese mfmsr r5 220a47a12beSStefan Roese ori r5, r5, (MSR_IR | MSR_DR) 221a47a12beSStefan Roese lis r3,addr_trans_enabled@h 222a47a12beSStefan Roese ori r3, r3, addr_trans_enabled@l 223a47a12beSStefan Roese mtspr SPRN_SRR0,r3 224a47a12beSStefan Roese mtspr SPRN_SRR1,r5 225a47a12beSStefan Roese rfi 226a47a12beSStefan Roese 227a47a12beSStefan Roeseaddr_trans_enabled: 228a47a12beSStefan Roese /* enable and invalidate the data cache */ 229a47a12beSStefan Roese/* bl l1dcache_enable */ 230a47a12beSStefan Roese bl dcache_enable 231a47a12beSStefan Roese sync 232a47a12beSStefan Roese 233a47a12beSStefan Roese#if 1 234a47a12beSStefan Roese bl icache_enable 235a47a12beSStefan Roese#endif 236a47a12beSStefan Roese 237a47a12beSStefan Roese#ifdef CONFIG_SYS_INIT_RAM_LOCK 238a47a12beSStefan Roese bl lock_ram_in_cache 239a47a12beSStefan Roese sync 240a47a12beSStefan Roese#endif 241a47a12beSStefan Roese 242a47a12beSStefan Roese#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 243a47a12beSStefan Roese bl setup_ccsrbar 244a47a12beSStefan Roese#endif 245a47a12beSStefan Roese 246a47a12beSStefan Roese /* set up the stack pointer in our newly created 247a47a12beSStefan Roese * cache-ram (r1) */ 248a47a12beSStefan Roese lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 249a47a12beSStefan Roese ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 250a47a12beSStefan Roese 251a47a12beSStefan Roese li r0, 0 /* Make room for stack frame header and */ 252a47a12beSStefan Roese stwu r0, -4(r1) /* clear final stack frame so that */ 253a47a12beSStefan Roese stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 254a47a12beSStefan Roese 255a47a12beSStefan Roese GET_GOT /* initialize GOT access */ 256a47a12beSStefan Roese 257a47a12beSStefan Roese /* run low-level CPU init code (from Flash) */ 258a47a12beSStefan Roese bl cpu_init_f 259a47a12beSStefan Roese sync 260a47a12beSStefan Roese 261a47a12beSStefan Roese#ifdef RUN_DIAG 262a47a12beSStefan Roese 263a47a12beSStefan Roese /* Load PX_AUX register address in r4 */ 264a47a12beSStefan Roese lis r4, PIXIS_BASE@h 265a47a12beSStefan Roese ori r4, r4, 0x6 266a47a12beSStefan Roese /* Load contents of PX_AUX in r3 bits 24 to 31*/ 267a47a12beSStefan Roese lbz r3, 0(r4) 268a47a12beSStefan Roese 269a47a12beSStefan Roese /* Mask and obtain the bit in r3 */ 270a47a12beSStefan Roese rlwinm. r3, r3, 0, 24, 24 271a47a12beSStefan Roese /* If not zero, jump and continue with u-boot */ 272a47a12beSStefan Roese bne diag_done 273a47a12beSStefan Roese 274a47a12beSStefan Roese /* Load back contents of PX_AUX in r3 bits 24 to 31 */ 275a47a12beSStefan Roese lbz r3, 0(r4) 276a47a12beSStefan Roese /* Set the MSB of the register value */ 277a47a12beSStefan Roese ori r3, r3, 0x80 278a47a12beSStefan Roese /* Write value in r3 back to PX_AUX */ 279a47a12beSStefan Roese stb r3, 0(r4) 280a47a12beSStefan Roese 281a47a12beSStefan Roese /* Get the address to jump to in r3*/ 282a47a12beSStefan Roese lis r3, CONFIG_SYS_DIAG_ADDR@h 283a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DIAG_ADDR@l 284a47a12beSStefan Roese 285a47a12beSStefan Roese /* Load the LR with the branch address */ 286a47a12beSStefan Roese mtlr r3 287a47a12beSStefan Roese 288a47a12beSStefan Roese /* Branch to diagnostic */ 289a47a12beSStefan Roese blr 290a47a12beSStefan Roese 291a47a12beSStefan Roesediag_done: 292a47a12beSStefan Roese#endif 293a47a12beSStefan Roese 294a47a12beSStefan Roese/* bl l2cache_enable */ 295a47a12beSStefan Roese 296a47a12beSStefan Roese /* run 1st part of board init code (from Flash) */ 297a47a12beSStefan Roese bl board_init_f 298a47a12beSStefan Roese sync 299a47a12beSStefan Roese 30052ebd9c1SPeter Tyser /* NOTREACHED - board_init_f() does not return */ 301a47a12beSStefan Roese 302a47a12beSStefan Roese .globl invalidate_bats 303a47a12beSStefan Roeseinvalidate_bats: 304a47a12beSStefan Roese 305a47a12beSStefan Roese li r0, 0 306a47a12beSStefan Roese /* invalidate BATs */ 307a47a12beSStefan Roese mtspr IBAT0U, r0 308a47a12beSStefan Roese mtspr IBAT1U, r0 309a47a12beSStefan Roese mtspr IBAT2U, r0 310a47a12beSStefan Roese mtspr IBAT3U, r0 311a47a12beSStefan Roese mtspr IBAT4U, r0 312a47a12beSStefan Roese mtspr IBAT5U, r0 313a47a12beSStefan Roese mtspr IBAT6U, r0 314a47a12beSStefan Roese mtspr IBAT7U, r0 315a47a12beSStefan Roese 316a47a12beSStefan Roese isync 317a47a12beSStefan Roese mtspr DBAT0U, r0 318a47a12beSStefan Roese mtspr DBAT1U, r0 319a47a12beSStefan Roese mtspr DBAT2U, r0 320a47a12beSStefan Roese mtspr DBAT3U, r0 321a47a12beSStefan Roese mtspr DBAT4U, r0 322a47a12beSStefan Roese mtspr DBAT5U, r0 323a47a12beSStefan Roese mtspr DBAT6U, r0 324a47a12beSStefan Roese mtspr DBAT7U, r0 325a47a12beSStefan Roese 326a47a12beSStefan Roese isync 327a47a12beSStefan Roese sync 328a47a12beSStefan Roese blr 329a47a12beSStefan Roese 330a47a12beSStefan Roese/* 331a47a12beSStefan Roese * early_bats: 332a47a12beSStefan Roese * 333a47a12beSStefan Roese * Set up bats needed early on - this is usually the BAT for the 334a47a12beSStefan Roese * stack-in-cache, the Flash, and CCSR space 335a47a12beSStefan Roese */ 336a47a12beSStefan Roese .globl early_bats 337a47a12beSStefan Roeseearly_bats: 338a47a12beSStefan Roese /* IBAT 3 */ 339a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT3L@h 340a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT3L@l 341a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT3U@h 342a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT3U@l 343a47a12beSStefan Roese mtspr IBAT3L, r4 344a47a12beSStefan Roese mtspr IBAT3U, r3 345a47a12beSStefan Roese isync 346a47a12beSStefan Roese 347a47a12beSStefan Roese /* DBAT 3 */ 348a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT3L@h 349a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT3L@l 350a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT3U@h 351a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT3U@l 352a47a12beSStefan Roese mtspr DBAT3L, r4 353a47a12beSStefan Roese mtspr DBAT3U, r3 354a47a12beSStefan Roese isync 355a47a12beSStefan Roese 356a47a12beSStefan Roese /* IBAT 5 */ 357a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT5L@h 358a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT5L@l 359a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT5U@h 360a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT5U@l 361a47a12beSStefan Roese mtspr IBAT5L, r4 362a47a12beSStefan Roese mtspr IBAT5U, r3 363a47a12beSStefan Roese isync 364a47a12beSStefan Roese 365a47a12beSStefan Roese /* DBAT 5 */ 366a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT5L@h 367a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT5L@l 368a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT5U@h 369a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT5U@l 370a47a12beSStefan Roese mtspr DBAT5L, r4 371a47a12beSStefan Roese mtspr DBAT5U, r3 372a47a12beSStefan Roese isync 373a47a12beSStefan Roese 374a47a12beSStefan Roese /* IBAT 6 */ 375a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT6L_EARLY@h 376a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l 377a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT6U_EARLY@h 378a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l 379a47a12beSStefan Roese mtspr IBAT6L, r4 380a47a12beSStefan Roese mtspr IBAT6U, r3 381a47a12beSStefan Roese isync 382a47a12beSStefan Roese 383a47a12beSStefan Roese /* DBAT 6 */ 384a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT6L_EARLY@h 385a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l 386a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT6U_EARLY@h 387a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l 388a47a12beSStefan Roese mtspr DBAT6L, r4 389a47a12beSStefan Roese mtspr DBAT6U, r3 390a47a12beSStefan Roese isync 391a47a12beSStefan Roese 392a47a12beSStefan Roese#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 393a47a12beSStefan Roese /* IBAT 7 */ 394a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h 395a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l 396a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h 397a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l 398a47a12beSStefan Roese mtspr IBAT7L, r4 399a47a12beSStefan Roese mtspr IBAT7U, r3 400a47a12beSStefan Roese isync 401a47a12beSStefan Roese 402a47a12beSStefan Roese /* DBAT 7 */ 403a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h 404a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l 405a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h 406a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l 407a47a12beSStefan Roese mtspr DBAT7L, r4 408a47a12beSStefan Roese mtspr DBAT7U, r3 409a47a12beSStefan Roese isync 410a47a12beSStefan Roese#endif 411a47a12beSStefan Roese blr 412a47a12beSStefan Roese 413a47a12beSStefan Roese .globl clear_tlbs 414a47a12beSStefan Roeseclear_tlbs: 415a47a12beSStefan Roese addis r3, 0, 0x0000 416a47a12beSStefan Roese addis r5, 0, 0x4 417a47a12beSStefan Roese isync 418a47a12beSStefan Roesetlblp: 419a47a12beSStefan Roese tlbie r3 420a47a12beSStefan Roese sync 421a47a12beSStefan Roese addi r3, r3, 0x1000 422a47a12beSStefan Roese cmp 0, 0, r3, r5 423a47a12beSStefan Roese blt tlblp 424a47a12beSStefan Roese blr 425a47a12beSStefan Roese 426a47a12beSStefan Roese .globl disable_addr_trans 427a47a12beSStefan Roesedisable_addr_trans: 428a47a12beSStefan Roese /* disable address translation */ 429a47a12beSStefan Roese mflr r4 430a47a12beSStefan Roese mfmsr r3 431a47a12beSStefan Roese andi. r0, r3, (MSR_IR | MSR_DR) 432a47a12beSStefan Roese beqlr 433a47a12beSStefan Roese andc r3, r3, r0 434a47a12beSStefan Roese mtspr SRR0, r4 435a47a12beSStefan Roese mtspr SRR1, r3 436a47a12beSStefan Roese rfi 437a47a12beSStefan Roese 438a47a12beSStefan Roese/* 439a47a12beSStefan Roese * This code finishes saving the registers to the exception frame 440a47a12beSStefan Roese * and jumps to the appropriate handler for the exception. 441a47a12beSStefan Roese * Register r21 is pointer into trap frame, r1 has new stack pointer. 442a47a12beSStefan Roese */ 443a47a12beSStefan Roese .globl transfer_to_handler 444a47a12beSStefan Roesetransfer_to_handler: 445a47a12beSStefan Roese stw r22,_NIP(r21) 446a47a12beSStefan Roese lis r22,MSR_POW@h 447a47a12beSStefan Roese andc r23,r23,r22 448a47a12beSStefan Roese stw r23,_MSR(r21) 449a47a12beSStefan Roese SAVE_GPR(7, r21) 450a47a12beSStefan Roese SAVE_4GPRS(8, r21) 451a47a12beSStefan Roese SAVE_8GPRS(12, r21) 452a47a12beSStefan Roese SAVE_8GPRS(24, r21) 453a47a12beSStefan Roese mflr r23 454a47a12beSStefan Roese andi. r24,r23,0x3f00 /* get vector offset */ 455a47a12beSStefan Roese stw r24,TRAP(r21) 456a47a12beSStefan Roese li r22,0 457a47a12beSStefan Roese stw r22,RESULT(r21) 458a47a12beSStefan Roese mtspr SPRG2,r22 /* r1 is now kernel sp */ 459a47a12beSStefan Roese lwz r24,0(r23) /* virtual address of handler */ 460a47a12beSStefan Roese lwz r23,4(r23) /* where to go when done */ 461a47a12beSStefan Roese mtspr SRR0,r24 462a47a12beSStefan Roese mtspr SRR1,r20 463a47a12beSStefan Roese mtlr r23 464a47a12beSStefan Roese SYNC 465a47a12beSStefan Roese rfi /* jump to handler, enable MMU */ 466a47a12beSStefan Roese 467a47a12beSStefan Roeseint_return: 468a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 469a47a12beSStefan Roese li r4,0 470a47a12beSStefan Roese ori r4,r4,MSR_EE 471a47a12beSStefan Roese andc r28,r28,r4 472a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 473a47a12beSStefan Roese mtmsr r28 474a47a12beSStefan Roese SYNC 475a47a12beSStefan Roese lwz r2,_CTR(r1) 476a47a12beSStefan Roese lwz r0,_LINK(r1) 477a47a12beSStefan Roese mtctr r2 478a47a12beSStefan Roese mtlr r0 479a47a12beSStefan Roese lwz r2,_XER(r1) 480a47a12beSStefan Roese lwz r0,_CCR(r1) 481a47a12beSStefan Roese mtspr XER,r2 482a47a12beSStefan Roese mtcrf 0xFF,r0 483a47a12beSStefan Roese REST_10GPRS(3, r1) 484a47a12beSStefan Roese REST_10GPRS(13, r1) 485a47a12beSStefan Roese REST_8GPRS(23, r1) 486a47a12beSStefan Roese REST_GPR(31, r1) 487a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 488a47a12beSStefan Roese lwz r0,_MSR(r1) 489a47a12beSStefan Roese mtspr SRR0,r2 490a47a12beSStefan Roese mtspr SRR1,r0 491a47a12beSStefan Roese lwz r0,GPR0(r1) 492a47a12beSStefan Roese lwz r2,GPR2(r1) 493a47a12beSStefan Roese lwz r1,GPR1(r1) 494a47a12beSStefan Roese SYNC 495a47a12beSStefan Roese rfi 496a47a12beSStefan Roese 497a47a12beSStefan Roese .globl dc_read 498a47a12beSStefan Roesedc_read: 499a47a12beSStefan Roese blr 500a47a12beSStefan Roese 501a47a12beSStefan Roese .globl get_pvr 502a47a12beSStefan Roeseget_pvr: 503a47a12beSStefan Roese mfspr r3, PVR 504a47a12beSStefan Roese blr 505a47a12beSStefan Roese 506a47a12beSStefan Roese .globl get_svr 507a47a12beSStefan Roeseget_svr: 508a47a12beSStefan Roese mfspr r3, SVR 509a47a12beSStefan Roese blr 510a47a12beSStefan Roese 511a47a12beSStefan Roese 512a47a12beSStefan Roese/* 513a47a12beSStefan Roese * Function: in8 514a47a12beSStefan Roese * Description: Input 8 bits 515a47a12beSStefan Roese */ 516a47a12beSStefan Roese .globl in8 517a47a12beSStefan Roesein8: 518a47a12beSStefan Roese lbz r3,0x0000(r3) 519a47a12beSStefan Roese blr 520a47a12beSStefan Roese 521a47a12beSStefan Roese/* 522a47a12beSStefan Roese * Function: out8 523a47a12beSStefan Roese * Description: Output 8 bits 524a47a12beSStefan Roese */ 525a47a12beSStefan Roese .globl out8 526a47a12beSStefan Roeseout8: 527a47a12beSStefan Roese stb r4,0x0000(r3) 528a47a12beSStefan Roese blr 529a47a12beSStefan Roese 530a47a12beSStefan Roese/* 531a47a12beSStefan Roese * Function: out16 532a47a12beSStefan Roese * Description: Output 16 bits 533a47a12beSStefan Roese */ 534a47a12beSStefan Roese .globl out16 535a47a12beSStefan Roeseout16: 536a47a12beSStefan Roese sth r4,0x0000(r3) 537a47a12beSStefan Roese blr 538a47a12beSStefan Roese 539a47a12beSStefan Roese/* 540a47a12beSStefan Roese * Function: out16r 541a47a12beSStefan Roese * Description: Byte reverse and output 16 bits 542a47a12beSStefan Roese */ 543a47a12beSStefan Roese .globl out16r 544a47a12beSStefan Roeseout16r: 545a47a12beSStefan Roese sthbrx r4,r0,r3 546a47a12beSStefan Roese blr 547a47a12beSStefan Roese 548a47a12beSStefan Roese/* 549a47a12beSStefan Roese * Function: out32 550a47a12beSStefan Roese * Description: Output 32 bits 551a47a12beSStefan Roese */ 552a47a12beSStefan Roese .globl out32 553a47a12beSStefan Roeseout32: 554a47a12beSStefan Roese stw r4,0x0000(r3) 555a47a12beSStefan Roese blr 556a47a12beSStefan Roese 557a47a12beSStefan Roese/* 558a47a12beSStefan Roese * Function: out32r 559a47a12beSStefan Roese * Description: Byte reverse and output 32 bits 560a47a12beSStefan Roese */ 561a47a12beSStefan Roese .globl out32r 562a47a12beSStefan Roeseout32r: 563a47a12beSStefan Roese stwbrx r4,r0,r3 564a47a12beSStefan Roese blr 565a47a12beSStefan Roese 566a47a12beSStefan Roese/* 567a47a12beSStefan Roese * Function: in16 568a47a12beSStefan Roese * Description: Input 16 bits 569a47a12beSStefan Roese */ 570a47a12beSStefan Roese .globl in16 571a47a12beSStefan Roesein16: 572a47a12beSStefan Roese lhz r3,0x0000(r3) 573a47a12beSStefan Roese blr 574a47a12beSStefan Roese 575a47a12beSStefan Roese/* 576a47a12beSStefan Roese * Function: in16r 577a47a12beSStefan Roese * Description: Input 16 bits and byte reverse 578a47a12beSStefan Roese */ 579a47a12beSStefan Roese .globl in16r 580a47a12beSStefan Roesein16r: 581a47a12beSStefan Roese lhbrx r3,r0,r3 582a47a12beSStefan Roese blr 583a47a12beSStefan Roese 584a47a12beSStefan Roese/* 585a47a12beSStefan Roese * Function: in32 586a47a12beSStefan Roese * Description: Input 32 bits 587a47a12beSStefan Roese */ 588a47a12beSStefan Roese .globl in32 589a47a12beSStefan Roesein32: 590a47a12beSStefan Roese lwz 3,0x0000(3) 591a47a12beSStefan Roese blr 592a47a12beSStefan Roese 593a47a12beSStefan Roese/* 594a47a12beSStefan Roese * Function: in32r 595a47a12beSStefan Roese * Description: Input 32 bits and byte reverse 596a47a12beSStefan Roese */ 597a47a12beSStefan Roese .globl in32r 598a47a12beSStefan Roesein32r: 599a47a12beSStefan Roese lwbrx r3,r0,r3 600a47a12beSStefan Roese blr 601a47a12beSStefan Roese 602a47a12beSStefan Roese/* 603a47a12beSStefan Roese * void relocate_code (addr_sp, gd, addr_moni) 604a47a12beSStefan Roese * 605a47a12beSStefan Roese * This "function" does not return, instead it continues in RAM 606a47a12beSStefan Roese * after relocating the monitor code. 607a47a12beSStefan Roese * 608a47a12beSStefan Roese * r3 = dest 609a47a12beSStefan Roese * r4 = src 610a47a12beSStefan Roese * r5 = length in bytes 611a47a12beSStefan Roese * r6 = cachelinesize 612a47a12beSStefan Roese */ 613a47a12beSStefan Roese .globl relocate_code 614a47a12beSStefan Roeserelocate_code: 615a47a12beSStefan Roese 616a47a12beSStefan Roese mr r1, r3 /* Set new stack pointer */ 617a47a12beSStefan Roese mr r9, r4 /* Save copy of Global Data pointer */ 618a47a12beSStefan Roese mr r10, r5 /* Save copy of Destination Address */ 619a47a12beSStefan Roese 620a47a12beSStefan Roese GET_GOT 621a47a12beSStefan Roese mr r3, r5 /* Destination Address */ 622a47a12beSStefan Roese lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 623a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 624a47a12beSStefan Roese lwz r5, GOT(__init_end) 625a47a12beSStefan Roese sub r5, r5, r4 626a47a12beSStefan Roese li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 627a47a12beSStefan Roese 628a47a12beSStefan Roese /* 629a47a12beSStefan Roese * Fix GOT pointer: 630a47a12beSStefan Roese * 631a47a12beSStefan Roese * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 632a47a12beSStefan Roese * 633a47a12beSStefan Roese * Offset: 634a47a12beSStefan Roese */ 635a47a12beSStefan Roese sub r15, r10, r4 636a47a12beSStefan Roese 637a47a12beSStefan Roese /* First our own GOT */ 638a47a12beSStefan Roese add r12, r12, r15 639a47a12beSStefan Roese /* then the one used by the C code */ 640a47a12beSStefan Roese add r30, r30, r15 641a47a12beSStefan Roese 642a47a12beSStefan Roese /* 643a47a12beSStefan Roese * Now relocate code 644a47a12beSStefan Roese */ 645a47a12beSStefan Roese cmplw cr1,r3,r4 646a47a12beSStefan Roese addi r0,r5,3 647a47a12beSStefan Roese srwi. r0,r0,2 648a47a12beSStefan Roese beq cr1,4f /* In place copy is not necessary */ 649a47a12beSStefan Roese beq 7f /* Protect against 0 count */ 650a47a12beSStefan Roese mtctr r0 651a47a12beSStefan Roese bge cr1,2f 652a47a12beSStefan Roese 653a47a12beSStefan Roese la r8,-4(r4) 654a47a12beSStefan Roese la r7,-4(r3) 655a47a12beSStefan Roese1: lwzu r0,4(r8) 656a47a12beSStefan Roese stwu r0,4(r7) 657a47a12beSStefan Roese bdnz 1b 658a47a12beSStefan Roese b 4f 659a47a12beSStefan Roese 660a47a12beSStefan Roese2: slwi r0,r0,2 661a47a12beSStefan Roese add r8,r4,r0 662a47a12beSStefan Roese add r7,r3,r0 663a47a12beSStefan Roese3: lwzu r0,-4(r8) 664a47a12beSStefan Roese stwu r0,-4(r7) 665a47a12beSStefan Roese bdnz 3b 666a47a12beSStefan Roese/* 667a47a12beSStefan Roese * Now flush the cache: note that we must start from a cache aligned 668a47a12beSStefan Roese * address. Otherwise we might miss one cache line. 669a47a12beSStefan Roese */ 670a47a12beSStefan Roese4: cmpwi r6,0 671a47a12beSStefan Roese add r5,r3,r5 672a47a12beSStefan Roese beq 7f /* Always flush prefetch queue in any case */ 673a47a12beSStefan Roese subi r0,r6,1 674a47a12beSStefan Roese andc r3,r3,r0 675a47a12beSStefan Roese mr r4,r3 676a47a12beSStefan Roese5: dcbst 0,r4 677a47a12beSStefan Roese add r4,r4,r6 678a47a12beSStefan Roese cmplw r4,r5 679a47a12beSStefan Roese blt 5b 680a47a12beSStefan Roese sync /* Wait for all dcbst to complete on bus */ 681a47a12beSStefan Roese mr r4,r3 682a47a12beSStefan Roese6: icbi 0,r4 683a47a12beSStefan Roese add r4,r4,r6 684a47a12beSStefan Roese cmplw r4,r5 685a47a12beSStefan Roese blt 6b 686a47a12beSStefan Roese7: sync /* Wait for all icbi to complete on bus */ 687a47a12beSStefan Roese isync 688a47a12beSStefan Roese 689a47a12beSStefan Roese/* 690a47a12beSStefan Roese * We are done. Do not return, instead branch to second part of board 691a47a12beSStefan Roese * initialization, now running from RAM. 692a47a12beSStefan Roese */ 693a47a12beSStefan Roese addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 694a47a12beSStefan Roese mtlr r0 695a47a12beSStefan Roese blr 696a47a12beSStefan Roese 697a47a12beSStefan Roesein_ram: 698a47a12beSStefan Roese /* 699a47a12beSStefan Roese * Relocation Function, r12 point to got2+0x8000 700a47a12beSStefan Roese * 701a47a12beSStefan Roese * Adjust got2 pointers, no need to check for 0, this code 702a47a12beSStefan Roese * already puts a few entries in the table. 703a47a12beSStefan Roese */ 704a47a12beSStefan Roese li r0,__got2_entries@sectoff@l 705a47a12beSStefan Roese la r3,GOT(_GOT2_TABLE_) 706a47a12beSStefan Roese lwz r11,GOT(_GOT2_TABLE_) 707a47a12beSStefan Roese mtctr r0 708a47a12beSStefan Roese sub r11,r3,r11 709a47a12beSStefan Roese addi r3,r3,-4 710a47a12beSStefan Roese1: lwzu r0,4(r3) 711a47a12beSStefan Roese cmpwi r0,0 712a47a12beSStefan Roese beq- 2f 713a47a12beSStefan Roese add r0,r0,r11 714a47a12beSStefan Roese stw r0,0(r3) 715a47a12beSStefan Roese2: bdnz 1b 716a47a12beSStefan Roese 717a47a12beSStefan Roese /* 718a47a12beSStefan Roese * Now adjust the fixups and the pointers to the fixups 719a47a12beSStefan Roese * in case we need to move ourselves again. 720a47a12beSStefan Roese */ 721a47a12beSStefan Roese li r0,__fixup_entries@sectoff@l 722a47a12beSStefan Roese lwz r3,GOT(_FIXUP_TABLE_) 723a47a12beSStefan Roese cmpwi r0,0 724a47a12beSStefan Roese mtctr r0 725a47a12beSStefan Roese addi r3,r3,-4 726a47a12beSStefan Roese beq 4f 727a47a12beSStefan Roese3: lwzu r4,4(r3) 728a47a12beSStefan Roese lwzux r0,r4,r11 729a47a12beSStefan Roese add r0,r0,r11 730a47a12beSStefan Roese stw r10,0(r3) 731a47a12beSStefan Roese stw r0,0(r4) 732a47a12beSStefan Roese bdnz 3b 733a47a12beSStefan Roese4: 734a47a12beSStefan Roese/* clear_bss: */ 735a47a12beSStefan Roese /* 736a47a12beSStefan Roese * Now clear BSS segment 737a47a12beSStefan Roese */ 738a47a12beSStefan Roese lwz r3,GOT(__bss_start) 739a47a12beSStefan Roese lwz r4,GOT(_end) 740a47a12beSStefan Roese 741a47a12beSStefan Roese cmplw 0, r3, r4 742a47a12beSStefan Roese beq 6f 743a47a12beSStefan Roese 744a47a12beSStefan Roese li r0, 0 745a47a12beSStefan Roese5: 746a47a12beSStefan Roese stw r0, 0(r3) 747a47a12beSStefan Roese addi r3, r3, 4 748a47a12beSStefan Roese cmplw 0, r3, r4 749a47a12beSStefan Roese bne 5b 750a47a12beSStefan Roese6: 751a47a12beSStefan Roese mr r3, r9 /* Init Date pointer */ 752a47a12beSStefan Roese mr r4, r10 /* Destination Address */ 753a47a12beSStefan Roese bl board_init_r 754a47a12beSStefan Roese 755a47a12beSStefan Roese /* not reached - end relocate_code */ 756a47a12beSStefan Roese/*-----------------------------------------------------------------------*/ 757a47a12beSStefan Roese 758a47a12beSStefan Roese /* 759a47a12beSStefan Roese * Copy exception vector code to low memory 760a47a12beSStefan Roese * 761a47a12beSStefan Roese * r3: dest_addr 762a47a12beSStefan Roese * r7: source address, r8: end address, r9: target address 763a47a12beSStefan Roese */ 764a47a12beSStefan Roese .globl trap_init 765a47a12beSStefan Roesetrap_init: 766a47a12beSStefan Roese mflr r4 /* save link register */ 767a47a12beSStefan Roese GET_GOT 768a47a12beSStefan Roese lwz r7, GOT(_start) 769a47a12beSStefan Roese lwz r8, GOT(_end_of_vectors) 770a47a12beSStefan Roese 771a47a12beSStefan Roese li r9, 0x100 /* reset vector always at 0x100 */ 772a47a12beSStefan Roese 773a47a12beSStefan Roese cmplw 0, r7, r8 774a47a12beSStefan Roese bgelr /* return if r7>=r8 - just in case */ 775a47a12beSStefan Roese1: 776a47a12beSStefan Roese lwz r0, 0(r7) 777a47a12beSStefan Roese stw r0, 0(r9) 778a47a12beSStefan Roese addi r7, r7, 4 779a47a12beSStefan Roese addi r9, r9, 4 780a47a12beSStefan Roese cmplw 0, r7, r8 781a47a12beSStefan Roese bne 1b 782a47a12beSStefan Roese 783a47a12beSStefan Roese /* 784a47a12beSStefan Roese * relocate `hdlr' and `int_return' entries 785a47a12beSStefan Roese */ 786a47a12beSStefan Roese li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 787a47a12beSStefan Roese li r8, Alignment - _start + EXC_OFF_SYS_RESET 788a47a12beSStefan Roese2: 789a47a12beSStefan Roese bl trap_reloc 790a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 791a47a12beSStefan Roese cmplw 0, r7, r8 792a47a12beSStefan Roese blt 2b 793a47a12beSStefan Roese 794a47a12beSStefan Roese li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 795a47a12beSStefan Roese bl trap_reloc 796a47a12beSStefan Roese 797a47a12beSStefan Roese li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 798a47a12beSStefan Roese bl trap_reloc 799a47a12beSStefan Roese 800a47a12beSStefan Roese li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 801a47a12beSStefan Roese li r8, SystemCall - _start + EXC_OFF_SYS_RESET 802a47a12beSStefan Roese3: 803a47a12beSStefan Roese bl trap_reloc 804a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 805a47a12beSStefan Roese cmplw 0, r7, r8 806a47a12beSStefan Roese blt 3b 807a47a12beSStefan Roese 808a47a12beSStefan Roese li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 809a47a12beSStefan Roese li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 810a47a12beSStefan Roese4: 811a47a12beSStefan Roese bl trap_reloc 812a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 813a47a12beSStefan Roese cmplw 0, r7, r8 814a47a12beSStefan Roese blt 4b 815a47a12beSStefan Roese 816a47a12beSStefan Roese /* enable execptions from RAM vectors */ 817a47a12beSStefan Roese mfmsr r7 818a47a12beSStefan Roese li r8,MSR_IP 819a47a12beSStefan Roese andc r7,r7,r8 820a47a12beSStefan Roese ori r7,r7,MSR_ME /* Enable Machine Check */ 821a47a12beSStefan Roese mtmsr r7 822a47a12beSStefan Roese 823a47a12beSStefan Roese mtlr r4 /* restore link register */ 824a47a12beSStefan Roese blr 825a47a12beSStefan Roese 826a47a12beSStefan Roese.globl enable_ext_addr 827a47a12beSStefan Roeseenable_ext_addr: 828a47a12beSStefan Roese mfspr r0, HID0 829a47a12beSStefan Roese lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h 830a47a12beSStefan Roese ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l 831a47a12beSStefan Roese mtspr HID0, r0 832a47a12beSStefan Roese sync 833a47a12beSStefan Roese isync 834a47a12beSStefan Roese blr 835a47a12beSStefan Roese 836a47a12beSStefan Roese#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 837a47a12beSStefan Roese.globl setup_ccsrbar 838a47a12beSStefan Roesesetup_ccsrbar: 839a47a12beSStefan Roese /* Special sequence needed to update CCSRBAR itself */ 840a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h 841a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l 842a47a12beSStefan Roese 843a47a12beSStefan Roese lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 844a47a12beSStefan Roese ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 845a47a12beSStefan Roese srwi r5,r5,12 846a47a12beSStefan Roese li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 847a47a12beSStefan Roese rlwimi r5,r6,20,8,11 848a47a12beSStefan Roese stw r5, 0(r4) /* Store physical value of CCSR */ 849a47a12beSStefan Roese isync 850a47a12beSStefan Roese 851*14d0a02aSWolfgang Denk lis r5, CONFIG_SYS_TEXT_BASE@h 852*14d0a02aSWolfgang Denk ori r5,r5,CONFIG_SYS_TEXT_BASE@l 853a47a12beSStefan Roese lwz r5, 0(r5) 854a47a12beSStefan Roese isync 855a47a12beSStefan Roese 856a47a12beSStefan Roese /* Use VA of CCSR to do read */ 857a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSRBAR@h 858a47a12beSStefan Roese lwz r5, CONFIG_SYS_CCSRBAR@l(r3) 859a47a12beSStefan Roese isync 860a47a12beSStefan Roese 861a47a12beSStefan Roese blr 862a47a12beSStefan Roese#endif 863a47a12beSStefan Roese 864a47a12beSStefan Roese#ifdef CONFIG_SYS_INIT_RAM_LOCK 865a47a12beSStefan Roeselock_ram_in_cache: 866a47a12beSStefan Roese /* Allocate Initial RAM in data cache. 867a47a12beSStefan Roese */ 868a47a12beSStefan Roese lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 869a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 870a47a12beSStefan Roese li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ 871a47a12beSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 872a47a12beSStefan Roese mtctr r4 873a47a12beSStefan Roese1: 874a47a12beSStefan Roese dcbz r0, r3 875a47a12beSStefan Roese addi r3, r3, 32 876a47a12beSStefan Roese bdnz 1b 877a47a12beSStefan Roese#if 1 878a47a12beSStefan Roese/* Lock the data cache */ 879a47a12beSStefan Roese mfspr r0, HID0 880a47a12beSStefan Roese ori r0, r0, 0x1000 881a47a12beSStefan Roese sync 882a47a12beSStefan Roese mtspr HID0, r0 883a47a12beSStefan Roese sync 884a47a12beSStefan Roese blr 885a47a12beSStefan Roese#endif 886a47a12beSStefan Roese#if 0 887a47a12beSStefan Roese /* Lock the first way of the data cache */ 888a47a12beSStefan Roese mfspr r0, LDSTCR 889a47a12beSStefan Roese ori r0, r0, 0x0080 890a47a12beSStefan Roese#if defined(CONFIG_ALTIVEC) 891a47a12beSStefan Roese dssall 892a47a12beSStefan Roese#endif 893a47a12beSStefan Roese sync 894a47a12beSStefan Roese mtspr LDSTCR, r0 895a47a12beSStefan Roese sync 896a47a12beSStefan Roese isync 897a47a12beSStefan Roese blr 898a47a12beSStefan Roese#endif 899a47a12beSStefan Roese 900a47a12beSStefan Roese.globl unlock_ram_in_cache 901a47a12beSStefan Roeseunlock_ram_in_cache: 902a47a12beSStefan Roese /* invalidate the INIT_RAM section */ 903a47a12beSStefan Roese lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 904a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 905a47a12beSStefan Roese li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ 906a47a12beSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 907a47a12beSStefan Roese mtctr r4 908a47a12beSStefan Roese1: icbi r0, r3 909a47a12beSStefan Roese addi r3, r3, 32 910a47a12beSStefan Roese bdnz 1b 911a47a12beSStefan Roese sync /* Wait for all icbi to complete on bus */ 912a47a12beSStefan Roese isync 913a47a12beSStefan Roese#if 1 914a47a12beSStefan Roese/* Unlock the data cache and invalidate it */ 915a47a12beSStefan Roese mfspr r0, HID0 916a47a12beSStefan Roese li r3,0x1000 917a47a12beSStefan Roese andc r0,r0,r3 918a47a12beSStefan Roese li r3,0x0400 919a47a12beSStefan Roese or r0,r0,r3 920a47a12beSStefan Roese sync 921a47a12beSStefan Roese mtspr HID0, r0 922a47a12beSStefan Roese sync 923a47a12beSStefan Roese blr 924a47a12beSStefan Roese#endif 925a47a12beSStefan Roese#if 0 926a47a12beSStefan Roese /* Unlock the first way of the data cache */ 927a47a12beSStefan Roese mfspr r0, LDSTCR 928a47a12beSStefan Roese li r3,0x0080 929a47a12beSStefan Roese andc r0,r0,r3 930a47a12beSStefan Roese#ifdef CONFIG_ALTIVEC 931a47a12beSStefan Roese dssall 932a47a12beSStefan Roese#endif 933a47a12beSStefan Roese sync 934a47a12beSStefan Roese mtspr LDSTCR, r0 935a47a12beSStefan Roese sync 936a47a12beSStefan Roese isync 937a47a12beSStefan Roese li r3,0x0400 938a47a12beSStefan Roese or r0,r0,r3 939a47a12beSStefan Roese sync 940a47a12beSStefan Roese mtspr HID0, r0 941a47a12beSStefan Roese sync 942a47a12beSStefan Roese blr 943a47a12beSStefan Roese#endif 944a47a12beSStefan Roese#endif 945