1*a47a12beSStefan Roese/* 2*a47a12beSStefan Roese * Copyright 2004, 2007, 2008 Freescale Semiconductor. 3*a47a12beSStefan Roese * Srikanth Srinivasan <srikanth.srinivaan@freescale.com> 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6*a47a12beSStefan Roese * project. 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11*a47a12beSStefan Roese * the License, or (at your option) any later version. 12*a47a12beSStefan Roese * 13*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*a47a12beSStefan Roese * GNU General Public License for more details. 17*a47a12beSStefan Roese * 18*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*a47a12beSStefan Roese * MA 02111-1307 USA 22*a47a12beSStefan Roese */ 23*a47a12beSStefan Roese#include <config.h> 24*a47a12beSStefan Roese#include <mpc86xx.h> 25*a47a12beSStefan Roese#include <version.h> 26*a47a12beSStefan Roese 27*a47a12beSStefan Roese#include <ppc_asm.tmpl> 28*a47a12beSStefan Roese#include <ppc_defs.h> 29*a47a12beSStefan Roese 30*a47a12beSStefan Roese#include <asm/cache.h> 31*a47a12beSStefan Roese#include <asm/mmu.h> 32*a47a12beSStefan Roese 33*a47a12beSStefan Roese/* If this is a multi-cpu system then we need to handle the 34*a47a12beSStefan Roese * 2nd cpu. The assumption is that the 2nd cpu is being 35*a47a12beSStefan Roese * held in boot holdoff mode until the 1st cpu unlocks it 36*a47a12beSStefan Roese * from Linux. We'll do some basic cpu init and then pass 37*a47a12beSStefan Roese * it to the Linux Reset Vector. 38*a47a12beSStefan Roese * Sri: Much of this initialization is not required. Linux 39*a47a12beSStefan Roese * rewrites the bats, and the sprs and also enables the L1 cache. 40*a47a12beSStefan Roese * 41*a47a12beSStefan Roese * Core 0 must copy this to a 1M aligned region and set BPTR 42*a47a12beSStefan Roese * to point to it. 43*a47a12beSStefan Roese */ 44*a47a12beSStefan Roese .align 12 45*a47a12beSStefan Roese.globl __secondary_start_page 46*a47a12beSStefan Roese__secondary_start_page: 47*a47a12beSStefan Roese .space 0x100 /* space over to reset vector loc */ 48*a47a12beSStefan Roese mfspr r0, MSSCR0 49*a47a12beSStefan Roese andi. r0, r0, 0x0020 50*a47a12beSStefan Roese rlwinm r0,r0,27,31,31 51*a47a12beSStefan Roese mtspr PIR, r0 52*a47a12beSStefan Roese 53*a47a12beSStefan Roese /* Invalidate BATs */ 54*a47a12beSStefan Roese li r0, 0 55*a47a12beSStefan Roese mtspr IBAT0U, r0 56*a47a12beSStefan Roese mtspr IBAT1U, r0 57*a47a12beSStefan Roese mtspr IBAT2U, r0 58*a47a12beSStefan Roese mtspr IBAT3U, r0 59*a47a12beSStefan Roese mtspr IBAT4U, r0 60*a47a12beSStefan Roese mtspr IBAT5U, r0 61*a47a12beSStefan Roese mtspr IBAT6U, r0 62*a47a12beSStefan Roese mtspr IBAT7U, r0 63*a47a12beSStefan Roese isync 64*a47a12beSStefan Roese mtspr DBAT0U, r0 65*a47a12beSStefan Roese mtspr DBAT1U, r0 66*a47a12beSStefan Roese mtspr DBAT2U, r0 67*a47a12beSStefan Roese mtspr DBAT3U, r0 68*a47a12beSStefan Roese mtspr DBAT4U, r0 69*a47a12beSStefan Roese mtspr DBAT5U, r0 70*a47a12beSStefan Roese mtspr DBAT6U, r0 71*a47a12beSStefan Roese mtspr DBAT7U, r0 72*a47a12beSStefan Roese isync 73*a47a12beSStefan Roese sync 74*a47a12beSStefan Roese 75*a47a12beSStefan Roese /* enable extended addressing */ 76*a47a12beSStefan Roese mfspr r0, HID0 77*a47a12beSStefan Roese lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h 78*a47a12beSStefan Roese ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l 79*a47a12beSStefan Roese mtspr HID0, r0 80*a47a12beSStefan Roese sync 81*a47a12beSStefan Roese isync 82*a47a12beSStefan Roese 83*a47a12beSStefan Roese#ifdef CONFIG_SYS_L2 84*a47a12beSStefan Roese /* init the L2 cache */ 85*a47a12beSStefan Roese addis r3, r0, L2_INIT@h 86*a47a12beSStefan Roese ori r3, r3, L2_INIT@l 87*a47a12beSStefan Roese sync 88*a47a12beSStefan Roese mtspr l2cr, r3 89*a47a12beSStefan Roese#ifdef CONFIG_ALTIVEC 90*a47a12beSStefan Roese dssall 91*a47a12beSStefan Roese#endif 92*a47a12beSStefan Roese /* invalidate the L2 cache */ 93*a47a12beSStefan Roese mfspr r3, l2cr 94*a47a12beSStefan Roese rlwinm. r3, r3, 0, 0, 0 95*a47a12beSStefan Roese beq 1f 96*a47a12beSStefan Roese 97*a47a12beSStefan Roese mfspr r3, l2cr 98*a47a12beSStefan Roese rlwinm r3, r3, 0, 1, 31 99*a47a12beSStefan Roese 100*a47a12beSStefan Roese#ifdef CONFIG_ALTIVEC 101*a47a12beSStefan Roese dssall 102*a47a12beSStefan Roese#endif 103*a47a12beSStefan Roese sync 104*a47a12beSStefan Roese mtspr l2cr, r3 105*a47a12beSStefan Roese sync 106*a47a12beSStefan Roese1: mfspr r3, l2cr 107*a47a12beSStefan Roese oris r3, r3, L2CR_L2I@h 108*a47a12beSStefan Roese mtspr l2cr, r3 109*a47a12beSStefan Roese 110*a47a12beSStefan Roeseinvl2: 111*a47a12beSStefan Roese mfspr r3, l2cr 112*a47a12beSStefan Roese andis. r3, r3, L2CR_L2I@h 113*a47a12beSStefan Roese bne invl2 114*a47a12beSStefan Roese sync 115*a47a12beSStefan Roese#endif 116*a47a12beSStefan Roese 117*a47a12beSStefan Roese /* enable and invalidate the data cache */ 118*a47a12beSStefan Roese mfspr r3, HID0 119*a47a12beSStefan Roese li r5, HID0_DCFI|HID0_DLOCK 120*a47a12beSStefan Roese andc r3, r3, r5 121*a47a12beSStefan Roese mtspr HID0, r3 /* no invalidate, unlock */ 122*a47a12beSStefan Roese ori r3, r3, HID0_DCE 123*a47a12beSStefan Roese ori r5, r3, HID0_DCFI 124*a47a12beSStefan Roese mtspr HID0, r5 /* enable + invalidate */ 125*a47a12beSStefan Roese mtspr HID0, r3 /* enable */ 126*a47a12beSStefan Roese sync 127*a47a12beSStefan Roese#ifdef CONFIG_SYS_L2 128*a47a12beSStefan Roese sync 129*a47a12beSStefan Roese lis r3, L2_ENABLE@h 130*a47a12beSStefan Roese ori r3, r3, L2_ENABLE@l 131*a47a12beSStefan Roese mtspr l2cr, r3 132*a47a12beSStefan Roese isync 133*a47a12beSStefan Roese sync 134*a47a12beSStefan Roese#endif 135*a47a12beSStefan Roese 136*a47a12beSStefan Roese /* enable and invalidate the instruction cache*/ 137*a47a12beSStefan Roese mfspr r3, HID0 138*a47a12beSStefan Roese li r5, HID0_ICFI|HID0_ILOCK 139*a47a12beSStefan Roese andc r3, r3, r5 140*a47a12beSStefan Roese ori r3, r3, HID0_ICE 141*a47a12beSStefan Roese ori r5, r3, HID0_ICFI 142*a47a12beSStefan Roese mtspr HID0, r5 143*a47a12beSStefan Roese mtspr HID0, r3 144*a47a12beSStefan Roese isync 145*a47a12beSStefan Roese sync 146*a47a12beSStefan Roese 147*a47a12beSStefan Roese /* TBEN in HID0 */ 148*a47a12beSStefan Roese mfspr r4, HID0 149*a47a12beSStefan Roese oris r4, r4, 0x0400 150*a47a12beSStefan Roese mtspr HID0, r4 151*a47a12beSStefan Roese sync 152*a47a12beSStefan Roese isync 153*a47a12beSStefan Roese 154*a47a12beSStefan Roese /* MCP|SYNCBE|ABE in HID1 */ 155*a47a12beSStefan Roese mfspr r4, HID1 156*a47a12beSStefan Roese oris r4, r4, 0x8000 157*a47a12beSStefan Roese ori r4, r4, 0x0C00 158*a47a12beSStefan Roese mtspr HID1, r4 159*a47a12beSStefan Roese sync 160*a47a12beSStefan Roese isync 161*a47a12beSStefan Roese 162*a47a12beSStefan Roese lis r3, CONFIG_LINUX_RESET_VEC@h 163*a47a12beSStefan Roese ori r3, r3, CONFIG_LINUX_RESET_VEC@l 164*a47a12beSStefan Roese mtlr r3 165*a47a12beSStefan Roese blr 166*a47a12beSStefan Roese 167*a47a12beSStefan Roese /* Never Returns, Running in Linux Now */ 168