1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * Copyright 2008-2010 Freescale Semiconductor, Inc. 3*a47a12beSStefan Roese * 4*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 5*a47a12beSStefan Roese * project. 6*a47a12beSStefan Roese * 7*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 8*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 9*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 10*a47a12beSStefan Roese * the License, or (at your option) any later version. 11*a47a12beSStefan Roese * 12*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 13*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*a47a12beSStefan Roese * GNU General Public License for more details. 16*a47a12beSStefan Roese * 17*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 18*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 19*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20*a47a12beSStefan Roese * MA 02111-1307 USA 21*a47a12beSStefan Roese */ 22*a47a12beSStefan Roese 23*a47a12beSStefan Roese #include <common.h> 24*a47a12beSStefan Roese #include <asm/processor.h> 25*a47a12beSStefan Roese #include <asm/mmu.h> 26*a47a12beSStefan Roese #include <ioports.h> 27*a47a12beSStefan Roese #include <lmb.h> 28*a47a12beSStefan Roese #include <asm/io.h> 29*a47a12beSStefan Roese #include <asm/mp.h> 30*a47a12beSStefan Roese 31*a47a12beSStefan Roese DECLARE_GLOBAL_DATA_PTR; 32*a47a12beSStefan Roese 33*a47a12beSStefan Roese int cpu_reset(int nr) 34*a47a12beSStefan Roese { 35*a47a12beSStefan Roese /* dummy function so common/cmd_mp.c will build 36*a47a12beSStefan Roese * should be implemented in the future, when cpu_release() 37*a47a12beSStefan Roese * is supported. Be aware there may be a similiar bug 38*a47a12beSStefan Roese * as exists on MPC85xx w/its PIC having a timing window 39*a47a12beSStefan Roese * associated to resetting the core */ 40*a47a12beSStefan Roese return 1; 41*a47a12beSStefan Roese } 42*a47a12beSStefan Roese 43*a47a12beSStefan Roese int cpu_status(int nr) 44*a47a12beSStefan Roese { 45*a47a12beSStefan Roese /* dummy function so common/cmd_mp.c will build */ 46*a47a12beSStefan Roese return 0; 47*a47a12beSStefan Roese } 48*a47a12beSStefan Roese 49*a47a12beSStefan Roese int cpu_disable(int nr) 50*a47a12beSStefan Roese { 51*a47a12beSStefan Roese volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 52*a47a12beSStefan Roese volatile ccsr_gur_t *gur = &immap->im_gur; 53*a47a12beSStefan Roese 54*a47a12beSStefan Roese switch (nr) { 55*a47a12beSStefan Roese case 0: 56*a47a12beSStefan Roese setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0); 57*a47a12beSStefan Roese break; 58*a47a12beSStefan Roese case 1: 59*a47a12beSStefan Roese setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1); 60*a47a12beSStefan Roese break; 61*a47a12beSStefan Roese default: 62*a47a12beSStefan Roese printf("Invalid cpu number for disable %d\n", nr); 63*a47a12beSStefan Roese return 1; 64*a47a12beSStefan Roese } 65*a47a12beSStefan Roese 66*a47a12beSStefan Roese return 0; 67*a47a12beSStefan Roese } 68*a47a12beSStefan Roese 69*a47a12beSStefan Roese int cpu_release(int nr, int argc, char *argv[]) 70*a47a12beSStefan Roese { 71*a47a12beSStefan Roese /* dummy function so common/cmd_mp.c will build 72*a47a12beSStefan Roese * should be implemented in the future */ 73*a47a12beSStefan Roese return 1; 74*a47a12beSStefan Roese } 75*a47a12beSStefan Roese 76*a47a12beSStefan Roese u32 determine_mp_bootpg(void) 77*a47a12beSStefan Roese { 78*a47a12beSStefan Roese /* if we have 4G or more of memory, put the boot page at 4Gb-1M */ 79*a47a12beSStefan Roese if ((u64)gd->ram_size > 0xfffff000) 80*a47a12beSStefan Roese return (0xfff00000); 81*a47a12beSStefan Roese 82*a47a12beSStefan Roese return (gd->ram_size - (1024 * 1024)); 83*a47a12beSStefan Roese } 84*a47a12beSStefan Roese 85*a47a12beSStefan Roese void cpu_mp_lmb_reserve(struct lmb *lmb) 86*a47a12beSStefan Roese { 87*a47a12beSStefan Roese u32 bootpg = determine_mp_bootpg(); 88*a47a12beSStefan Roese 89*a47a12beSStefan Roese /* tell u-boot we stole a page */ 90*a47a12beSStefan Roese lmb_reserve(lmb, bootpg, 4096); 91*a47a12beSStefan Roese } 92*a47a12beSStefan Roese 93*a47a12beSStefan Roese /* 94*a47a12beSStefan Roese * Copy the code for other cpus to execute into an 95*a47a12beSStefan Roese * aligned location accessible via BPTR 96*a47a12beSStefan Roese */ 97*a47a12beSStefan Roese void setup_mp(void) 98*a47a12beSStefan Roese { 99*a47a12beSStefan Roese extern ulong __secondary_start_page; 100*a47a12beSStefan Roese ulong fixup = (ulong)&__secondary_start_page; 101*a47a12beSStefan Roese u32 bootpg = determine_mp_bootpg(); 102*a47a12beSStefan Roese u32 bootpg_va; 103*a47a12beSStefan Roese 104*a47a12beSStefan Roese if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) { 105*a47a12beSStefan Roese /* We're not covered by the DDR mapping, set up BAT */ 106*a47a12beSStefan Roese write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K | 107*a47a12beSStefan Roese BATU_VS | BATU_VP, 108*a47a12beSStefan Roese bootpg | BATL_PP_RW | BATL_MEMCOHERENCE); 109*a47a12beSStefan Roese bootpg_va = CONFIG_SYS_SCRATCH_VA; 110*a47a12beSStefan Roese } else { 111*a47a12beSStefan Roese bootpg_va = bootpg; 112*a47a12beSStefan Roese } 113*a47a12beSStefan Roese 114*a47a12beSStefan Roese memcpy((void *)bootpg_va, (void *)fixup, 4096); 115*a47a12beSStefan Roese flush_cache(bootpg_va, 4096); 116*a47a12beSStefan Roese 117*a47a12beSStefan Roese /* remove the temporary BAT mapping */ 118*a47a12beSStefan Roese if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) 119*a47a12beSStefan Roese write_bat(DBAT7, 0, 0); 120*a47a12beSStefan Roese 121*a47a12beSStefan Roese /* If the physical location of bootpg is not at fff00000, set BPTR */ 122*a47a12beSStefan Roese if (bootpg != 0xfff00000) 123*a47a12beSStefan Roese out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 | 124*a47a12beSStefan Roese (bootpg >> 12)); 125*a47a12beSStefan Roese } 126