1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2000-2002 3*a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * (C) Copyright 2002 (440 port) 6*a47a12beSStefan Roese * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * (C) Copyright 2003 Motorola Inc. (MPC85xx port) 9*a47a12beSStefan Roese * Xianghua Xiao (X.Xiao@motorola.com) 10*a47a12beSStefan Roese * 11*a47a12beSStefan Roese * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port) 12*a47a12beSStefan Roese * Jeff Brown 13*a47a12beSStefan Roese * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 14*a47a12beSStefan Roese * 15*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 16*a47a12beSStefan Roese * project. 17*a47a12beSStefan Roese * 18*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 19*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 20*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 21*a47a12beSStefan Roese * the License, or (at your option) any later version. 22*a47a12beSStefan Roese * 23*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 24*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 25*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26*a47a12beSStefan Roese * GNU General Public License for more details. 27*a47a12beSStefan Roese * 28*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 29*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 30*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31*a47a12beSStefan Roese * MA 02111-1307 USA 32*a47a12beSStefan Roese */ 33*a47a12beSStefan Roese 34*a47a12beSStefan Roese #include <common.h> 35*a47a12beSStefan Roese #include <mpc86xx.h> 36*a47a12beSStefan Roese #include <command.h> 37*a47a12beSStefan Roese #include <asm/processor.h> 38*a47a12beSStefan Roese 39*a47a12beSStefan Roese int interrupt_init_cpu(unsigned long *decrementer_count) 40*a47a12beSStefan Roese { 41*a47a12beSStefan Roese volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 42*a47a12beSStefan Roese volatile ccsr_pic_t *pic = &immr->im_pic; 43*a47a12beSStefan Roese 44*a47a12beSStefan Roese pic->gcr = MPC86xx_PICGCR_RST; 45*a47a12beSStefan Roese while (pic->gcr & MPC86xx_PICGCR_RST) 46*a47a12beSStefan Roese ; 47*a47a12beSStefan Roese pic->gcr = MPC86xx_PICGCR_MODE; 48*a47a12beSStefan Roese 49*a47a12beSStefan Roese *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; 50*a47a12beSStefan Roese debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n", 51*a47a12beSStefan Roese (get_tbclk() / 1000000), 52*a47a12beSStefan Roese *decrementer_count); 53*a47a12beSStefan Roese 54*a47a12beSStefan Roese #ifdef CONFIG_INTERRUPTS 55*a47a12beSStefan Roese 56*a47a12beSStefan Roese pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */ 57*a47a12beSStefan Roese debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1); 58*a47a12beSStefan Roese 59*a47a12beSStefan Roese pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ 60*a47a12beSStefan Roese debug("iivpr2@%x = %x\n", &pic->iivpr2, pic->iivpr2); 61*a47a12beSStefan Roese 62*a47a12beSStefan Roese pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ 63*a47a12beSStefan Roese debug("iivpr3@%x = %x\n", &pic->iivpr3, pic->iivpr3); 64*a47a12beSStefan Roese 65*a47a12beSStefan Roese #if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1) 66*a47a12beSStefan Roese pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */ 67*a47a12beSStefan Roese debug("iivpr8@%x = %x\n", &pic->iivpr8, pic->iivpr8); 68*a47a12beSStefan Roese #endif 69*a47a12beSStefan Roese #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) 70*a47a12beSStefan Roese pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */ 71*a47a12beSStefan Roese debug("iivpr9@%x = %x\n", &pic->iivpr9, pic->iivpr9); 72*a47a12beSStefan Roese #endif 73*a47a12beSStefan Roese 74*a47a12beSStefan Roese pic->ctpr = 0; /* 40080 clear current task priority register */ 75*a47a12beSStefan Roese #endif 76*a47a12beSStefan Roese 77*a47a12beSStefan Roese return 0; 78*a47a12beSStefan Roese } 79*a47a12beSStefan Roese 80*a47a12beSStefan Roese /* 81*a47a12beSStefan Roese * timer_interrupt - gets called when the decrementer overflows, 82*a47a12beSStefan Roese * with interrupts disabled. 83*a47a12beSStefan Roese * Trivial implementation - no need to be really accurate. 84*a47a12beSStefan Roese */ 85*a47a12beSStefan Roese void timer_interrupt_cpu(struct pt_regs *regs) 86*a47a12beSStefan Roese { 87*a47a12beSStefan Roese /* nothing to do here */ 88*a47a12beSStefan Roese } 89*a47a12beSStefan Roese 90*a47a12beSStefan Roese /* 91*a47a12beSStefan Roese * Install and free a interrupt handler. Not implemented yet. 92*a47a12beSStefan Roese */ 93*a47a12beSStefan Roese void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) 94*a47a12beSStefan Roese { 95*a47a12beSStefan Roese } 96*a47a12beSStefan Roese 97*a47a12beSStefan Roese void irq_free_handler(int vec) 98*a47a12beSStefan Roese { 99*a47a12beSStefan Roese } 100*a47a12beSStefan Roese 101*a47a12beSStefan Roese /* 102*a47a12beSStefan Roese * irqinfo - print information about PCI devices,not implemented. 103*a47a12beSStefan Roese */ 104*a47a12beSStefan Roese int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) 105*a47a12beSStefan Roese { 106*a47a12beSStefan Roese return 0; 107*a47a12beSStefan Roese } 108*a47a12beSStefan Roese 109*a47a12beSStefan Roese /* 110*a47a12beSStefan Roese * Handle external interrupts 111*a47a12beSStefan Roese */ 112*a47a12beSStefan Roese void external_interrupt(struct pt_regs *regs) 113*a47a12beSStefan Roese { 114*a47a12beSStefan Roese puts("external_interrupt (oops!)\n"); 115*a47a12beSStefan Roese } 116