1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * (C) Copyright 2000-2002 3a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4a47a12beSStefan Roese * 5a47a12beSStefan Roese * (C) Copyright 2002 (440 port) 6a47a12beSStefan Roese * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com 7a47a12beSStefan Roese * 8a47a12beSStefan Roese * (C) Copyright 2003 Motorola Inc. (MPC85xx port) 9a47a12beSStefan Roese * Xianghua Xiao (X.Xiao@motorola.com) 10a47a12beSStefan Roese * 11a47a12beSStefan Roese * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port) 12a47a12beSStefan Roese * Jeff Brown 13a47a12beSStefan Roese * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 14a47a12beSStefan Roese * 151a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 16a47a12beSStefan Roese */ 17a47a12beSStefan Roese 18a47a12beSStefan Roese #include <common.h> 19a47a12beSStefan Roese #include <mpc86xx.h> 20a47a12beSStefan Roese #include <command.h> 21a47a12beSStefan Roese #include <asm/processor.h> 22cc1dd33fSJohn Schmoller #ifdef CONFIG_POST 23cc1dd33fSJohn Schmoller #include <post.h> 24cc1dd33fSJohn Schmoller #endif 25a47a12beSStefan Roese 26*08dd988bSChristophe Leroy int interrupt_init_cpu(unsigned *decrementer_count) 27a47a12beSStefan Roese { 28a47a12beSStefan Roese volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 29a47a12beSStefan Roese volatile ccsr_pic_t *pic = &immr->im_pic; 30a47a12beSStefan Roese 31cc1dd33fSJohn Schmoller #ifdef CONFIG_POST 32cc1dd33fSJohn Schmoller /* 33cc1dd33fSJohn Schmoller * The POST word is stored in the PIC's TFRR register which gets 34cc1dd33fSJohn Schmoller * cleared when the PIC is reset. Save it off so we can restore it 35cc1dd33fSJohn Schmoller * later. 36cc1dd33fSJohn Schmoller */ 37cc1dd33fSJohn Schmoller ulong post_word = post_word_load(); 38cc1dd33fSJohn Schmoller #endif 39cc1dd33fSJohn Schmoller 40a47a12beSStefan Roese pic->gcr = MPC86xx_PICGCR_RST; 41a47a12beSStefan Roese while (pic->gcr & MPC86xx_PICGCR_RST) 42a47a12beSStefan Roese ; 43a47a12beSStefan Roese pic->gcr = MPC86xx_PICGCR_MODE; 44a47a12beSStefan Roese 45a47a12beSStefan Roese *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; 46*08dd988bSChristophe Leroy debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n", 47a47a12beSStefan Roese (get_tbclk() / 1000000), 48a47a12beSStefan Roese *decrementer_count); 49a47a12beSStefan Roese 50a47a12beSStefan Roese #ifdef CONFIG_INTERRUPTS 51a47a12beSStefan Roese 52a47a12beSStefan Roese pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */ 537f2229b5SMarek Vasut debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1); 54a47a12beSStefan Roese 55a47a12beSStefan Roese pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ 567f2229b5SMarek Vasut debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2); 57a47a12beSStefan Roese 58a47a12beSStefan Roese pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ 597f2229b5SMarek Vasut debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3); 60a47a12beSStefan Roese 61a47a12beSStefan Roese #if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1) 62a47a12beSStefan Roese pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */ 637f2229b5SMarek Vasut debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8); 64a47a12beSStefan Roese #endif 65a47a12beSStefan Roese #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) 66a47a12beSStefan Roese pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */ 677f2229b5SMarek Vasut debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9); 68a47a12beSStefan Roese #endif 69a47a12beSStefan Roese 70a47a12beSStefan Roese pic->ctpr = 0; /* 40080 clear current task priority register */ 71a47a12beSStefan Roese #endif 72a47a12beSStefan Roese 73cc1dd33fSJohn Schmoller #ifdef CONFIG_POST 74cc1dd33fSJohn Schmoller post_word_store(post_word); 75cc1dd33fSJohn Schmoller #endif 76cc1dd33fSJohn Schmoller 77a47a12beSStefan Roese return 0; 78a47a12beSStefan Roese } 79a47a12beSStefan Roese 80a47a12beSStefan Roese /* 81a47a12beSStefan Roese * timer_interrupt - gets called when the decrementer overflows, 82a47a12beSStefan Roese * with interrupts disabled. 83a47a12beSStefan Roese * Trivial implementation - no need to be really accurate. 84a47a12beSStefan Roese */ 85a47a12beSStefan Roese void timer_interrupt_cpu(struct pt_regs *regs) 86a47a12beSStefan Roese { 87a47a12beSStefan Roese /* nothing to do here */ 88a47a12beSStefan Roese } 89a47a12beSStefan Roese 90a47a12beSStefan Roese /* 91a47a12beSStefan Roese * Install and free a interrupt handler. Not implemented yet. 92a47a12beSStefan Roese */ 93a47a12beSStefan Roese void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) 94a47a12beSStefan Roese { 95a47a12beSStefan Roese } 96a47a12beSStefan Roese 97a47a12beSStefan Roese void irq_free_handler(int vec) 98a47a12beSStefan Roese { 99a47a12beSStefan Roese } 100a47a12beSStefan Roese 101a47a12beSStefan Roese /* 102a47a12beSStefan Roese * irqinfo - print information about PCI devices,not implemented. 103a47a12beSStefan Roese */ 10454841ab5SWolfgang Denk int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 105a47a12beSStefan Roese { 106a47a12beSStefan Roese return 0; 107a47a12beSStefan Roese } 108a47a12beSStefan Roese 109a47a12beSStefan Roese /* 110a47a12beSStefan Roese * Handle external interrupts 111a47a12beSStefan Roese */ 112a47a12beSStefan Roese void external_interrupt(struct pt_regs *regs) 113a47a12beSStefan Roese { 114a47a12beSStefan Roese puts("external_interrupt (oops!)\n"); 115a47a12beSStefan Roese } 116