xref: /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/u-boot.lds (revision a47a12becf66f02a56da91c161e2edb625e9f20c)
1*a47a12beSStefan Roese/*
2*a47a12beSStefan Roese * Copyright 2007-2009 Freescale Semiconductor, Inc.
3*a47a12beSStefan Roese *
4*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this
5*a47a12beSStefan Roese * project.
6*a47a12beSStefan Roese *
7*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or
8*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as
9*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of
10*a47a12beSStefan Roese * the License, or (at your option) any later version.
11*a47a12beSStefan Roese *
12*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful,
13*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of
14*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15*a47a12beSStefan Roese * GNU General Public License for more details.
16*a47a12beSStefan Roese *
17*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License
18*a47a12beSStefan Roese * along with this program; if not, write to the Free Software
19*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20*a47a12beSStefan Roese * MA 02111-1307 USA
21*a47a12beSStefan Roese */
22*a47a12beSStefan Roese
23*a47a12beSStefan Roese#ifndef RESET_VECTOR_ADDRESS
24*a47a12beSStefan Roese#define RESET_VECTOR_ADDRESS	0xfffffffc
25*a47a12beSStefan Roese#endif
26*a47a12beSStefan Roese
27*a47a12beSStefan RoeseOUTPUT_ARCH(powerpc)
28*a47a12beSStefan Roese/* Do we need any of these for elf?
29*a47a12beSStefan Roese   __DYNAMIC = 0;    */
30*a47a12beSStefan RoesePHDRS
31*a47a12beSStefan Roese{
32*a47a12beSStefan Roese  text PT_LOAD;
33*a47a12beSStefan Roese  bss PT_LOAD;
34*a47a12beSStefan Roese}
35*a47a12beSStefan Roese
36*a47a12beSStefan RoeseSECTIONS
37*a47a12beSStefan Roese{
38*a47a12beSStefan Roese  /* Read-only sections, merged into text segment: */
39*a47a12beSStefan Roese  . = + SIZEOF_HEADERS;
40*a47a12beSStefan Roese  .interp : { *(.interp) }
41*a47a12beSStefan Roese  .hash          : { *(.hash)		}
42*a47a12beSStefan Roese  .dynsym        : { *(.dynsym)		}
43*a47a12beSStefan Roese  .dynstr        : { *(.dynstr)		}
44*a47a12beSStefan Roese  .rel.text      : { *(.rel.text)		}
45*a47a12beSStefan Roese  .rela.text     : { *(.rela.text)	}
46*a47a12beSStefan Roese  .rel.data      : { *(.rel.data)		}
47*a47a12beSStefan Roese  .rela.data     : { *(.rela.data)	}
48*a47a12beSStefan Roese  .rel.rodata    : { *(.rel.rodata)	}
49*a47a12beSStefan Roese  .rela.rodata   : { *(.rela.rodata)	}
50*a47a12beSStefan Roese  .rel.got       : { *(.rel.got)		}
51*a47a12beSStefan Roese  .rela.got      : { *(.rela.got)		}
52*a47a12beSStefan Roese  .rel.ctors     : { *(.rel.ctors)	}
53*a47a12beSStefan Roese  .rela.ctors    : { *(.rela.ctors)	}
54*a47a12beSStefan Roese  .rel.dtors     : { *(.rel.dtors)	}
55*a47a12beSStefan Roese  .rela.dtors    : { *(.rela.dtors)	}
56*a47a12beSStefan Roese  .rel.bss       : { *(.rel.bss)		}
57*a47a12beSStefan Roese  .rela.bss      : { *(.rela.bss)		}
58*a47a12beSStefan Roese  .rel.plt       : { *(.rel.plt)		}
59*a47a12beSStefan Roese  .rela.plt      : { *(.rela.plt)		}
60*a47a12beSStefan Roese  .init          : { *(.init)	}
61*a47a12beSStefan Roese  .plt : { *(.plt) }
62*a47a12beSStefan Roese  .text      :
63*a47a12beSStefan Roese  {
64*a47a12beSStefan Roese    *(.text)
65*a47a12beSStefan Roese    *(.got1)
66*a47a12beSStefan Roese   } :text
67*a47a12beSStefan Roese    _etext = .;
68*a47a12beSStefan Roese    PROVIDE (etext = .);
69*a47a12beSStefan Roese    .rodata    :
70*a47a12beSStefan Roese   {
71*a47a12beSStefan Roese    *(.eh_frame)
72*a47a12beSStefan Roese    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
73*a47a12beSStefan Roese  } :text
74*a47a12beSStefan Roese  .fini      : { *(.fini)    } =0
75*a47a12beSStefan Roese  .ctors     : { *(.ctors)   }
76*a47a12beSStefan Roese  .dtors     : { *(.dtors)   }
77*a47a12beSStefan Roese
78*a47a12beSStefan Roese  /* Read-write section, merged into data segment: */
79*a47a12beSStefan Roese  . = (. + 0x00FF) & 0xFFFFFF00;
80*a47a12beSStefan Roese  _erotext = .;
81*a47a12beSStefan Roese  PROVIDE (erotext = .);
82*a47a12beSStefan Roese  .reloc   :
83*a47a12beSStefan Roese  {
84*a47a12beSStefan Roese    *(.got)
85*a47a12beSStefan Roese    _GOT2_TABLE_ = .;
86*a47a12beSStefan Roese    *(.got2)
87*a47a12beSStefan Roese    _FIXUP_TABLE_ = .;
88*a47a12beSStefan Roese    *(.fixup)
89*a47a12beSStefan Roese  }
90*a47a12beSStefan Roese  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
91*a47a12beSStefan Roese  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
92*a47a12beSStefan Roese
93*a47a12beSStefan Roese  .data    :
94*a47a12beSStefan Roese  {
95*a47a12beSStefan Roese    *(.data)
96*a47a12beSStefan Roese    *(.data1)
97*a47a12beSStefan Roese    *(.sdata)
98*a47a12beSStefan Roese    *(.sdata2)
99*a47a12beSStefan Roese    *(.dynamic)
100*a47a12beSStefan Roese    CONSTRUCTORS
101*a47a12beSStefan Roese  }
102*a47a12beSStefan Roese  _edata  =  .;
103*a47a12beSStefan Roese  PROVIDE (edata = .);
104*a47a12beSStefan Roese
105*a47a12beSStefan Roese  . = .;
106*a47a12beSStefan Roese  __u_boot_cmd_start = .;
107*a47a12beSStefan Roese  .u_boot_cmd : { *(.u_boot_cmd) }
108*a47a12beSStefan Roese  __u_boot_cmd_end = .;
109*a47a12beSStefan Roese
110*a47a12beSStefan Roese  . = .;
111*a47a12beSStefan Roese  __start___ex_table = .;
112*a47a12beSStefan Roese  __ex_table : { *(__ex_table) }
113*a47a12beSStefan Roese  __stop___ex_table = .;
114*a47a12beSStefan Roese
115*a47a12beSStefan Roese  . = ALIGN(256);
116*a47a12beSStefan Roese  __init_begin = .;
117*a47a12beSStefan Roese  .text.init : { *(.text.init) }
118*a47a12beSStefan Roese  .data.init : { *(.data.init) }
119*a47a12beSStefan Roese  . = ALIGN(256);
120*a47a12beSStefan Roese  __init_end = .;
121*a47a12beSStefan Roese
122*a47a12beSStefan Roese  .bootpg RESET_VECTOR_ADDRESS - 0xffc :
123*a47a12beSStefan Roese  {
124*a47a12beSStefan Roese    arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
125*a47a12beSStefan Roese  } :text = 0xffff
126*a47a12beSStefan Roese
127*a47a12beSStefan Roese  .resetvec RESET_VECTOR_ADDRESS :
128*a47a12beSStefan Roese  {
129*a47a12beSStefan Roese    *(.resetvec)
130*a47a12beSStefan Roese  } :text = 0xffff
131*a47a12beSStefan Roese
132*a47a12beSStefan Roese  . = RESET_VECTOR_ADDRESS + 0x4;
133*a47a12beSStefan Roese
134*a47a12beSStefan Roese  /*
135*a47a12beSStefan Roese   * Make sure that the bss segment isn't linked at 0x0, otherwise its
136*a47a12beSStefan Roese   * address won't be updated during relocation fixups.  Note that
137*a47a12beSStefan Roese   * this is a temporary fix.  Code to dynamically the fixup the bss
138*a47a12beSStefan Roese   * location will be added in the future.  When the bss relocation
139*a47a12beSStefan Roese   * fixup code is present this workaround should be removed.
140*a47a12beSStefan Roese   */
141*a47a12beSStefan Roese#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
142*a47a12beSStefan Roese  . |= 0x10;
143*a47a12beSStefan Roese#endif
144*a47a12beSStefan Roese
145*a47a12beSStefan Roese  __bss_start = .;
146*a47a12beSStefan Roese  .bss (NOLOAD)       :
147*a47a12beSStefan Roese  {
148*a47a12beSStefan Roese   *(.sbss) *(.scommon)
149*a47a12beSStefan Roese   *(.dynbss)
150*a47a12beSStefan Roese   *(.bss)
151*a47a12beSStefan Roese   *(COMMON)
152*a47a12beSStefan Roese  } :bss
153*a47a12beSStefan Roese
154*a47a12beSStefan Roese  . = ALIGN(4);
155*a47a12beSStefan Roese  _end = . ;
156*a47a12beSStefan Roese  PROVIDE (end = .);
157*a47a12beSStefan Roese}
158