1/* 2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. 3 * Copyright (C) 2003 Motorola,Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 9 * 10 * The processor starts at 0xfffffffc and the code is first executed in the 11 * last 4K page(0xfffff000-0xffffffff) in flash/rom. 12 * 13 */ 14 15#include <asm-offsets.h> 16#include <config.h> 17#include <mpc85xx.h> 18#include <version.h> 19 20#include <ppc_asm.tmpl> 21#include <ppc_defs.h> 22 23#include <asm/cache.h> 24#include <asm/mmu.h> 25 26#undef MSR_KERNEL 27#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 28 29#if defined(CONFIG_NAND_SPL) || \ 30 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) 31#define MINIMAL_SPL 32#endif 33 34#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \ 35 !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 36#define NOR_BOOT 37#endif 38 39/* 40 * Set up GOT: Global Offset Table 41 * 42 * Use r12 to access the GOT 43 */ 44 START_GOT 45 GOT_ENTRY(_GOT2_TABLE_) 46 GOT_ENTRY(_FIXUP_TABLE_) 47 48#ifndef MINIMAL_SPL 49 GOT_ENTRY(_start) 50 GOT_ENTRY(_start_of_vectors) 51 GOT_ENTRY(_end_of_vectors) 52 GOT_ENTRY(transfer_to_handler) 53#endif 54 55 GOT_ENTRY(__init_end) 56 GOT_ENTRY(__bss_end) 57 GOT_ENTRY(__bss_start) 58 END_GOT 59 60/* 61 * e500 Startup -- after reset only the last 4KB of the effective 62 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 63 * section is located at THIS LAST page and basically does three 64 * things: clear some registers, set up exception tables and 65 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 66 * continue the boot procedure. 67 68 * Once the boot rom is mapped by TLB entries we can proceed 69 * with normal startup. 70 * 71 */ 72 73 .section .bootpg,"ax" 74 .globl _start_e500 75 76_start_e500: 77/* Enable debug exception */ 78 li r1,MSR_DE 79 mtmsr r1 80 81 /* 82 * If we got an ePAPR device tree pointer passed in as r3, we need that 83 * later in cpu_init_early_f(). Save it to a safe register before we 84 * clobber it so that we can fetch it from there later. 85 */ 86 mr r24, r3 87 88#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 89 mfspr r3,SPRN_SVR 90 rlwinm r3,r3,0,0xff 91 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 92 cmpw r3,r4 93 beq 1f 94 95#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 96 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 97 cmpw r3,r4 98 beq 1f 99#endif 100 101 /* Not a supported revision affected by erratum */ 102 li r27,0 103 b 2f 104 1051: li r27,1 /* Remember for later that we have the erratum */ 106 /* Erratum says set bits 55:60 to 001001 */ 107 msync 108 isync 109 mfspr r3,SPRN_HDBCR0 110 li r4,0x48 111 rlwimi r3,r4,0,0x1f8 112 mtspr SPRN_HDBCR0,r3 113 isync 1142: 115#endif 116#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 117 msync 118 isync 119 mfspr r3, SPRN_HDBCR0 120 oris r3, r3, 0x0080 121 mtspr SPRN_HDBCR0, r3 122#endif 123 124 125#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) 126 /* ISBC uses L2 as stack. 127 * Disable L2 cache here so that u-boot can enable it later 128 * as part of it's normal flow 129 */ 130 131 /* Check if L2 is enabled */ 132 mfspr r3, SPRN_L2CSR0 133 lis r2, L2CSR0_L2E@h 134 ori r2, r2, L2CSR0_L2E@l 135 and. r4, r3, r2 136 beq l2_disabled 137 138 mfspr r3, SPRN_L2CSR0 139 /* Flush L2 cache */ 140 lis r2,(L2CSR0_L2FL)@h 141 ori r2, r2, (L2CSR0_L2FL)@l 142 or r3, r2, r3 143 sync 144 isync 145 mtspr SPRN_L2CSR0,r3 146 isync 1471: 148 mfspr r3, SPRN_L2CSR0 149 and. r1, r3, r2 150 bne 1b 151 152 mfspr r3, SPRN_L2CSR0 153 lis r2, L2CSR0_L2E@h 154 ori r2, r2, L2CSR0_L2E@l 155 andc r4, r3, r2 156 sync 157 isync 158 mtspr SPRN_L2CSR0,r4 159 isync 160 161l2_disabled: 162#endif 163 164/* clear registers/arrays not reset by hardware */ 165 166 /* L1 */ 167 li r0,2 168 mtspr L1CSR0,r0 /* invalidate d-cache */ 169 mtspr L1CSR1,r0 /* invalidate i-cache */ 170 171 mfspr r1,DBSR 172 mtspr DBSR,r1 /* Clear all valid bits */ 173 174 175 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch 176 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h 177 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l 178 mtspr MAS0, \scratch 179 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h 180 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l 181 mtspr MAS1, \scratch 182 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h 183 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l 184 mtspr MAS2, \scratch 185 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h 186 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l 187 mtspr MAS3, \scratch 188 lis \scratch, \phy_high@h 189 ori \scratch, \scratch, \phy_high@l 190 mtspr MAS7, \scratch 191 isync 192 msync 193 tlbwe 194 isync 195 .endm 196 197 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch 198 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h 199 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l 200 mtspr MAS0, \scratch 201 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h 202 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l 203 mtspr MAS1, \scratch 204 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h 205 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l 206 mtspr MAS2, \scratch 207 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h 208 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l 209 mtspr MAS3, \scratch 210 lis \scratch, \phy_high@h 211 ori \scratch, \scratch, \phy_high@l 212 mtspr MAS7, \scratch 213 isync 214 msync 215 tlbwe 216 isync 217 .endm 218 219 .macro delete_tlb1_entry esel scratch 220 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h 221 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l 222 mtspr MAS0, \scratch 223 li \scratch, 0 224 mtspr MAS1, \scratch 225 isync 226 msync 227 tlbwe 228 isync 229 .endm 230 231 .macro delete_tlb0_entry esel epn wimg scratch 232 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h 233 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l 234 mtspr MAS0, \scratch 235 li \scratch, 0 236 mtspr MAS1, \scratch 237 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h 238 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l 239 mtspr MAS2, \scratch 240 isync 241 msync 242 tlbwe 243 isync 244 .endm 245 246/* Interrupt vectors do not fit in minimal SPL. */ 247#if !defined(MINIMAL_SPL) 248 /* Setup interrupt vectors */ 249 lis r1,CONFIG_SYS_MONITOR_BASE@h 250 mtspr IVPR,r1 251 252 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h 253 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l 254 255 addi r4,r3,CriticalInput - _start + _START_OFFSET 256 mtspr IVOR0,r4 /* 0: Critical input */ 257 addi r4,r3,MachineCheck - _start + _START_OFFSET 258 mtspr IVOR1,r4 /* 1: Machine check */ 259 addi r4,r3,DataStorage - _start + _START_OFFSET 260 mtspr IVOR2,r4 /* 2: Data storage */ 261 addi r4,r3,InstStorage - _start + _START_OFFSET 262 mtspr IVOR3,r4 /* 3: Instruction storage */ 263 addi r4,r3,ExtInterrupt - _start + _START_OFFSET 264 mtspr IVOR4,r4 /* 4: External interrupt */ 265 addi r4,r3,Alignment - _start + _START_OFFSET 266 mtspr IVOR5,r4 /* 5: Alignment */ 267 addi r4,r3,ProgramCheck - _start + _START_OFFSET 268 mtspr IVOR6,r4 /* 6: Program check */ 269 addi r4,r3,FPUnavailable - _start + _START_OFFSET 270 mtspr IVOR7,r4 /* 7: floating point unavailable */ 271 addi r4,r3,SystemCall - _start + _START_OFFSET 272 mtspr IVOR8,r4 /* 8: System call */ 273 /* 9: Auxiliary processor unavailable(unsupported) */ 274 addi r4,r3,Decrementer - _start + _START_OFFSET 275 mtspr IVOR10,r4 /* 10: Decrementer */ 276 addi r4,r3,IntervalTimer - _start + _START_OFFSET 277 mtspr IVOR11,r4 /* 11: Interval timer */ 278 addi r4,r3,WatchdogTimer - _start + _START_OFFSET 279 mtspr IVOR12,r4 /* 12: Watchdog timer */ 280 addi r4,r3,DataTLBError - _start + _START_OFFSET 281 mtspr IVOR13,r4 /* 13: Data TLB error */ 282 addi r4,r3,InstructionTLBError - _start + _START_OFFSET 283 mtspr IVOR14,r4 /* 14: Instruction TLB error */ 284 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET 285 mtspr IVOR15,r4 /* 15: Debug */ 286#endif 287 288 /* Clear and set up some registers. */ 289 li r0,0x0000 290 lis r1,0xffff 291 mtspr DEC,r0 /* prevent dec exceptions */ 292 mttbl r0 /* prevent fit & wdt exceptions */ 293 mttbu r0 294 mtspr TSR,r1 /* clear all timer exception status */ 295 mtspr TCR,r0 /* disable all */ 296 mtspr ESR,r0 /* clear exception syndrome register */ 297 mtspr MCSR,r0 /* machine check syndrome register */ 298 mtxer r0 /* clear integer exception register */ 299 300#ifdef CONFIG_SYS_BOOK3E_HV 301 mtspr MAS8,r0 /* make sure MAS8 is clear */ 302#endif 303 304 /* Enable Time Base and Select Time Base Clock */ 305 lis r0,HID0_EMCP@h /* Enable machine check */ 306#if defined(CONFIG_ENABLE_36BIT_PHYS) 307 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 308#endif 309#ifndef CONFIG_E500MC 310 ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 311#endif 312 mtspr HID0,r0 313 314#ifndef CONFIG_E500MC 315 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 316 mfspr r3,PVR 317 andi. r3,r3, 0xff 318 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 319 blt 1f 320 /* Set MBDD bit also */ 321 ori r0, r0, HID1_MBDD@l 3221: 323 mtspr HID1,r0 324#endif 325 326#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 327 mfspr r3,SPRN_HDBCR1 328 oris r3,r3,0x0100 329 mtspr SPRN_HDBCR1,r3 330#endif 331 332 /* Enable Branch Prediction */ 333#if defined(CONFIG_BTB) 334 lis r0,BUCSR_ENABLE@h 335 ori r0,r0,BUCSR_ENABLE@l 336 mtspr SPRN_BUCSR,r0 337#endif 338 339#if defined(CONFIG_SYS_INIT_DBCR) 340 lis r1,0xffff 341 ori r1,r1,0xffff 342 mtspr DBSR,r1 /* Clear all status bits */ 343 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 344 ori r0,r0,CONFIG_SYS_INIT_DBCR@l 345 mtspr DBCR0,r0 346#endif 347 348#ifdef CONFIG_MPC8569 349#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 350#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 351 352 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 353 * use address space which is more than 12bits, and it must be done in 354 * the 4K boot page. So we set this bit here. 355 */ 356 357 /* create a temp mapping TLB0[0] for LBCR */ 358 create_tlb0_entry 0, \ 359 0, BOOKE_PAGESZ_4K, \ 360 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \ 361 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \ 362 0, r6 363 364 /* Set LBCR register */ 365 lis r4,CONFIG_SYS_LBCR_ADDR@h 366 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 367 368 lis r5,CONFIG_SYS_LBC_LBCR@h 369 ori r5,r5,CONFIG_SYS_LBC_LBCR@l 370 stw r5,0(r4) 371 isync 372 373 /* invalidate this temp TLB */ 374 lis r4,CONFIG_SYS_LBC_ADDR@h 375 ori r4,r4,CONFIG_SYS_LBC_ADDR@l 376 tlbivax 0,r4 377 isync 378 379#endif /* CONFIG_MPC8569 */ 380 381/* 382 * Search for the TLB that covers the code we're executing, and shrink it 383 * so that it covers only this 4K page. That will ensure that any other 384 * TLB we create won't interfere with it. We assume that the TLB exists, 385 * which is why we don't check the Valid bit of MAS1. We also assume 386 * it is in TLB1. 387 * 388 * This is necessary, for example, when booting from the on-chip ROM, 389 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. 390 */ 391 bl nexti /* Find our address */ 392nexti: mflr r1 /* R1 = our PC */ 393 li r2, 0 394 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ 395 isync 396 msync 397 tlbsx 0, r1 /* This must succeed */ 398 399 mfspr r14, MAS0 /* Save ESEL for later */ 400 rlwinm r14, r14, 16, 0xfff 401 402 /* Set the size of the TLB to 4KB */ 403 mfspr r3, MAS1 404 li r2, 0xF80 405 andc r3, r3, r2 /* Clear the TSIZE bits */ 406 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l 407 oris r3, r3, MAS1_IPROT@h 408 mtspr MAS1, r3 409 410 /* 411 * Set the base address of the TLB to our PC. We assume that 412 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. 413 */ 414 lis r3, MAS2_EPN@h 415 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ 416 417 and r1, r1, r3 /* Our PC, rounded down to the nearest page */ 418 419 mfspr r2, MAS2 420 andc r2, r2, r3 421 or r2, r2, r1 422#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 423 cmpwi r27,0 424 beq 1f 425 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */ 426 rlwinm r2, r2, 0, ~MAS2_I 427 ori r2, r2, MAS2_G 4281: 429#endif 430 mtspr MAS2, r2 /* Set the EPN to our PC base address */ 431 432 mfspr r2, MAS3 433 andc r2, r2, r3 434 or r2, r2, r1 435 mtspr MAS3, r2 /* Set the RPN to our PC base address */ 436 437 isync 438 msync 439 tlbwe 440 441/* 442 * Clear out any other TLB entries that may exist, to avoid conflicts. 443 * Our TLB entry is in r14. 444 */ 445 li r0, TLBIVAX_ALL | TLBIVAX_TLB0 446 tlbivax 0, r0 447 tlbsync 448 449 mfspr r4, SPRN_TLB1CFG 450 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK 451 452 li r3, 0 453 mtspr MAS1, r3 4541: cmpw r3, r14 455 rlwinm r5, r3, 16, MAS0_ESEL_MSK 456 addi r3, r3, 1 457 beq 2f /* skip the entry we're executing from */ 458 459 oris r5, r5, MAS0_TLBSEL(1)@h 460 mtspr MAS0, r5 461 462 isync 463 tlbwe 464 isync 465 msync 466 4672: cmpw r3, r4 468 blt 1b 469 470#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \ 471 !defined(CONFIG_SECURE_BOOT) 472/* 473 * TLB entry for debuggging in AS1 474 * Create temporary TLB entry in AS0 to handle debug exception 475 * As on debug exception MSR is cleared i.e. Address space is changed 476 * to 0. A TLB entry (in AS0) is required to handle debug exception generated 477 * in AS1. 478 */ 479 480#ifdef NOR_BOOT 481/* 482 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 483 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. 484 * and this window is outside of 4K boot window. 485 */ 486 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ 487 0, BOOKE_PAGESZ_4M, \ 488 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ 489 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 490 0, r6 491 492#else 493/* 494 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 495 * because "nexti" will resize TLB to 4K 496 */ 497 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ 498 0, BOOKE_PAGESZ_256K, \ 499 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \ 500 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \ 501 0, r6 502#endif 503#endif 504 505/* 506 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default 507 * location is not where we want it. This typically happens on a 36-bit 508 * system, where we want to move CCSR to near the top of 36-bit address space. 509 * 510 * To move CCSR, we create two temporary TLBs, one for the old location, and 511 * another for the new location. On CoreNet systems, we also need to create 512 * a special, temporary LAW. 513 * 514 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for 515 * long-term TLBs, so we use TLB0 here. 516 */ 517#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) 518 519#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) 520#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." 521#endif 522 523create_ccsr_new_tlb: 524 /* 525 * Create a TLB for the new location of CCSR. Register R8 is reserved 526 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). 527 */ 528 lis r8, CONFIG_SYS_CCSRBAR@h 529 ori r8, r8, CONFIG_SYS_CCSRBAR@l 530 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h 531 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l 532 create_tlb0_entry 0, \ 533 0, BOOKE_PAGESZ_4K, \ 534 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ 535 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ 536 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 537 /* 538 * Create a TLB for the current location of CCSR. Register R9 is reserved 539 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). 540 */ 541create_ccsr_old_tlb: 542 create_tlb0_entry 1, \ 543 0, BOOKE_PAGESZ_4K, \ 544 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ 545 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ 546 0, r3 /* The default CCSR address is always a 32-bit number */ 547 548 549 /* 550 * We have a TLB for what we think is the current (old) CCSR. Let's 551 * verify that, otherwise we won't be able to move it. 552 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only 553 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. 554 */ 555verify_old_ccsr: 556 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h 557 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l 558#ifdef CONFIG_FSL_CORENET 559 lwz r1, 4(r9) /* CCSRBARL */ 560#else 561 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ 562 slwi r1, r1, 12 563#endif 564 565 cmpl 0, r0, r1 566 567 /* 568 * If the value we read from CCSRBARL is not what we expect, then 569 * enter an infinite loop. This will at least allow a debugger to 570 * halt execution and examine TLBs, etc. There's no point in going 571 * on. 572 */ 573infinite_debug_loop: 574 bne infinite_debug_loop 575 576#ifdef CONFIG_FSL_CORENET 577 578#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 579#define LAW_EN 0x80000000 580#define LAW_SIZE_4K 0xb 581#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) 582#define CCSRAR_C 0x80000000 /* Commit */ 583 584create_temp_law: 585 /* 586 * On CoreNet systems, we create the temporary LAW using a special LAW 587 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. 588 */ 589 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 590 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 591 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 592 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 593 lis r2, CCSRBAR_LAWAR@h 594 ori r2, r2, CCSRBAR_LAWAR@l 595 596 stw r0, 0xc00(r9) /* LAWBARH0 */ 597 stw r1, 0xc04(r9) /* LAWBARL0 */ 598 sync 599 stw r2, 0xc08(r9) /* LAWAR0 */ 600 601 /* 602 * Read back from LAWAR to ensure the update is complete. e500mc 603 * cores also require an isync. 604 */ 605 lwz r0, 0xc08(r9) /* LAWAR0 */ 606 isync 607 608 /* 609 * Read the current CCSRBARH and CCSRBARL using load word instructions. 610 * Follow this with an isync instruction. This forces any outstanding 611 * accesses to configuration space to completion. 612 */ 613read_old_ccsrbar: 614 lwz r0, 0(r9) /* CCSRBARH */ 615 lwz r0, 4(r9) /* CCSRBARL */ 616 isync 617 618 /* 619 * Write the new values for CCSRBARH and CCSRBARL to their old 620 * locations. The CCSRBARH has a shadow register. When the CCSRBARH 621 * has a new value written it loads a CCSRBARH shadow register. When 622 * the CCSRBARL is written, the CCSRBARH shadow register contents 623 * along with the CCSRBARL value are loaded into the CCSRBARH and 624 * CCSRBARL registers, respectively. Follow this with a sync 625 * instruction. 626 */ 627write_new_ccsrbar: 628 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 629 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 630 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 631 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 632 lis r2, CCSRAR_C@h 633 ori r2, r2, CCSRAR_C@l 634 635 stw r0, 0(r9) /* Write to CCSRBARH */ 636 sync /* Make sure we write to CCSRBARH first */ 637 stw r1, 4(r9) /* Write to CCSRBARL */ 638 sync 639 640 /* 641 * Write a 1 to the commit bit (C) of CCSRAR at the old location. 642 * Follow this with a sync instruction. 643 */ 644 stw r2, 8(r9) 645 sync 646 647 /* Delete the temporary LAW */ 648delete_temp_law: 649 li r1, 0 650 stw r1, 0xc08(r8) 651 sync 652 stw r1, 0xc00(r8) 653 stw r1, 0xc04(r8) 654 sync 655 656#else /* #ifdef CONFIG_FSL_CORENET */ 657 658write_new_ccsrbar: 659 /* 660 * Read the current value of CCSRBAR using a load word instruction 661 * followed by an isync. This forces all accesses to configuration 662 * space to complete. 663 */ 664 sync 665 lwz r0, 0(r9) 666 isync 667 668/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ 669#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ 670 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) 671 672 /* Write the new value to CCSRBAR. */ 673 lis r0, CCSRBAR_PHYS_RS12@h 674 ori r0, r0, CCSRBAR_PHYS_RS12@l 675 stw r0, 0(r9) 676 sync 677 678 /* 679 * The manual says to perform a load of an address that does not 680 * access configuration space or the on-chip SRAM using an existing TLB, 681 * but that doesn't appear to be necessary. We will do the isync, 682 * though. 683 */ 684 isync 685 686 /* 687 * Read the contents of CCSRBAR from its new location, followed by 688 * another isync. 689 */ 690 lwz r0, 0(r8) 691 isync 692 693#endif /* #ifdef CONFIG_FSL_CORENET */ 694 695 /* Delete the temporary TLBs */ 696delete_temp_tlbs: 697 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 698 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 699 700#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ 701 702#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 703create_ccsr_l2_tlb: 704 /* 705 * Create a TLB for the MMR location of CCSR 706 * to access L2CSR0 register 707 */ 708 create_tlb0_entry 0, \ 709 0, BOOKE_PAGESZ_4K, \ 710 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ 711 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ 712 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 713 714enable_l2_cluster_l2: 715 /* enable L2 cache */ 716 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h 717 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l 718 li r4, 33 /* stash id */ 719 stw r4, 4(r3) 720 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h 721 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l 722 sync 723 stw r4, 0(r3) /* invalidate L2 */ 7241: sync 725 lwz r0, 0(r3) 726 twi 0, r0, 0 727 isync 728 and. r1, r0, r4 729 bne 1b 730 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h 731 ori r4, r4, (L2CSR0_L2REP_MODE)@l 732 sync 733 stw r4, 0(r3) /* enable L2 */ 734delete_ccsr_l2_tlb: 735 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 736#endif 737 738 /* 739 * Enable the L1. On e6500, this has to be done 740 * after the L2 is up. 741 */ 742 743#ifdef CONFIG_SYS_CACHE_STASHING 744 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 745 li r2,(32 + 0) 746 mtspr L1CSR2,r2 747#endif 748 749 /* Enable/invalidate the I-Cache */ 750 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 751 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 752 mtspr SPRN_L1CSR1,r2 7531: 754 mfspr r3,SPRN_L1CSR1 755 and. r1,r3,r2 756 bne 1b 757 758 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 759 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 760 mtspr SPRN_L1CSR1,r3 761 isync 7622: 763 mfspr r3,SPRN_L1CSR1 764 andi. r1,r3,L1CSR1_ICE@l 765 beq 2b 766 767 /* Enable/invalidate the D-Cache */ 768 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 769 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 770 mtspr SPRN_L1CSR0,r2 7711: 772 mfspr r3,SPRN_L1CSR0 773 and. r1,r3,r2 774 bne 1b 775 776 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 777 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 778 mtspr SPRN_L1CSR0,r3 779 isync 7802: 781 mfspr r3,SPRN_L1CSR0 782 andi. r1,r3,L1CSR0_DCE@l 783 beq 2b 784#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 785#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 786#define LAW_SIZE_1M 0x13 787#define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M) 788 789 cmpwi r27,0 790 beq 9f 791 792 /* 793 * Create a TLB entry for CCSR 794 * 795 * We're executing out of TLB1 entry in r14, and that's the only 796 * TLB entry that exists. To allocate some TLB entries for our 797 * own use, flip a bit high enough that we won't flip it again 798 * via incrementing. 799 */ 800 801 xori r8, r14, 32 802 lis r0, MAS0_TLBSEL(1)@h 803 rlwimi r0, r8, 16, MAS0_ESEL_MSK 804 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h 805 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l 806 lis r7, CONFIG_SYS_CCSRBAR@h 807 ori r7, r7, CONFIG_SYS_CCSRBAR@l 808 ori r2, r7, MAS2_I|MAS2_G 809 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h 810 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l 811 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 812 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 813 mtspr MAS0, r0 814 mtspr MAS1, r1 815 mtspr MAS2, r2 816 mtspr MAS3, r3 817 mtspr MAS7, r4 818 isync 819 tlbwe 820 isync 821 msync 822 823 /* Map DCSR temporarily to physical address zero */ 824 li r0, 0 825 lis r3, DCSRBAR_LAWAR@h 826 ori r3, r3, DCSRBAR_LAWAR@l 827 828 stw r0, 0xc00(r7) /* LAWBARH0 */ 829 stw r0, 0xc04(r7) /* LAWBARL0 */ 830 sync 831 stw r3, 0xc08(r7) /* LAWAR0 */ 832 833 /* Read back from LAWAR to ensure the update is complete. */ 834 lwz r3, 0xc08(r7) /* LAWAR0 */ 835 isync 836 837 /* Create a TLB entry for DCSR at zero */ 838 839 addi r9, r8, 1 840 lis r0, MAS0_TLBSEL(1)@h 841 rlwimi r0, r9, 16, MAS0_ESEL_MSK 842 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h 843 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l 844 li r6, 0 /* DCSR effective address */ 845 ori r2, r6, MAS2_I|MAS2_G 846 li r3, MAS3_SW|MAS3_SR 847 li r4, 0 848 mtspr MAS0, r0 849 mtspr MAS1, r1 850 mtspr MAS2, r2 851 mtspr MAS3, r3 852 mtspr MAS7, r4 853 isync 854 tlbwe 855 isync 856 msync 857 858 /* enable the timebase */ 859#define CTBENR 0xe2084 860 li r3, 1 861 addis r4, r7, CTBENR@ha 862 stw r3, CTBENR@l(r4) 863 lwz r3, CTBENR@l(r4) 864 twi 0,r3,0 865 isync 866 867 .macro erratum_set_ccsr offset value 868 addis r3, r7, \offset@ha 869 lis r4, \value@h 870 addi r3, r3, \offset@l 871 ori r4, r4, \value@l 872 bl erratum_set_value 873 .endm 874 875 .macro erratum_set_dcsr offset value 876 addis r3, r6, \offset@ha 877 lis r4, \value@h 878 addi r3, r3, \offset@l 879 ori r4, r4, \value@l 880 bl erratum_set_value 881 .endm 882 883 erratum_set_dcsr 0xb0e08 0xe0201800 884 erratum_set_dcsr 0xb0e18 0xe0201800 885 erratum_set_dcsr 0xb0e38 0xe0400000 886 erratum_set_dcsr 0xb0008 0x00900000 887 erratum_set_dcsr 0xb0e40 0xe00a0000 888 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 889#ifdef CONFIG_RAMBOOT_PBL 890 erratum_set_ccsr 0x10f00 0x495e5000 891#else 892 erratum_set_ccsr 0x10f00 0x415e5000 893#endif 894 erratum_set_ccsr 0x11f00 0x415e5000 895 896 /* Make temp mapping uncacheable again, if it was initially */ 897 bl 2f 8982: mflr r3 899 tlbsx 0, r3 900 mfspr r4, MAS2 901 rlwimi r4, r15, 0, MAS2_I 902 rlwimi r4, r15, 0, MAS2_G 903 mtspr MAS2, r4 904 isync 905 tlbwe 906 isync 907 msync 908 909 /* Clear the cache */ 910 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 911 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 912 sync 913 isync 914 mtspr SPRN_L1CSR1,r3 915 isync 9162: sync 917 mfspr r4,SPRN_L1CSR1 918 and. r4,r4,r3 919 bne 2b 920 921 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 922 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 923 sync 924 isync 925 mtspr SPRN_L1CSR1,r3 926 isync 9272: sync 928 mfspr r4,SPRN_L1CSR1 929 and. r4,r4,r3 930 beq 2b 931 932 /* Remove temporary mappings */ 933 lis r0, MAS0_TLBSEL(1)@h 934 rlwimi r0, r9, 16, MAS0_ESEL_MSK 935 li r3, 0 936 mtspr MAS0, r0 937 mtspr MAS1, r3 938 isync 939 tlbwe 940 isync 941 msync 942 943 li r3, 0 944 stw r3, 0xc08(r7) /* LAWAR0 */ 945 lwz r3, 0xc08(r7) 946 isync 947 948 lis r0, MAS0_TLBSEL(1)@h 949 rlwimi r0, r8, 16, MAS0_ESEL_MSK 950 li r3, 0 951 mtspr MAS0, r0 952 mtspr MAS1, r3 953 isync 954 tlbwe 955 isync 956 msync 957 958 b 9f 959 960 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */ 961erratum_set_value: 962 /* Lock two cache lines into I-Cache */ 963 sync 964 mfspr r11, SPRN_L1CSR1 965 rlwinm r11, r11, 0, ~L1CSR1_ICUL 966 sync 967 isync 968 mtspr SPRN_L1CSR1, r11 969 isync 970 971 mflr r12 972 bl 5f 9735: mflr r5 974 addi r5, r5, 2f - 5b 975 icbtls 0, 0, r5 976 addi r5, r5, 64 977 978 sync 979 mfspr r11, SPRN_L1CSR1 9803: andi. r11, r11, L1CSR1_ICUL 981 bne 3b 982 983 icbtls 0, 0, r5 984 addi r5, r5, 64 985 986 sync 987 mfspr r11, SPRN_L1CSR1 9883: andi. r11, r11, L1CSR1_ICUL 989 bne 3b 990 991 b 2f 992 .align 6 993 /* Inside a locked cacheline, wait a while, write, then wait a while */ 9942: sync 995 996 mfspr r5, SPRN_TBRL 997 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ 9984: mfspr r5, SPRN_TBRL 999 subf. r5, r5, r11 1000 bgt 4b 1001 1002 stw r4, 0(r3) 1003 1004 mfspr r5, SPRN_TBRL 1005 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ 10064: mfspr r5, SPRN_TBRL 1007 subf. r5, r5, r11 1008 bgt 4b 1009 1010 sync 1011 1012 /* 1013 * Fill out the rest of this cache line and the next with nops, 1014 * to ensure that nothing outside the locked area will be 1015 * fetched due to a branch. 1016 */ 1017 .rept 19 1018 nop 1019 .endr 1020 1021 sync 1022 mfspr r11, SPRN_L1CSR1 1023 rlwinm r11, r11, 0, ~L1CSR1_ICUL 1024 sync 1025 isync 1026 mtspr SPRN_L1CSR1, r11 1027 isync 1028 1029 mtlr r12 1030 blr 1031 10329: 1033#endif 1034 1035create_init_ram_area: 1036 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 1037 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 1038 1039#ifdef NOR_BOOT 1040 /* create a temp mapping in AS=1 to the 4M boot window */ 1041 create_tlb1_entry 15, \ 1042 1, BOOKE_PAGESZ_4M, \ 1043 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ 1044 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 1045 0, r6 1046 1047#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 1048 /* create a temp mapping in AS = 1 for Flash mapping 1049 * created by PBL for ISBC code 1050 */ 1051 create_tlb1_entry 15, \ 1052 1, BOOKE_PAGESZ_1M, \ 1053 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ 1054 CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 1055 0, r6 1056#else 1057 /* 1058 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main 1059 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. 1060 */ 1061 create_tlb1_entry 15, \ 1062 1, BOOKE_PAGESZ_1M, \ 1063 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ 1064 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 1065 0, r6 1066#endif 1067 1068 /* create a temp mapping in AS=1 to the stack */ 1069#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ 1070 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) 1071 create_tlb1_entry 14, \ 1072 1, BOOKE_PAGESZ_16K, \ 1073 CONFIG_SYS_INIT_RAM_ADDR, 0, \ 1074 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ 1075 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 1076 1077#else 1078 create_tlb1_entry 14, \ 1079 1, BOOKE_PAGESZ_16K, \ 1080 CONFIG_SYS_INIT_RAM_ADDR, 0, \ 1081 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ 1082 0, r6 1083#endif 1084 1085 lis r6,MSR_IS|MSR_DS|MSR_DE@h 1086 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l 1087 lis r7,switch_as@h 1088 ori r7,r7,switch_as@l 1089 1090 mtspr SPRN_SRR0,r7 1091 mtspr SPRN_SRR1,r6 1092 rfi 1093 1094switch_as: 1095/* L1 DCache is used for initial RAM */ 1096 1097 /* Allocate Initial RAM in data cache. 1098 */ 1099 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1100 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1101 mfspr r2, L1CFG0 1102 andi. r2, r2, 0x1ff 1103 /* cache size * 1024 / (2 * L1 line size) */ 1104 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 1105 mtctr r2 1106 li r0,0 11071: 1108 dcbz r0,r3 1109 dcbtls 0,r0,r3 1110 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1111 bdnz 1b 1112 1113 /* Jump out the last 4K page and continue to 'normal' start */ 1114#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 1115 /* We assume that we're already running at the address we're linked at */ 1116 b _start_cont 1117#else 1118 /* Calculate absolute address in FLASH and jump there */ 1119 /*--------------------------------------------------------------*/ 1120 lis r3,CONFIG_SYS_MONITOR_BASE@h 1121 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 1122 addi r3,r3,_start_cont - _start + _START_OFFSET 1123 mtlr r3 1124 blr 1125#endif 1126 1127 .text 1128 .globl _start 1129_start: 1130 .long 0x27051956 /* U-BOOT Magic Number */ 1131 .globl version_string 1132version_string: 1133 .ascii U_BOOT_VERSION_STRING, "\0" 1134 1135 .align 4 1136 .globl _start_cont 1137_start_cont: 1138 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 1139 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h 1140 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ 1141 li r0,0 1142 stw r0,0(r3) /* Terminate Back Chain */ 1143 stw r0,+4(r3) /* NULL return address. */ 1144 mr r1,r3 /* Transfer to SP(r1) */ 1145 1146 GET_GOT 1147 1148 /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */ 1149 mr r3, r24 1150 1151 bl cpu_init_early_f 1152 1153 /* switch back to AS = 0 */ 1154 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 1155 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 1156 mtmsr r3 1157 isync 1158 1159 bl cpu_init_f 1160 bl board_init_f 1161 isync 1162 1163 /* NOTREACHED - board_init_f() does not return */ 1164 1165#ifndef MINIMAL_SPL 1166 . = EXC_OFF_SYS_RESET 1167 .globl _start_of_vectors 1168_start_of_vectors: 1169 1170/* Critical input. */ 1171 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 1172 1173/* Machine check */ 1174 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 1175 1176/* Data Storage exception. */ 1177 STD_EXCEPTION(0x0300, DataStorage, UnknownException) 1178 1179/* Instruction Storage exception. */ 1180 STD_EXCEPTION(0x0400, InstStorage, UnknownException) 1181 1182/* External Interrupt exception. */ 1183 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 1184 1185/* Alignment exception. */ 1186 . = 0x0600 1187Alignment: 1188 EXCEPTION_PROLOG(SRR0, SRR1) 1189 mfspr r4,DAR 1190 stw r4,_DAR(r21) 1191 mfspr r5,DSISR 1192 stw r5,_DSISR(r21) 1193 addi r3,r1,STACK_FRAME_OVERHEAD 1194 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 1195 1196/* Program check exception */ 1197 . = 0x0700 1198ProgramCheck: 1199 EXCEPTION_PROLOG(SRR0, SRR1) 1200 addi r3,r1,STACK_FRAME_OVERHEAD 1201 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 1202 MSR_KERNEL, COPY_EE) 1203 1204 /* No FPU on MPC85xx. This exception is not supposed to happen. 1205 */ 1206 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 1207 1208 . = 0x0900 1209/* 1210 * r0 - SYSCALL number 1211 * r3-... arguments 1212 */ 1213SystemCall: 1214 addis r11,r0,0 /* get functions table addr */ 1215 ori r11,r11,0 /* Note: this code is patched in trap_init */ 1216 addis r12,r0,0 /* get number of functions */ 1217 ori r12,r12,0 1218 1219 cmplw 0,r0,r12 1220 bge 1f 1221 1222 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 1223 add r11,r11,r0 1224 lwz r11,0(r11) 1225 1226 li r20,0xd00-4 /* Get stack pointer */ 1227 lwz r12,0(r20) 1228 subi r12,r12,12 /* Adjust stack pointer */ 1229 li r0,0xc00+_end_back-SystemCall 1230 cmplw 0,r0,r12 /* Check stack overflow */ 1231 bgt 1f 1232 stw r12,0(r20) 1233 1234 mflr r0 1235 stw r0,0(r12) 1236 mfspr r0,SRR0 1237 stw r0,4(r12) 1238 mfspr r0,SRR1 1239 stw r0,8(r12) 1240 1241 li r12,0xc00+_back-SystemCall 1242 mtlr r12 1243 mtspr SRR0,r11 1244 12451: SYNC 1246 rfi 1247_back: 1248 1249 mfmsr r11 /* Disable interrupts */ 1250 li r12,0 1251 ori r12,r12,MSR_EE 1252 andc r11,r11,r12 1253 SYNC /* Some chip revs need this... */ 1254 mtmsr r11 1255 SYNC 1256 1257 li r12,0xd00-4 /* restore regs */ 1258 lwz r12,0(r12) 1259 1260 lwz r11,0(r12) 1261 mtlr r11 1262 lwz r11,4(r12) 1263 mtspr SRR0,r11 1264 lwz r11,8(r12) 1265 mtspr SRR1,r11 1266 1267 addi r12,r12,12 /* Adjust stack pointer */ 1268 li r20,0xd00-4 1269 stw r12,0(r20) 1270 1271 SYNC 1272 rfi 1273_end_back: 1274 1275 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 1276 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 1277 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 1278 1279 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 1280 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 1281 1282 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 1283 1284 .globl _end_of_vectors 1285_end_of_vectors: 1286 1287 1288 . = . + (0x100 - ( . & 0xff )) /* align for debug */ 1289 1290/* 1291 * This code finishes saving the registers to the exception frame 1292 * and jumps to the appropriate handler for the exception. 1293 * Register r21 is pointer into trap frame, r1 has new stack pointer. 1294 */ 1295 .globl transfer_to_handler 1296transfer_to_handler: 1297 stw r22,_NIP(r21) 1298 lis r22,MSR_POW@h 1299 andc r23,r23,r22 1300 stw r23,_MSR(r21) 1301 SAVE_GPR(7, r21) 1302 SAVE_4GPRS(8, r21) 1303 SAVE_8GPRS(12, r21) 1304 SAVE_8GPRS(24, r21) 1305 1306 mflr r23 1307 andi. r24,r23,0x3f00 /* get vector offset */ 1308 stw r24,TRAP(r21) 1309 li r22,0 1310 stw r22,RESULT(r21) 1311 mtspr SPRG2,r22 /* r1 is now kernel sp */ 1312 1313 lwz r24,0(r23) /* virtual address of handler */ 1314 lwz r23,4(r23) /* where to go when done */ 1315 mtspr SRR0,r24 1316 mtspr SRR1,r20 1317 mtlr r23 1318 SYNC 1319 rfi /* jump to handler, enable MMU */ 1320 1321int_return: 1322 mfmsr r28 /* Disable interrupts */ 1323 li r4,0 1324 ori r4,r4,MSR_EE 1325 andc r28,r28,r4 1326 SYNC /* Some chip revs need this... */ 1327 mtmsr r28 1328 SYNC 1329 lwz r2,_CTR(r1) 1330 lwz r0,_LINK(r1) 1331 mtctr r2 1332 mtlr r0 1333 lwz r2,_XER(r1) 1334 lwz r0,_CCR(r1) 1335 mtspr XER,r2 1336 mtcrf 0xFF,r0 1337 REST_10GPRS(3, r1) 1338 REST_10GPRS(13, r1) 1339 REST_8GPRS(23, r1) 1340 REST_GPR(31, r1) 1341 lwz r2,_NIP(r1) /* Restore environment */ 1342 lwz r0,_MSR(r1) 1343 mtspr SRR0,r2 1344 mtspr SRR1,r0 1345 lwz r0,GPR0(r1) 1346 lwz r2,GPR2(r1) 1347 lwz r1,GPR1(r1) 1348 SYNC 1349 rfi 1350 1351crit_return: 1352 mfmsr r28 /* Disable interrupts */ 1353 li r4,0 1354 ori r4,r4,MSR_EE 1355 andc r28,r28,r4 1356 SYNC /* Some chip revs need this... */ 1357 mtmsr r28 1358 SYNC 1359 lwz r2,_CTR(r1) 1360 lwz r0,_LINK(r1) 1361 mtctr r2 1362 mtlr r0 1363 lwz r2,_XER(r1) 1364 lwz r0,_CCR(r1) 1365 mtspr XER,r2 1366 mtcrf 0xFF,r0 1367 REST_10GPRS(3, r1) 1368 REST_10GPRS(13, r1) 1369 REST_8GPRS(23, r1) 1370 REST_GPR(31, r1) 1371 lwz r2,_NIP(r1) /* Restore environment */ 1372 lwz r0,_MSR(r1) 1373 mtspr SPRN_CSRR0,r2 1374 mtspr SPRN_CSRR1,r0 1375 lwz r0,GPR0(r1) 1376 lwz r2,GPR2(r1) 1377 lwz r1,GPR1(r1) 1378 SYNC 1379 rfci 1380 1381mck_return: 1382 mfmsr r28 /* Disable interrupts */ 1383 li r4,0 1384 ori r4,r4,MSR_EE 1385 andc r28,r28,r4 1386 SYNC /* Some chip revs need this... */ 1387 mtmsr r28 1388 SYNC 1389 lwz r2,_CTR(r1) 1390 lwz r0,_LINK(r1) 1391 mtctr r2 1392 mtlr r0 1393 lwz r2,_XER(r1) 1394 lwz r0,_CCR(r1) 1395 mtspr XER,r2 1396 mtcrf 0xFF,r0 1397 REST_10GPRS(3, r1) 1398 REST_10GPRS(13, r1) 1399 REST_8GPRS(23, r1) 1400 REST_GPR(31, r1) 1401 lwz r2,_NIP(r1) /* Restore environment */ 1402 lwz r0,_MSR(r1) 1403 mtspr SPRN_MCSRR0,r2 1404 mtspr SPRN_MCSRR1,r0 1405 lwz r0,GPR0(r1) 1406 lwz r2,GPR2(r1) 1407 lwz r1,GPR1(r1) 1408 SYNC 1409 rfmci 1410 1411/* Cache functions. 1412*/ 1413.globl flush_icache 1414flush_icache: 1415.globl invalidate_icache 1416invalidate_icache: 1417 mfspr r0,L1CSR1 1418 ori r0,r0,L1CSR1_ICFI 1419 msync 1420 isync 1421 mtspr L1CSR1,r0 1422 isync 1423 blr /* entire I cache */ 1424 1425.globl invalidate_dcache 1426invalidate_dcache: 1427 mfspr r0,L1CSR0 1428 ori r0,r0,L1CSR0_DCFI 1429 msync 1430 isync 1431 mtspr L1CSR0,r0 1432 isync 1433 blr 1434 1435 .globl icache_enable 1436icache_enable: 1437 mflr r8 1438 bl invalidate_icache 1439 mtlr r8 1440 isync 1441 mfspr r4,L1CSR1 1442 ori r4,r4,0x0001 1443 oris r4,r4,0x0001 1444 mtspr L1CSR1,r4 1445 isync 1446 blr 1447 1448 .globl icache_disable 1449icache_disable: 1450 mfspr r0,L1CSR1 1451 lis r3,0 1452 ori r3,r3,L1CSR1_ICE 1453 andc r0,r0,r3 1454 mtspr L1CSR1,r0 1455 isync 1456 blr 1457 1458 .globl icache_status 1459icache_status: 1460 mfspr r3,L1CSR1 1461 andi. r3,r3,L1CSR1_ICE 1462 blr 1463 1464 .globl dcache_enable 1465dcache_enable: 1466 mflr r8 1467 bl invalidate_dcache 1468 mtlr r8 1469 isync 1470 mfspr r0,L1CSR0 1471 ori r0,r0,0x0001 1472 oris r0,r0,0x0001 1473 msync 1474 isync 1475 mtspr L1CSR0,r0 1476 isync 1477 blr 1478 1479 .globl dcache_disable 1480dcache_disable: 1481 mfspr r3,L1CSR0 1482 lis r4,0 1483 ori r4,r4,L1CSR0_DCE 1484 andc r3,r3,r4 1485 mtspr L1CSR0,r3 1486 isync 1487 blr 1488 1489 .globl dcache_status 1490dcache_status: 1491 mfspr r3,L1CSR0 1492 andi. r3,r3,L1CSR0_DCE 1493 blr 1494 1495 .globl get_pir 1496get_pir: 1497 mfspr r3,PIR 1498 blr 1499 1500 .globl get_pvr 1501get_pvr: 1502 mfspr r3,PVR 1503 blr 1504 1505 .globl get_svr 1506get_svr: 1507 mfspr r3,SVR 1508 blr 1509 1510 .globl wr_tcr 1511wr_tcr: 1512 mtspr TCR,r3 1513 blr 1514 1515/*------------------------------------------------------------------------------- */ 1516/* Function: in8 */ 1517/* Description: Input 8 bits */ 1518/*------------------------------------------------------------------------------- */ 1519 .globl in8 1520in8: 1521 lbz r3,0x0000(r3) 1522 blr 1523 1524/*------------------------------------------------------------------------------- */ 1525/* Function: out8 */ 1526/* Description: Output 8 bits */ 1527/*------------------------------------------------------------------------------- */ 1528 .globl out8 1529out8: 1530 stb r4,0x0000(r3) 1531 sync 1532 blr 1533 1534/*------------------------------------------------------------------------------- */ 1535/* Function: out16 */ 1536/* Description: Output 16 bits */ 1537/*------------------------------------------------------------------------------- */ 1538 .globl out16 1539out16: 1540 sth r4,0x0000(r3) 1541 sync 1542 blr 1543 1544/*------------------------------------------------------------------------------- */ 1545/* Function: out16r */ 1546/* Description: Byte reverse and output 16 bits */ 1547/*------------------------------------------------------------------------------- */ 1548 .globl out16r 1549out16r: 1550 sthbrx r4,r0,r3 1551 sync 1552 blr 1553 1554/*------------------------------------------------------------------------------- */ 1555/* Function: out32 */ 1556/* Description: Output 32 bits */ 1557/*------------------------------------------------------------------------------- */ 1558 .globl out32 1559out32: 1560 stw r4,0x0000(r3) 1561 sync 1562 blr 1563 1564/*------------------------------------------------------------------------------- */ 1565/* Function: out32r */ 1566/* Description: Byte reverse and output 32 bits */ 1567/*------------------------------------------------------------------------------- */ 1568 .globl out32r 1569out32r: 1570 stwbrx r4,r0,r3 1571 sync 1572 blr 1573 1574/*------------------------------------------------------------------------------- */ 1575/* Function: in16 */ 1576/* Description: Input 16 bits */ 1577/*------------------------------------------------------------------------------- */ 1578 .globl in16 1579in16: 1580 lhz r3,0x0000(r3) 1581 blr 1582 1583/*------------------------------------------------------------------------------- */ 1584/* Function: in16r */ 1585/* Description: Input 16 bits and byte reverse */ 1586/*------------------------------------------------------------------------------- */ 1587 .globl in16r 1588in16r: 1589 lhbrx r3,r0,r3 1590 blr 1591 1592/*------------------------------------------------------------------------------- */ 1593/* Function: in32 */ 1594/* Description: Input 32 bits */ 1595/*------------------------------------------------------------------------------- */ 1596 .globl in32 1597in32: 1598 lwz 3,0x0000(3) 1599 blr 1600 1601/*------------------------------------------------------------------------------- */ 1602/* Function: in32r */ 1603/* Description: Input 32 bits and byte reverse */ 1604/*------------------------------------------------------------------------------- */ 1605 .globl in32r 1606in32r: 1607 lwbrx r3,r0,r3 1608 blr 1609#endif /* !MINIMAL_SPL */ 1610 1611/*------------------------------------------------------------------------------*/ 1612 1613/* 1614 * void write_tlb(mas0, mas1, mas2, mas3, mas7) 1615 */ 1616 .globl write_tlb 1617write_tlb: 1618 mtspr MAS0,r3 1619 mtspr MAS1,r4 1620 mtspr MAS2,r5 1621 mtspr MAS3,r6 1622#ifdef CONFIG_ENABLE_36BIT_PHYS 1623 mtspr MAS7,r7 1624#endif 1625 li r3,0 1626#ifdef CONFIG_SYS_BOOK3E_HV 1627 mtspr MAS8,r3 1628#endif 1629 isync 1630 tlbwe 1631 msync 1632 isync 1633 blr 1634 1635/* 1636 * void relocate_code (addr_sp, gd, addr_moni) 1637 * 1638 * This "function" does not return, instead it continues in RAM 1639 * after relocating the monitor code. 1640 * 1641 * r3 = dest 1642 * r4 = src 1643 * r5 = length in bytes 1644 * r6 = cachelinesize 1645 */ 1646 .globl relocate_code 1647relocate_code: 1648 mr r1,r3 /* Set new stack pointer */ 1649 mr r9,r4 /* Save copy of Init Data pointer */ 1650 mr r10,r5 /* Save copy of Destination Address */ 1651 1652 GET_GOT 1653 mr r3,r5 /* Destination Address */ 1654 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1655 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 1656 lwz r5,GOT(__init_end) 1657 sub r5,r5,r4 1658 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 1659 1660 /* 1661 * Fix GOT pointer: 1662 * 1663 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1664 * 1665 * Offset: 1666 */ 1667 sub r15,r10,r4 1668 1669 /* First our own GOT */ 1670 add r12,r12,r15 1671 /* the the one used by the C code */ 1672 add r30,r30,r15 1673 1674 /* 1675 * Now relocate code 1676 */ 1677 1678 cmplw cr1,r3,r4 1679 addi r0,r5,3 1680 srwi. r0,r0,2 1681 beq cr1,4f /* In place copy is not necessary */ 1682 beq 7f /* Protect against 0 count */ 1683 mtctr r0 1684 bge cr1,2f 1685 1686 la r8,-4(r4) 1687 la r7,-4(r3) 16881: lwzu r0,4(r8) 1689 stwu r0,4(r7) 1690 bdnz 1b 1691 b 4f 1692 16932: slwi r0,r0,2 1694 add r8,r4,r0 1695 add r7,r3,r0 16963: lwzu r0,-4(r8) 1697 stwu r0,-4(r7) 1698 bdnz 3b 1699 1700/* 1701 * Now flush the cache: note that we must start from a cache aligned 1702 * address. Otherwise we might miss one cache line. 1703 */ 17044: cmpwi r6,0 1705 add r5,r3,r5 1706 beq 7f /* Always flush prefetch queue in any case */ 1707 subi r0,r6,1 1708 andc r3,r3,r0 1709 mr r4,r3 17105: dcbst 0,r4 1711 add r4,r4,r6 1712 cmplw r4,r5 1713 blt 5b 1714 sync /* Wait for all dcbst to complete on bus */ 1715 mr r4,r3 17166: icbi 0,r4 1717 add r4,r4,r6 1718 cmplw r4,r5 1719 blt 6b 17207: sync /* Wait for all icbi to complete on bus */ 1721 isync 1722 1723/* 1724 * We are done. Do not return, instead branch to second part of board 1725 * initialization, now running from RAM. 1726 */ 1727 1728 addi r0,r10,in_ram - _start + _START_OFFSET 1729 1730 /* 1731 * As IVPR is going to point RAM address, 1732 * Make sure IVOR15 has valid opcode to support debugger 1733 */ 1734 mtspr IVOR15,r0 1735 1736 /* 1737 * Re-point the IVPR at RAM 1738 */ 1739 mtspr IVPR,r10 1740 1741 mtlr r0 1742 blr /* NEVER RETURNS! */ 1743 .globl in_ram 1744in_ram: 1745 1746 /* 1747 * Relocation Function, r12 point to got2+0x8000 1748 * 1749 * Adjust got2 pointers, no need to check for 0, this code 1750 * already puts a few entries in the table. 1751 */ 1752 li r0,__got2_entries@sectoff@l 1753 la r3,GOT(_GOT2_TABLE_) 1754 lwz r11,GOT(_GOT2_TABLE_) 1755 mtctr r0 1756 sub r11,r3,r11 1757 addi r3,r3,-4 17581: lwzu r0,4(r3) 1759 cmpwi r0,0 1760 beq- 2f 1761 add r0,r0,r11 1762 stw r0,0(r3) 17632: bdnz 1b 1764 1765 /* 1766 * Now adjust the fixups and the pointers to the fixups 1767 * in case we need to move ourselves again. 1768 */ 1769 li r0,__fixup_entries@sectoff@l 1770 lwz r3,GOT(_FIXUP_TABLE_) 1771 cmpwi r0,0 1772 mtctr r0 1773 addi r3,r3,-4 1774 beq 4f 17753: lwzu r4,4(r3) 1776 lwzux r0,r4,r11 1777 cmpwi r0,0 1778 add r0,r0,r11 1779 stw r4,0(r3) 1780 beq- 5f 1781 stw r0,0(r4) 17825: bdnz 3b 17834: 1784clear_bss: 1785 /* 1786 * Now clear BSS segment 1787 */ 1788 lwz r3,GOT(__bss_start) 1789 lwz r4,GOT(__bss_end) 1790 1791 cmplw 0,r3,r4 1792 beq 6f 1793 1794 li r0,0 17955: 1796 stw r0,0(r3) 1797 addi r3,r3,4 1798 cmplw 0,r3,r4 1799 blt 5b 18006: 1801 1802 mr r3,r9 /* Init Data pointer */ 1803 mr r4,r10 /* Destination Address */ 1804 bl board_init_r 1805 1806#ifndef MINIMAL_SPL 1807 /* 1808 * Copy exception vector code to low memory 1809 * 1810 * r3: dest_addr 1811 * r7: source address, r8: end address, r9: target address 1812 */ 1813 .globl trap_init 1814trap_init: 1815 mflr r4 /* save link register */ 1816 GET_GOT 1817 lwz r7,GOT(_start_of_vectors) 1818 lwz r8,GOT(_end_of_vectors) 1819 1820 li r9,0x100 /* reset vector always at 0x100 */ 1821 1822 cmplw 0,r7,r8 1823 bgelr /* return if r7>=r8 - just in case */ 18241: 1825 lwz r0,0(r7) 1826 stw r0,0(r9) 1827 addi r7,r7,4 1828 addi r9,r9,4 1829 cmplw 0,r7,r8 1830 bne 1b 1831 1832 /* 1833 * relocate `hdlr' and `int_return' entries 1834 */ 1835 li r7,.L_CriticalInput - _start + _START_OFFSET 1836 bl trap_reloc 1837 li r7,.L_MachineCheck - _start + _START_OFFSET 1838 bl trap_reloc 1839 li r7,.L_DataStorage - _start + _START_OFFSET 1840 bl trap_reloc 1841 li r7,.L_InstStorage - _start + _START_OFFSET 1842 bl trap_reloc 1843 li r7,.L_ExtInterrupt - _start + _START_OFFSET 1844 bl trap_reloc 1845 li r7,.L_Alignment - _start + _START_OFFSET 1846 bl trap_reloc 1847 li r7,.L_ProgramCheck - _start + _START_OFFSET 1848 bl trap_reloc 1849 li r7,.L_FPUnavailable - _start + _START_OFFSET 1850 bl trap_reloc 1851 li r7,.L_Decrementer - _start + _START_OFFSET 1852 bl trap_reloc 1853 li r7,.L_IntervalTimer - _start + _START_OFFSET 1854 li r8,_end_of_vectors - _start + _START_OFFSET 18552: 1856 bl trap_reloc 1857 addi r7,r7,0x100 /* next exception vector */ 1858 cmplw 0,r7,r8 1859 blt 2b 1860 1861 /* Update IVORs as per relocated vector table address */ 1862 li r7,0x0100 1863 mtspr IVOR0,r7 /* 0: Critical input */ 1864 li r7,0x0200 1865 mtspr IVOR1,r7 /* 1: Machine check */ 1866 li r7,0x0300 1867 mtspr IVOR2,r7 /* 2: Data storage */ 1868 li r7,0x0400 1869 mtspr IVOR3,r7 /* 3: Instruction storage */ 1870 li r7,0x0500 1871 mtspr IVOR4,r7 /* 4: External interrupt */ 1872 li r7,0x0600 1873 mtspr IVOR5,r7 /* 5: Alignment */ 1874 li r7,0x0700 1875 mtspr IVOR6,r7 /* 6: Program check */ 1876 li r7,0x0800 1877 mtspr IVOR7,r7 /* 7: floating point unavailable */ 1878 li r7,0x0900 1879 mtspr IVOR8,r7 /* 8: System call */ 1880 /* 9: Auxiliary processor unavailable(unsupported) */ 1881 li r7,0x0a00 1882 mtspr IVOR10,r7 /* 10: Decrementer */ 1883 li r7,0x0b00 1884 mtspr IVOR11,r7 /* 11: Interval timer */ 1885 li r7,0x0c00 1886 mtspr IVOR12,r7 /* 12: Watchdog timer */ 1887 li r7,0x0d00 1888 mtspr IVOR13,r7 /* 13: Data TLB error */ 1889 li r7,0x0e00 1890 mtspr IVOR14,r7 /* 14: Instruction TLB error */ 1891 li r7,0x0f00 1892 mtspr IVOR15,r7 /* 15: Debug */ 1893 1894 lis r7,0x0 1895 mtspr IVPR,r7 1896 1897 mtlr r4 /* restore link register */ 1898 blr 1899 1900.globl unlock_ram_in_cache 1901unlock_ram_in_cache: 1902 /* invalidate the INIT_RAM section */ 1903 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1904 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1905 mfspr r4,L1CFG0 1906 andi. r4,r4,0x1ff 1907 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1908 mtctr r4 19091: dcbi r0,r3 1910 dcblc r0,r3 1911 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1912 bdnz 1b 1913 sync 1914 1915 /* Invalidate the TLB entries for the cache */ 1916 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1917 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1918 tlbivax 0,r3 1919 addi r3,r3,0x1000 1920 tlbivax 0,r3 1921 addi r3,r3,0x1000 1922 tlbivax 0,r3 1923 addi r3,r3,0x1000 1924 tlbivax 0,r3 1925 isync 1926 blr 1927 1928.globl flush_dcache 1929flush_dcache: 1930 mfspr r3,SPRN_L1CFG0 1931 1932 rlwinm r5,r3,9,3 /* Extract cache block size */ 1933 twlgti r5,1 /* Only 32 and 64 byte cache blocks 1934 * are currently defined. 1935 */ 1936 li r4,32 1937 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1938 * log2(number of ways) 1939 */ 1940 slw r5,r4,r5 /* r5 = cache block size */ 1941 1942 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1943 mulli r7,r7,13 /* An 8-way cache will require 13 1944 * loads per set. 1945 */ 1946 slw r7,r7,r6 1947 1948 /* save off HID0 and set DCFA */ 1949 mfspr r8,SPRN_HID0 1950 ori r9,r8,HID0_DCFA@l 1951 mtspr SPRN_HID0,r9 1952 isync 1953 1954 lis r4,0 1955 mtctr r7 1956 19571: lwz r3,0(r4) /* Load... */ 1958 add r4,r4,r5 1959 bdnz 1b 1960 1961 msync 1962 lis r4,0 1963 mtctr r7 1964 19651: dcbf 0,r4 /* ...and flush. */ 1966 add r4,r4,r5 1967 bdnz 1b 1968 1969 /* restore HID0 */ 1970 mtspr SPRN_HID0,r8 1971 isync 1972 1973 blr 1974#endif /* !MINIMAL_SPL */ 1975