1/* 2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. 3 * Copyright (C) 2003 Motorola,Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 9 * 10 * The processor starts at 0xfffffffc and the code is first executed in the 11 * last 4K page(0xfffff000-0xffffffff) in flash/rom. 12 * 13 */ 14 15#include <asm-offsets.h> 16#include <config.h> 17#include <mpc85xx.h> 18#include <version.h> 19 20#include <ppc_asm.tmpl> 21#include <ppc_defs.h> 22 23#include <asm/cache.h> 24#include <asm/mmu.h> 25 26#undef MSR_KERNEL 27#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 28 29#define LAW_EN 0x80000000 30 31#if defined(CONFIG_NAND_SPL) || \ 32 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) 33#define MINIMAL_SPL 34#endif 35 36#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \ 37 !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 38#define NOR_BOOT 39#endif 40 41/* 42 * Set up GOT: Global Offset Table 43 * 44 * Use r12 to access the GOT 45 */ 46 START_GOT 47 GOT_ENTRY(_GOT2_TABLE_) 48 GOT_ENTRY(_FIXUP_TABLE_) 49 50#ifndef MINIMAL_SPL 51 GOT_ENTRY(_start) 52 GOT_ENTRY(_start_of_vectors) 53 GOT_ENTRY(_end_of_vectors) 54 GOT_ENTRY(transfer_to_handler) 55#endif 56 57 GOT_ENTRY(__init_end) 58 GOT_ENTRY(__bss_end) 59 GOT_ENTRY(__bss_start) 60 END_GOT 61 62/* 63 * e500 Startup -- after reset only the last 4KB of the effective 64 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 65 * section is located at THIS LAST page and basically does three 66 * things: clear some registers, set up exception tables and 67 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 68 * continue the boot procedure. 69 70 * Once the boot rom is mapped by TLB entries we can proceed 71 * with normal startup. 72 * 73 */ 74 75 .section .bootpg,"ax" 76 .globl _start_e500 77 78_start_e500: 79/* Enable debug exception */ 80 li r1,MSR_DE 81 mtmsr r1 82 83 /* 84 * If we got an ePAPR device tree pointer passed in as r3, we need that 85 * later in cpu_init_early_f(). Save it to a safe register before we 86 * clobber it so that we can fetch it from there later. 87 */ 88 mr r24, r3 89 90#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 91 mfspr r3,SPRN_SVR 92 rlwinm r3,r3,0,0xff 93 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 94 cmpw r3,r4 95 beq 1f 96 97#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 98 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 99 cmpw r3,r4 100 beq 1f 101#endif 102 103 /* Not a supported revision affected by erratum */ 104 li r27,0 105 b 2f 106 1071: li r27,1 /* Remember for later that we have the erratum */ 108 /* Erratum says set bits 55:60 to 001001 */ 109 msync 110 isync 111 mfspr r3,SPRN_HDBCR0 112 li r4,0x48 113 rlwimi r3,r4,0,0x1f8 114 mtspr SPRN_HDBCR0,r3 115 isync 1162: 117#endif 118#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 119 msync 120 isync 121 mfspr r3, SPRN_HDBCR0 122 oris r3, r3, 0x0080 123 mtspr SPRN_HDBCR0, r3 124#endif 125 126 127#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ 128 !defined(CONFIG_E6500) 129 /* ISBC uses L2 as stack. 130 * Disable L2 cache here so that u-boot can enable it later 131 * as part of it's normal flow 132 */ 133 134 /* Check if L2 is enabled */ 135 mfspr r3, SPRN_L2CSR0 136 lis r2, L2CSR0_L2E@h 137 ori r2, r2, L2CSR0_L2E@l 138 and. r4, r3, r2 139 beq l2_disabled 140 141 mfspr r3, SPRN_L2CSR0 142 /* Flush L2 cache */ 143 lis r2,(L2CSR0_L2FL)@h 144 ori r2, r2, (L2CSR0_L2FL)@l 145 or r3, r2, r3 146 sync 147 isync 148 mtspr SPRN_L2CSR0,r3 149 isync 1501: 151 mfspr r3, SPRN_L2CSR0 152 and. r1, r3, r2 153 bne 1b 154 155 mfspr r3, SPRN_L2CSR0 156 lis r2, L2CSR0_L2E@h 157 ori r2, r2, L2CSR0_L2E@l 158 andc r4, r3, r2 159 sync 160 isync 161 mtspr SPRN_L2CSR0,r4 162 isync 163 164l2_disabled: 165#endif 166 167/* clear registers/arrays not reset by hardware */ 168 169 /* L1 */ 170 li r0,2 171 mtspr L1CSR0,r0 /* invalidate d-cache */ 172 mtspr L1CSR1,r0 /* invalidate i-cache */ 173 174 mfspr r1,DBSR 175 mtspr DBSR,r1 /* Clear all valid bits */ 176 177 178 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch 179 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h 180 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l 181 mtspr MAS0, \scratch 182 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h 183 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l 184 mtspr MAS1, \scratch 185 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h 186 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l 187 mtspr MAS2, \scratch 188 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h 189 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l 190 mtspr MAS3, \scratch 191 lis \scratch, \phy_high@h 192 ori \scratch, \scratch, \phy_high@l 193 mtspr MAS7, \scratch 194 isync 195 msync 196 tlbwe 197 isync 198 .endm 199 200 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch 201 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h 202 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l 203 mtspr MAS0, \scratch 204 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h 205 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l 206 mtspr MAS1, \scratch 207 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h 208 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l 209 mtspr MAS2, \scratch 210 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h 211 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l 212 mtspr MAS3, \scratch 213 lis \scratch, \phy_high@h 214 ori \scratch, \scratch, \phy_high@l 215 mtspr MAS7, \scratch 216 isync 217 msync 218 tlbwe 219 isync 220 .endm 221 222 .macro delete_tlb1_entry esel scratch 223 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h 224 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l 225 mtspr MAS0, \scratch 226 li \scratch, 0 227 mtspr MAS1, \scratch 228 isync 229 msync 230 tlbwe 231 isync 232 .endm 233 234 .macro delete_tlb0_entry esel epn wimg scratch 235 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h 236 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l 237 mtspr MAS0, \scratch 238 li \scratch, 0 239 mtspr MAS1, \scratch 240 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h 241 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l 242 mtspr MAS2, \scratch 243 isync 244 msync 245 tlbwe 246 isync 247 .endm 248 249/* Interrupt vectors do not fit in minimal SPL. */ 250#if !defined(MINIMAL_SPL) 251 /* Setup interrupt vectors */ 252 lis r1,CONFIG_SYS_MONITOR_BASE@h 253 mtspr IVPR,r1 254 255 li r4,CriticalInput@l 256 mtspr IVOR0,r4 /* 0: Critical input */ 257 li r4,MachineCheck@l 258 mtspr IVOR1,r4 /* 1: Machine check */ 259 li r4,DataStorage@l 260 mtspr IVOR2,r4 /* 2: Data storage */ 261 li r4,InstStorage@l 262 mtspr IVOR3,r4 /* 3: Instruction storage */ 263 li r4,ExtInterrupt@l 264 mtspr IVOR4,r4 /* 4: External interrupt */ 265 li r4,Alignment@l 266 mtspr IVOR5,r4 /* 5: Alignment */ 267 li r4,ProgramCheck@l 268 mtspr IVOR6,r4 /* 6: Program check */ 269 li r4,FPUnavailable@l 270 mtspr IVOR7,r4 /* 7: floating point unavailable */ 271 li r4,SystemCall@l 272 mtspr IVOR8,r4 /* 8: System call */ 273 /* 9: Auxiliary processor unavailable(unsupported) */ 274 li r4,Decrementer@l 275 mtspr IVOR10,r4 /* 10: Decrementer */ 276 li r4,IntervalTimer@l 277 mtspr IVOR11,r4 /* 11: Interval timer */ 278 li r4,WatchdogTimer@l 279 mtspr IVOR12,r4 /* 12: Watchdog timer */ 280 li r4,DataTLBError@l 281 mtspr IVOR13,r4 /* 13: Data TLB error */ 282 li r4,InstructionTLBError@l 283 mtspr IVOR14,r4 /* 14: Instruction TLB error */ 284 li r4,DebugBreakpoint@l 285 mtspr IVOR15,r4 /* 15: Debug */ 286#endif 287 288 /* Clear and set up some registers. */ 289 li r0,0x0000 290 lis r1,0xffff 291 mtspr DEC,r0 /* prevent dec exceptions */ 292 mttbl r0 /* prevent fit & wdt exceptions */ 293 mttbu r0 294 mtspr TSR,r1 /* clear all timer exception status */ 295 mtspr TCR,r0 /* disable all */ 296 mtspr ESR,r0 /* clear exception syndrome register */ 297 mtspr MCSR,r0 /* machine check syndrome register */ 298 mtxer r0 /* clear integer exception register */ 299 300#ifdef CONFIG_SYS_BOOK3E_HV 301 mtspr MAS8,r0 /* make sure MAS8 is clear */ 302#endif 303 304 /* Enable Time Base and Select Time Base Clock */ 305 lis r0,HID0_EMCP@h /* Enable machine check */ 306#if defined(CONFIG_ENABLE_36BIT_PHYS) 307 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 308#endif 309#ifndef CONFIG_E500MC 310 ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 311#endif 312 mtspr HID0,r0 313 314#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500) 315 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 316 mfspr r3,PVR 317 andi. r3,r3, 0xff 318 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 319 blt 1f 320 /* Set MBDD bit also */ 321 ori r0, r0, HID1_MBDD@l 3221: 323 mtspr HID1,r0 324#endif 325 326#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 327 mfspr r3,SPRN_HDBCR1 328 oris r3,r3,0x0100 329 mtspr SPRN_HDBCR1,r3 330#endif 331 332 /* Enable Branch Prediction */ 333#if defined(CONFIG_BTB) 334 lis r0,BUCSR_ENABLE@h 335 ori r0,r0,BUCSR_ENABLE@l 336 mtspr SPRN_BUCSR,r0 337#endif 338 339#if defined(CONFIG_SYS_INIT_DBCR) 340 lis r1,0xffff 341 ori r1,r1,0xffff 342 mtspr DBSR,r1 /* Clear all status bits */ 343 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 344 ori r0,r0,CONFIG_SYS_INIT_DBCR@l 345 mtspr DBCR0,r0 346#endif 347 348#ifdef CONFIG_MPC8569 349#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 350#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 351 352 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 353 * use address space which is more than 12bits, and it must be done in 354 * the 4K boot page. So we set this bit here. 355 */ 356 357 /* create a temp mapping TLB0[0] for LBCR */ 358 create_tlb0_entry 0, \ 359 0, BOOKE_PAGESZ_4K, \ 360 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \ 361 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \ 362 0, r6 363 364 /* Set LBCR register */ 365 lis r4,CONFIG_SYS_LBCR_ADDR@h 366 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 367 368 lis r5,CONFIG_SYS_LBC_LBCR@h 369 ori r5,r5,CONFIG_SYS_LBC_LBCR@l 370 stw r5,0(r4) 371 isync 372 373 /* invalidate this temp TLB */ 374 lis r4,CONFIG_SYS_LBC_ADDR@h 375 ori r4,r4,CONFIG_SYS_LBC_ADDR@l 376 tlbivax 0,r4 377 isync 378 379#endif /* CONFIG_MPC8569 */ 380 381/* 382 * Search for the TLB that covers the code we're executing, and shrink it 383 * so that it covers only this 4K page. That will ensure that any other 384 * TLB we create won't interfere with it. We assume that the TLB exists, 385 * which is why we don't check the Valid bit of MAS1. We also assume 386 * it is in TLB1. 387 * 388 * This is necessary, for example, when booting from the on-chip ROM, 389 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. 390 */ 391 bl nexti /* Find our address */ 392nexti: mflr r1 /* R1 = our PC */ 393 li r2, 0 394 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ 395 isync 396 msync 397 tlbsx 0, r1 /* This must succeed */ 398 399 mfspr r14, MAS0 /* Save ESEL for later */ 400 rlwinm r14, r14, 16, 0xfff 401 402 /* Set the size of the TLB to 4KB */ 403 mfspr r3, MAS1 404 li r2, 0xF80 405 andc r3, r3, r2 /* Clear the TSIZE bits */ 406 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l 407 oris r3, r3, MAS1_IPROT@h 408 mtspr MAS1, r3 409 410 /* 411 * Set the base address of the TLB to our PC. We assume that 412 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. 413 */ 414 lis r3, MAS2_EPN@h 415 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ 416 417 and r1, r1, r3 /* Our PC, rounded down to the nearest page */ 418 419 mfspr r2, MAS2 420 andc r2, r2, r3 421 or r2, r2, r1 422#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 423 cmpwi r27,0 424 beq 1f 425 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */ 426 rlwinm r2, r2, 0, ~MAS2_I 427 ori r2, r2, MAS2_G 4281: 429#endif 430 mtspr MAS2, r2 /* Set the EPN to our PC base address */ 431 432 mfspr r2, MAS3 433 andc r2, r2, r3 434 or r2, r2, r1 435 mtspr MAS3, r2 /* Set the RPN to our PC base address */ 436 437 isync 438 msync 439 tlbwe 440 441/* 442 * Clear out any other TLB entries that may exist, to avoid conflicts. 443 * Our TLB entry is in r14. 444 */ 445 li r0, TLBIVAX_ALL | TLBIVAX_TLB0 446 tlbivax 0, r0 447 tlbsync 448 449 mfspr r4, SPRN_TLB1CFG 450 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK 451 452 li r3, 0 453 mtspr MAS1, r3 4541: cmpw r3, r14 455 rlwinm r5, r3, 16, MAS0_ESEL_MSK 456 addi r3, r3, 1 457 beq 2f /* skip the entry we're executing from */ 458 459 oris r5, r5, MAS0_TLBSEL(1)@h 460 mtspr MAS0, r5 461 462 isync 463 tlbwe 464 isync 465 msync 466 4672: cmpw r3, r4 468 blt 1b 469 470#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \ 471 !defined(CONFIG_SECURE_BOOT) 472/* 473 * TLB entry for debuggging in AS1 474 * Create temporary TLB entry in AS0 to handle debug exception 475 * As on debug exception MSR is cleared i.e. Address space is changed 476 * to 0. A TLB entry (in AS0) is required to handle debug exception generated 477 * in AS1. 478 */ 479 480#ifdef NOR_BOOT 481/* 482 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 483 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. 484 * and this window is outside of 4K boot window. 485 */ 486 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ 487 0, BOOKE_PAGESZ_4M, \ 488 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ 489 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 490 0, r6 491 492#else 493/* 494 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 495 * because "nexti" will resize TLB to 4K 496 */ 497 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ 498 0, BOOKE_PAGESZ_256K, \ 499 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \ 500 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \ 501 0, r6 502#endif 503#endif 504 505/* 506 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default 507 * location is not where we want it. This typically happens on a 36-bit 508 * system, where we want to move CCSR to near the top of 36-bit address space. 509 * 510 * To move CCSR, we create two temporary TLBs, one for the old location, and 511 * another for the new location. On CoreNet systems, we also need to create 512 * a special, temporary LAW. 513 * 514 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for 515 * long-term TLBs, so we use TLB0 here. 516 */ 517#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) 518 519#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) 520#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." 521#endif 522 523create_ccsr_new_tlb: 524 /* 525 * Create a TLB for the new location of CCSR. Register R8 is reserved 526 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). 527 */ 528 lis r8, CONFIG_SYS_CCSRBAR@h 529 ori r8, r8, CONFIG_SYS_CCSRBAR@l 530 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h 531 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l 532 create_tlb0_entry 0, \ 533 0, BOOKE_PAGESZ_4K, \ 534 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ 535 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ 536 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 537 /* 538 * Create a TLB for the current location of CCSR. Register R9 is reserved 539 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). 540 */ 541create_ccsr_old_tlb: 542 create_tlb0_entry 1, \ 543 0, BOOKE_PAGESZ_4K, \ 544 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ 545 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ 546 0, r3 /* The default CCSR address is always a 32-bit number */ 547 548 549 /* 550 * We have a TLB for what we think is the current (old) CCSR. Let's 551 * verify that, otherwise we won't be able to move it. 552 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only 553 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. 554 */ 555verify_old_ccsr: 556 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h 557 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l 558#ifdef CONFIG_FSL_CORENET 559 lwz r1, 4(r9) /* CCSRBARL */ 560#else 561 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ 562 slwi r1, r1, 12 563#endif 564 565 cmpl 0, r0, r1 566 567 /* 568 * If the value we read from CCSRBARL is not what we expect, then 569 * enter an infinite loop. This will at least allow a debugger to 570 * halt execution and examine TLBs, etc. There's no point in going 571 * on. 572 */ 573infinite_debug_loop: 574 bne infinite_debug_loop 575 576#ifdef CONFIG_FSL_CORENET 577 578#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 579#define LAW_SIZE_4K 0xb 580#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) 581#define CCSRAR_C 0x80000000 /* Commit */ 582 583create_temp_law: 584 /* 585 * On CoreNet systems, we create the temporary LAW using a special LAW 586 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. 587 */ 588 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 589 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 590 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 591 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 592 lis r2, CCSRBAR_LAWAR@h 593 ori r2, r2, CCSRBAR_LAWAR@l 594 595 stw r0, 0xc00(r9) /* LAWBARH0 */ 596 stw r1, 0xc04(r9) /* LAWBARL0 */ 597 sync 598 stw r2, 0xc08(r9) /* LAWAR0 */ 599 600 /* 601 * Read back from LAWAR to ensure the update is complete. e500mc 602 * cores also require an isync. 603 */ 604 lwz r0, 0xc08(r9) /* LAWAR0 */ 605 isync 606 607 /* 608 * Read the current CCSRBARH and CCSRBARL using load word instructions. 609 * Follow this with an isync instruction. This forces any outstanding 610 * accesses to configuration space to completion. 611 */ 612read_old_ccsrbar: 613 lwz r0, 0(r9) /* CCSRBARH */ 614 lwz r0, 4(r9) /* CCSRBARL */ 615 isync 616 617 /* 618 * Write the new values for CCSRBARH and CCSRBARL to their old 619 * locations. The CCSRBARH has a shadow register. When the CCSRBARH 620 * has a new value written it loads a CCSRBARH shadow register. When 621 * the CCSRBARL is written, the CCSRBARH shadow register contents 622 * along with the CCSRBARL value are loaded into the CCSRBARH and 623 * CCSRBARL registers, respectively. Follow this with a sync 624 * instruction. 625 */ 626write_new_ccsrbar: 627 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 628 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 629 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 630 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 631 lis r2, CCSRAR_C@h 632 ori r2, r2, CCSRAR_C@l 633 634 stw r0, 0(r9) /* Write to CCSRBARH */ 635 sync /* Make sure we write to CCSRBARH first */ 636 stw r1, 4(r9) /* Write to CCSRBARL */ 637 sync 638 639 /* 640 * Write a 1 to the commit bit (C) of CCSRAR at the old location. 641 * Follow this with a sync instruction. 642 */ 643 stw r2, 8(r9) 644 sync 645 646 /* Delete the temporary LAW */ 647delete_temp_law: 648 li r1, 0 649 stw r1, 0xc08(r8) 650 sync 651 stw r1, 0xc00(r8) 652 stw r1, 0xc04(r8) 653 sync 654 655#else /* #ifdef CONFIG_FSL_CORENET */ 656 657write_new_ccsrbar: 658 /* 659 * Read the current value of CCSRBAR using a load word instruction 660 * followed by an isync. This forces all accesses to configuration 661 * space to complete. 662 */ 663 sync 664 lwz r0, 0(r9) 665 isync 666 667/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ 668#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ 669 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) 670 671 /* Write the new value to CCSRBAR. */ 672 lis r0, CCSRBAR_PHYS_RS12@h 673 ori r0, r0, CCSRBAR_PHYS_RS12@l 674 stw r0, 0(r9) 675 sync 676 677 /* 678 * The manual says to perform a load of an address that does not 679 * access configuration space or the on-chip SRAM using an existing TLB, 680 * but that doesn't appear to be necessary. We will do the isync, 681 * though. 682 */ 683 isync 684 685 /* 686 * Read the contents of CCSRBAR from its new location, followed by 687 * another isync. 688 */ 689 lwz r0, 0(r8) 690 isync 691 692#endif /* #ifdef CONFIG_FSL_CORENET */ 693 694 /* Delete the temporary TLBs */ 695delete_temp_tlbs: 696 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 697 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 698 699#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ 700 701#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 702create_ccsr_l2_tlb: 703 /* 704 * Create a TLB for the MMR location of CCSR 705 * to access L2CSR0 register 706 */ 707 create_tlb0_entry 0, \ 708 0, BOOKE_PAGESZ_4K, \ 709 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ 710 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ 711 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 712 713enable_l2_cluster_l2: 714 /* enable L2 cache */ 715 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h 716 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l 717 li r4, 33 /* stash id */ 718 stw r4, 4(r3) 719 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h 720 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l 721 sync 722 stw r4, 0(r3) /* invalidate L2 */ 7231: sync 724 lwz r0, 0(r3) 725 twi 0, r0, 0 726 isync 727 and. r1, r0, r4 728 bne 1b 729 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h 730 ori r4, r4, (L2CSR0_L2REP_MODE)@l 731 sync 732 stw r4, 0(r3) /* enable L2 */ 733delete_ccsr_l2_tlb: 734 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 735#endif 736 737 /* 738 * Enable the L1. On e6500, this has to be done 739 * after the L2 is up. 740 */ 741 742#ifdef CONFIG_SYS_CACHE_STASHING 743 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 744 li r2,(32 + 0) 745 mtspr L1CSR2,r2 746#endif 747 748 /* Enable/invalidate the I-Cache */ 749 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 750 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 751 mtspr SPRN_L1CSR1,r2 7521: 753 mfspr r3,SPRN_L1CSR1 754 and. r1,r3,r2 755 bne 1b 756 757 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 758 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 759 mtspr SPRN_L1CSR1,r3 760 isync 7612: 762 mfspr r3,SPRN_L1CSR1 763 andi. r1,r3,L1CSR1_ICE@l 764 beq 2b 765 766 /* Enable/invalidate the D-Cache */ 767 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 768 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 769 mtspr SPRN_L1CSR0,r2 7701: 771 mfspr r3,SPRN_L1CSR0 772 and. r1,r3,r2 773 bne 1b 774 775 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 776 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 777 mtspr SPRN_L1CSR0,r3 778 isync 7792: 780 mfspr r3,SPRN_L1CSR0 781 andi. r1,r3,L1CSR0_DCE@l 782 beq 2b 783#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 784#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 785#define LAW_SIZE_1M 0x13 786#define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M) 787 788 cmpwi r27,0 789 beq 9f 790 791 /* 792 * Create a TLB entry for CCSR 793 * 794 * We're executing out of TLB1 entry in r14, and that's the only 795 * TLB entry that exists. To allocate some TLB entries for our 796 * own use, flip a bit high enough that we won't flip it again 797 * via incrementing. 798 */ 799 800 xori r8, r14, 32 801 lis r0, MAS0_TLBSEL(1)@h 802 rlwimi r0, r8, 16, MAS0_ESEL_MSK 803 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h 804 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l 805 lis r7, CONFIG_SYS_CCSRBAR@h 806 ori r7, r7, CONFIG_SYS_CCSRBAR@l 807 ori r2, r7, MAS2_I|MAS2_G 808 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h 809 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l 810 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 811 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 812 mtspr MAS0, r0 813 mtspr MAS1, r1 814 mtspr MAS2, r2 815 mtspr MAS3, r3 816 mtspr MAS7, r4 817 isync 818 tlbwe 819 isync 820 msync 821 822 /* Map DCSR temporarily to physical address zero */ 823 li r0, 0 824 lis r3, DCSRBAR_LAWAR@h 825 ori r3, r3, DCSRBAR_LAWAR@l 826 827 stw r0, 0xc00(r7) /* LAWBARH0 */ 828 stw r0, 0xc04(r7) /* LAWBARL0 */ 829 sync 830 stw r3, 0xc08(r7) /* LAWAR0 */ 831 832 /* Read back from LAWAR to ensure the update is complete. */ 833 lwz r3, 0xc08(r7) /* LAWAR0 */ 834 isync 835 836 /* Create a TLB entry for DCSR at zero */ 837 838 addi r9, r8, 1 839 lis r0, MAS0_TLBSEL(1)@h 840 rlwimi r0, r9, 16, MAS0_ESEL_MSK 841 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h 842 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l 843 li r6, 0 /* DCSR effective address */ 844 ori r2, r6, MAS2_I|MAS2_G 845 li r3, MAS3_SW|MAS3_SR 846 li r4, 0 847 mtspr MAS0, r0 848 mtspr MAS1, r1 849 mtspr MAS2, r2 850 mtspr MAS3, r3 851 mtspr MAS7, r4 852 isync 853 tlbwe 854 isync 855 msync 856 857 /* enable the timebase */ 858#define CTBENR 0xe2084 859 li r3, 1 860 addis r4, r7, CTBENR@ha 861 stw r3, CTBENR@l(r4) 862 lwz r3, CTBENR@l(r4) 863 twi 0,r3,0 864 isync 865 866 .macro erratum_set_ccsr offset value 867 addis r3, r7, \offset@ha 868 lis r4, \value@h 869 addi r3, r3, \offset@l 870 ori r4, r4, \value@l 871 bl erratum_set_value 872 .endm 873 874 .macro erratum_set_dcsr offset value 875 addis r3, r6, \offset@ha 876 lis r4, \value@h 877 addi r3, r3, \offset@l 878 ori r4, r4, \value@l 879 bl erratum_set_value 880 .endm 881 882 erratum_set_dcsr 0xb0e08 0xe0201800 883 erratum_set_dcsr 0xb0e18 0xe0201800 884 erratum_set_dcsr 0xb0e38 0xe0400000 885 erratum_set_dcsr 0xb0008 0x00900000 886 erratum_set_dcsr 0xb0e40 0xe00a0000 887 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 888#ifdef CONFIG_RAMBOOT_PBL 889 erratum_set_ccsr 0x10f00 0x495e5000 890#else 891 erratum_set_ccsr 0x10f00 0x415e5000 892#endif 893 erratum_set_ccsr 0x11f00 0x415e5000 894 895 /* Make temp mapping uncacheable again, if it was initially */ 896 bl 2f 8972: mflr r3 898 tlbsx 0, r3 899 mfspr r4, MAS2 900 rlwimi r4, r15, 0, MAS2_I 901 rlwimi r4, r15, 0, MAS2_G 902 mtspr MAS2, r4 903 isync 904 tlbwe 905 isync 906 msync 907 908 /* Clear the cache */ 909 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 910 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 911 sync 912 isync 913 mtspr SPRN_L1CSR1,r3 914 isync 9152: sync 916 mfspr r4,SPRN_L1CSR1 917 and. r4,r4,r3 918 bne 2b 919 920 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 921 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 922 sync 923 isync 924 mtspr SPRN_L1CSR1,r3 925 isync 9262: sync 927 mfspr r4,SPRN_L1CSR1 928 and. r4,r4,r3 929 beq 2b 930 931 /* Remove temporary mappings */ 932 lis r0, MAS0_TLBSEL(1)@h 933 rlwimi r0, r9, 16, MAS0_ESEL_MSK 934 li r3, 0 935 mtspr MAS0, r0 936 mtspr MAS1, r3 937 isync 938 tlbwe 939 isync 940 msync 941 942 li r3, 0 943 stw r3, 0xc08(r7) /* LAWAR0 */ 944 lwz r3, 0xc08(r7) 945 isync 946 947 lis r0, MAS0_TLBSEL(1)@h 948 rlwimi r0, r8, 16, MAS0_ESEL_MSK 949 li r3, 0 950 mtspr MAS0, r0 951 mtspr MAS1, r3 952 isync 953 tlbwe 954 isync 955 msync 956 957 b 9f 958 959 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */ 960erratum_set_value: 961 /* Lock two cache lines into I-Cache */ 962 sync 963 mfspr r11, SPRN_L1CSR1 964 rlwinm r11, r11, 0, ~L1CSR1_ICUL 965 sync 966 isync 967 mtspr SPRN_L1CSR1, r11 968 isync 969 970 mflr r12 971 bl 5f 9725: mflr r5 973 addi r5, r5, 2f - 5b 974 icbtls 0, 0, r5 975 addi r5, r5, 64 976 977 sync 978 mfspr r11, SPRN_L1CSR1 9793: andi. r11, r11, L1CSR1_ICUL 980 bne 3b 981 982 icbtls 0, 0, r5 983 addi r5, r5, 64 984 985 sync 986 mfspr r11, SPRN_L1CSR1 9873: andi. r11, r11, L1CSR1_ICUL 988 bne 3b 989 990 b 2f 991 .align 6 992 /* Inside a locked cacheline, wait a while, write, then wait a while */ 9932: sync 994 995 mfspr r5, SPRN_TBRL 996 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ 9974: mfspr r5, SPRN_TBRL 998 subf. r5, r5, r11 999 bgt 4b 1000 1001 stw r4, 0(r3) 1002 1003 mfspr r5, SPRN_TBRL 1004 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ 10054: mfspr r5, SPRN_TBRL 1006 subf. r5, r5, r11 1007 bgt 4b 1008 1009 sync 1010 1011 /* 1012 * Fill out the rest of this cache line and the next with nops, 1013 * to ensure that nothing outside the locked area will be 1014 * fetched due to a branch. 1015 */ 1016 .rept 19 1017 nop 1018 .endr 1019 1020 sync 1021 mfspr r11, SPRN_L1CSR1 1022 rlwinm r11, r11, 0, ~L1CSR1_ICUL 1023 sync 1024 isync 1025 mtspr SPRN_L1CSR1, r11 1026 isync 1027 1028 mtlr r12 1029 blr 1030 10319: 1032#endif 1033 1034create_init_ram_area: 1035 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 1036 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 1037 1038#ifdef NOR_BOOT 1039 /* create a temp mapping in AS=1 to the 4M boot window */ 1040 create_tlb1_entry 15, \ 1041 1, BOOKE_PAGESZ_4M, \ 1042 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ 1043 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 1044 0, r6 1045 1046#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 1047 /* create a temp mapping in AS = 1 for Flash mapping 1048 * created by PBL for ISBC code 1049 */ 1050 create_tlb1_entry 15, \ 1051 1, BOOKE_PAGESZ_1M, \ 1052 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ 1053 CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 1054 0, r6 1055#else 1056 /* 1057 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main 1058 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. 1059 */ 1060 create_tlb1_entry 15, \ 1061 1, BOOKE_PAGESZ_1M, \ 1062 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ 1063 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 1064 0, r6 1065#endif 1066 1067 /* create a temp mapping in AS=1 to the stack */ 1068#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ 1069 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) 1070 create_tlb1_entry 14, \ 1071 1, BOOKE_PAGESZ_16K, \ 1072 CONFIG_SYS_INIT_RAM_ADDR, 0, \ 1073 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ 1074 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 1075 1076#else 1077 create_tlb1_entry 14, \ 1078 1, BOOKE_PAGESZ_16K, \ 1079 CONFIG_SYS_INIT_RAM_ADDR, 0, \ 1080 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ 1081 0, r6 1082#endif 1083 1084 lis r6,MSR_IS|MSR_DS|MSR_DE@h 1085 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l 1086 lis r7,switch_as@h 1087 ori r7,r7,switch_as@l 1088 1089 mtspr SPRN_SRR0,r7 1090 mtspr SPRN_SRR1,r6 1091 rfi 1092 1093switch_as: 1094/* L1 DCache is used for initial RAM */ 1095 1096 /* Allocate Initial RAM in data cache. 1097 */ 1098 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1099 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1100 mfspr r2, L1CFG0 1101 andi. r2, r2, 0x1ff 1102 /* cache size * 1024 / (2 * L1 line size) */ 1103 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 1104 mtctr r2 1105 li r0,0 11061: 1107 dcbz r0,r3 1108 dcbtls 0,r0,r3 1109 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1110 bdnz 1b 1111 1112 /* Jump out the last 4K page and continue to 'normal' start */ 1113#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 1114 /* We assume that we're already running at the address we're linked at */ 1115 b _start_cont 1116#else 1117 /* Calculate absolute address in FLASH and jump there */ 1118 /*--------------------------------------------------------------*/ 1119 lis r3,CONFIG_SYS_MONITOR_BASE@h 1120 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 1121 addi r3,r3,_start_cont - _start 1122 mtlr r3 1123 blr 1124#endif 1125 1126 .text 1127 .globl _start 1128_start: 1129 .long 0x27051956 /* U-BOOT Magic Number */ 1130 .globl version_string 1131version_string: 1132 .ascii U_BOOT_VERSION_STRING, "\0" 1133 1134 .align 4 1135 .globl _start_cont 1136_start_cont: 1137 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 1138 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h 1139 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ 1140 li r0,0 1141 stw r0,0(r3) /* Terminate Back Chain */ 1142 stw r0,+4(r3) /* NULL return address. */ 1143 mr r1,r3 /* Transfer to SP(r1) */ 1144 1145 GET_GOT 1146 1147 /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */ 1148 mr r3, r24 1149 1150 bl cpu_init_early_f 1151 1152 /* switch back to AS = 0 */ 1153 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 1154 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 1155 mtmsr r3 1156 isync 1157 1158 bl cpu_init_f /* return boot_flag for calling board_init_f */ 1159 bl board_init_f 1160 isync 1161 1162 /* NOTREACHED - board_init_f() does not return */ 1163 1164#ifndef MINIMAL_SPL 1165 .globl _start_of_vectors 1166_start_of_vectors: 1167 1168/* Critical input. */ 1169 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 1170 1171/* Machine check */ 1172 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 1173 1174/* Data Storage exception. */ 1175 STD_EXCEPTION(0x0300, DataStorage, UnknownException) 1176 1177/* Instruction Storage exception. */ 1178 STD_EXCEPTION(0x0400, InstStorage, UnknownException) 1179 1180/* External Interrupt exception. */ 1181 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 1182 1183/* Alignment exception. */ 1184Alignment: 1185 EXCEPTION_PROLOG(SRR0, SRR1) 1186 mfspr r4,DAR 1187 stw r4,_DAR(r21) 1188 mfspr r5,DSISR 1189 stw r5,_DSISR(r21) 1190 addi r3,r1,STACK_FRAME_OVERHEAD 1191 EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException, 1192 MSR_KERNEL, COPY_EE) 1193 1194/* Program check exception */ 1195ProgramCheck: 1196 EXCEPTION_PROLOG(SRR0, SRR1) 1197 addi r3,r1,STACK_FRAME_OVERHEAD 1198 EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException, 1199 MSR_KERNEL, COPY_EE) 1200 1201 /* No FPU on MPC85xx. This exception is not supposed to happen. 1202 */ 1203 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 1204 1205/* 1206 * r0 - SYSCALL number 1207 * r3-... arguments 1208 */ 1209SystemCall: 1210 addis r11,r0,0 /* get functions table addr */ 1211 ori r11,r11,0 /* Note: this code is patched in trap_init */ 1212 addis r12,r0,0 /* get number of functions */ 1213 ori r12,r12,0 1214 1215 cmplw 0,r0,r12 1216 bge 1f 1217 1218 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 1219 add r11,r11,r0 1220 lwz r11,0(r11) 1221 1222 li r20,0xd00-4 /* Get stack pointer */ 1223 lwz r12,0(r20) 1224 subi r12,r12,12 /* Adjust stack pointer */ 1225 li r0,0xc00+_end_back-SystemCall 1226 cmplw 0,r0,r12 /* Check stack overflow */ 1227 bgt 1f 1228 stw r12,0(r20) 1229 1230 mflr r0 1231 stw r0,0(r12) 1232 mfspr r0,SRR0 1233 stw r0,4(r12) 1234 mfspr r0,SRR1 1235 stw r0,8(r12) 1236 1237 li r12,0xc00+_back-SystemCall 1238 mtlr r12 1239 mtspr SRR0,r11 1240 12411: SYNC 1242 rfi 1243_back: 1244 1245 mfmsr r11 /* Disable interrupts */ 1246 li r12,0 1247 ori r12,r12,MSR_EE 1248 andc r11,r11,r12 1249 SYNC /* Some chip revs need this... */ 1250 mtmsr r11 1251 SYNC 1252 1253 li r12,0xd00-4 /* restore regs */ 1254 lwz r12,0(r12) 1255 1256 lwz r11,0(r12) 1257 mtlr r11 1258 lwz r11,4(r12) 1259 mtspr SRR0,r11 1260 lwz r11,8(r12) 1261 mtspr SRR1,r11 1262 1263 addi r12,r12,12 /* Adjust stack pointer */ 1264 li r20,0xd00-4 1265 stw r12,0(r20) 1266 1267 SYNC 1268 rfi 1269_end_back: 1270 1271 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 1272 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 1273 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 1274 1275 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 1276 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 1277 1278 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 1279 1280 .globl _end_of_vectors 1281_end_of_vectors: 1282 1283 1284 . = . + (0x100 - ( . & 0xff )) /* align for debug */ 1285 1286/* 1287 * This code finishes saving the registers to the exception frame 1288 * and jumps to the appropriate handler for the exception. 1289 * Register r21 is pointer into trap frame, r1 has new stack pointer. 1290 * r23 is the address of the handler. 1291 */ 1292 .globl transfer_to_handler 1293transfer_to_handler: 1294 SAVE_GPR(7, r21) 1295 SAVE_4GPRS(8, r21) 1296 SAVE_8GPRS(12, r21) 1297 SAVE_8GPRS(24, r21) 1298 1299 li r22,0 1300 stw r22,RESULT(r21) 1301 mtspr SPRG2,r22 /* r1 is now kernel sp */ 1302 1303 mtctr r23 /* virtual address of handler */ 1304 mtmsr r20 1305 bctrl 1306 1307int_return: 1308 mfmsr r28 /* Disable interrupts */ 1309 li r4,0 1310 ori r4,r4,MSR_EE 1311 andc r28,r28,r4 1312 SYNC /* Some chip revs need this... */ 1313 mtmsr r28 1314 SYNC 1315 lwz r2,_CTR(r1) 1316 lwz r0,_LINK(r1) 1317 mtctr r2 1318 mtlr r0 1319 lwz r2,_XER(r1) 1320 lwz r0,_CCR(r1) 1321 mtspr XER,r2 1322 mtcrf 0xFF,r0 1323 REST_10GPRS(3, r1) 1324 REST_10GPRS(13, r1) 1325 REST_8GPRS(23, r1) 1326 REST_GPR(31, r1) 1327 lwz r2,_NIP(r1) /* Restore environment */ 1328 lwz r0,_MSR(r1) 1329 mtspr SRR0,r2 1330 mtspr SRR1,r0 1331 lwz r0,GPR0(r1) 1332 lwz r2,GPR2(r1) 1333 lwz r1,GPR1(r1) 1334 SYNC 1335 rfi 1336 1337crit_return: 1338 mfmsr r28 /* Disable interrupts */ 1339 li r4,0 1340 ori r4,r4,MSR_EE 1341 andc r28,r28,r4 1342 SYNC /* Some chip revs need this... */ 1343 mtmsr r28 1344 SYNC 1345 lwz r2,_CTR(r1) 1346 lwz r0,_LINK(r1) 1347 mtctr r2 1348 mtlr r0 1349 lwz r2,_XER(r1) 1350 lwz r0,_CCR(r1) 1351 mtspr XER,r2 1352 mtcrf 0xFF,r0 1353 REST_10GPRS(3, r1) 1354 REST_10GPRS(13, r1) 1355 REST_8GPRS(23, r1) 1356 REST_GPR(31, r1) 1357 lwz r2,_NIP(r1) /* Restore environment */ 1358 lwz r0,_MSR(r1) 1359 mtspr SPRN_CSRR0,r2 1360 mtspr SPRN_CSRR1,r0 1361 lwz r0,GPR0(r1) 1362 lwz r2,GPR2(r1) 1363 lwz r1,GPR1(r1) 1364 SYNC 1365 rfci 1366 1367mck_return: 1368 mfmsr r28 /* Disable interrupts */ 1369 li r4,0 1370 ori r4,r4,MSR_EE 1371 andc r28,r28,r4 1372 SYNC /* Some chip revs need this... */ 1373 mtmsr r28 1374 SYNC 1375 lwz r2,_CTR(r1) 1376 lwz r0,_LINK(r1) 1377 mtctr r2 1378 mtlr r0 1379 lwz r2,_XER(r1) 1380 lwz r0,_CCR(r1) 1381 mtspr XER,r2 1382 mtcrf 0xFF,r0 1383 REST_10GPRS(3, r1) 1384 REST_10GPRS(13, r1) 1385 REST_8GPRS(23, r1) 1386 REST_GPR(31, r1) 1387 lwz r2,_NIP(r1) /* Restore environment */ 1388 lwz r0,_MSR(r1) 1389 mtspr SPRN_MCSRR0,r2 1390 mtspr SPRN_MCSRR1,r0 1391 lwz r0,GPR0(r1) 1392 lwz r2,GPR2(r1) 1393 lwz r1,GPR1(r1) 1394 SYNC 1395 rfmci 1396 1397/* Cache functions. 1398*/ 1399.globl flush_icache 1400flush_icache: 1401.globl invalidate_icache 1402invalidate_icache: 1403 mfspr r0,L1CSR1 1404 ori r0,r0,L1CSR1_ICFI 1405 msync 1406 isync 1407 mtspr L1CSR1,r0 1408 isync 1409 blr /* entire I cache */ 1410 1411.globl invalidate_dcache 1412invalidate_dcache: 1413 mfspr r0,L1CSR0 1414 ori r0,r0,L1CSR0_DCFI 1415 msync 1416 isync 1417 mtspr L1CSR0,r0 1418 isync 1419 blr 1420 1421 .globl icache_enable 1422icache_enable: 1423 mflr r8 1424 bl invalidate_icache 1425 mtlr r8 1426 isync 1427 mfspr r4,L1CSR1 1428 ori r4,r4,0x0001 1429 oris r4,r4,0x0001 1430 mtspr L1CSR1,r4 1431 isync 1432 blr 1433 1434 .globl icache_disable 1435icache_disable: 1436 mfspr r0,L1CSR1 1437 lis r3,0 1438 ori r3,r3,L1CSR1_ICE 1439 andc r0,r0,r3 1440 mtspr L1CSR1,r0 1441 isync 1442 blr 1443 1444 .globl icache_status 1445icache_status: 1446 mfspr r3,L1CSR1 1447 andi. r3,r3,L1CSR1_ICE 1448 blr 1449 1450 .globl dcache_enable 1451dcache_enable: 1452 mflr r8 1453 bl invalidate_dcache 1454 mtlr r8 1455 isync 1456 mfspr r0,L1CSR0 1457 ori r0,r0,0x0001 1458 oris r0,r0,0x0001 1459 msync 1460 isync 1461 mtspr L1CSR0,r0 1462 isync 1463 blr 1464 1465 .globl dcache_disable 1466dcache_disable: 1467 mfspr r3,L1CSR0 1468 lis r4,0 1469 ori r4,r4,L1CSR0_DCE 1470 andc r3,r3,r4 1471 mtspr L1CSR0,r3 1472 isync 1473 blr 1474 1475 .globl dcache_status 1476dcache_status: 1477 mfspr r3,L1CSR0 1478 andi. r3,r3,L1CSR0_DCE 1479 blr 1480 1481 .globl get_pir 1482get_pir: 1483 mfspr r3,PIR 1484 blr 1485 1486 .globl get_pvr 1487get_pvr: 1488 mfspr r3,PVR 1489 blr 1490 1491 .globl get_svr 1492get_svr: 1493 mfspr r3,SVR 1494 blr 1495 1496 .globl wr_tcr 1497wr_tcr: 1498 mtspr TCR,r3 1499 blr 1500 1501/*------------------------------------------------------------------------------- */ 1502/* Function: in8 */ 1503/* Description: Input 8 bits */ 1504/*------------------------------------------------------------------------------- */ 1505 .globl in8 1506in8: 1507 lbz r3,0x0000(r3) 1508 blr 1509 1510/*------------------------------------------------------------------------------- */ 1511/* Function: out8 */ 1512/* Description: Output 8 bits */ 1513/*------------------------------------------------------------------------------- */ 1514 .globl out8 1515out8: 1516 stb r4,0x0000(r3) 1517 sync 1518 blr 1519 1520/*------------------------------------------------------------------------------- */ 1521/* Function: out16 */ 1522/* Description: Output 16 bits */ 1523/*------------------------------------------------------------------------------- */ 1524 .globl out16 1525out16: 1526 sth r4,0x0000(r3) 1527 sync 1528 blr 1529 1530/*------------------------------------------------------------------------------- */ 1531/* Function: out16r */ 1532/* Description: Byte reverse and output 16 bits */ 1533/*------------------------------------------------------------------------------- */ 1534 .globl out16r 1535out16r: 1536 sthbrx r4,r0,r3 1537 sync 1538 blr 1539 1540/*------------------------------------------------------------------------------- */ 1541/* Function: out32 */ 1542/* Description: Output 32 bits */ 1543/*------------------------------------------------------------------------------- */ 1544 .globl out32 1545out32: 1546 stw r4,0x0000(r3) 1547 sync 1548 blr 1549 1550/*------------------------------------------------------------------------------- */ 1551/* Function: out32r */ 1552/* Description: Byte reverse and output 32 bits */ 1553/*------------------------------------------------------------------------------- */ 1554 .globl out32r 1555out32r: 1556 stwbrx r4,r0,r3 1557 sync 1558 blr 1559 1560/*------------------------------------------------------------------------------- */ 1561/* Function: in16 */ 1562/* Description: Input 16 bits */ 1563/*------------------------------------------------------------------------------- */ 1564 .globl in16 1565in16: 1566 lhz r3,0x0000(r3) 1567 blr 1568 1569/*------------------------------------------------------------------------------- */ 1570/* Function: in16r */ 1571/* Description: Input 16 bits and byte reverse */ 1572/*------------------------------------------------------------------------------- */ 1573 .globl in16r 1574in16r: 1575 lhbrx r3,r0,r3 1576 blr 1577 1578/*------------------------------------------------------------------------------- */ 1579/* Function: in32 */ 1580/* Description: Input 32 bits */ 1581/*------------------------------------------------------------------------------- */ 1582 .globl in32 1583in32: 1584 lwz 3,0x0000(3) 1585 blr 1586 1587/*------------------------------------------------------------------------------- */ 1588/* Function: in32r */ 1589/* Description: Input 32 bits and byte reverse */ 1590/*------------------------------------------------------------------------------- */ 1591 .globl in32r 1592in32r: 1593 lwbrx r3,r0,r3 1594 blr 1595#endif /* !MINIMAL_SPL */ 1596 1597/*------------------------------------------------------------------------------*/ 1598 1599/* 1600 * void write_tlb(mas0, mas1, mas2, mas3, mas7) 1601 */ 1602 .globl write_tlb 1603write_tlb: 1604 mtspr MAS0,r3 1605 mtspr MAS1,r4 1606 mtspr MAS2,r5 1607 mtspr MAS3,r6 1608#ifdef CONFIG_ENABLE_36BIT_PHYS 1609 mtspr MAS7,r7 1610#endif 1611 li r3,0 1612#ifdef CONFIG_SYS_BOOK3E_HV 1613 mtspr MAS8,r3 1614#endif 1615 isync 1616 tlbwe 1617 msync 1618 isync 1619 blr 1620 1621/* 1622 * void relocate_code (addr_sp, gd, addr_moni) 1623 * 1624 * This "function" does not return, instead it continues in RAM 1625 * after relocating the monitor code. 1626 * 1627 * r3 = dest 1628 * r4 = src 1629 * r5 = length in bytes 1630 * r6 = cachelinesize 1631 */ 1632 .globl relocate_code 1633relocate_code: 1634 mr r1,r3 /* Set new stack pointer */ 1635 mr r9,r4 /* Save copy of Init Data pointer */ 1636 mr r10,r5 /* Save copy of Destination Address */ 1637 1638 GET_GOT 1639#ifndef CONFIG_SPL_SKIP_RELOCATE 1640 mr r3,r5 /* Destination Address */ 1641 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1642 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 1643 lwz r5,GOT(__init_end) 1644 sub r5,r5,r4 1645 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 1646 1647 /* 1648 * Fix GOT pointer: 1649 * 1650 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1651 * 1652 * Offset: 1653 */ 1654 sub r15,r10,r4 1655 1656 /* First our own GOT */ 1657 add r12,r12,r15 1658 /* the the one used by the C code */ 1659 add r30,r30,r15 1660 1661 /* 1662 * Now relocate code 1663 */ 1664 1665 cmplw cr1,r3,r4 1666 addi r0,r5,3 1667 srwi. r0,r0,2 1668 beq cr1,4f /* In place copy is not necessary */ 1669 beq 7f /* Protect against 0 count */ 1670 mtctr r0 1671 bge cr1,2f 1672 1673 la r8,-4(r4) 1674 la r7,-4(r3) 16751: lwzu r0,4(r8) 1676 stwu r0,4(r7) 1677 bdnz 1b 1678 b 4f 1679 16802: slwi r0,r0,2 1681 add r8,r4,r0 1682 add r7,r3,r0 16833: lwzu r0,-4(r8) 1684 stwu r0,-4(r7) 1685 bdnz 3b 1686 1687/* 1688 * Now flush the cache: note that we must start from a cache aligned 1689 * address. Otherwise we might miss one cache line. 1690 */ 16914: cmpwi r6,0 1692 add r5,r3,r5 1693 beq 7f /* Always flush prefetch queue in any case */ 1694 subi r0,r6,1 1695 andc r3,r3,r0 1696 mr r4,r3 16975: dcbst 0,r4 1698 add r4,r4,r6 1699 cmplw r4,r5 1700 blt 5b 1701 sync /* Wait for all dcbst to complete on bus */ 1702 mr r4,r3 17036: icbi 0,r4 1704 add r4,r4,r6 1705 cmplw r4,r5 1706 blt 6b 17077: sync /* Wait for all icbi to complete on bus */ 1708 isync 1709 1710/* 1711 * We are done. Do not return, instead branch to second part of board 1712 * initialization, now running from RAM. 1713 */ 1714 1715 addi r0,r10,in_ram - _start 1716 1717 /* 1718 * As IVPR is going to point RAM address, 1719 * Make sure IVOR15 has valid opcode to support debugger 1720 */ 1721 mtspr IVOR15,r0 1722 1723 /* 1724 * Re-point the IVPR at RAM 1725 */ 1726 mtspr IVPR,r10 1727 1728 mtlr r0 1729 blr /* NEVER RETURNS! */ 1730#endif 1731 .globl in_ram 1732in_ram: 1733 1734 /* 1735 * Relocation Function, r12 point to got2+0x8000 1736 * 1737 * Adjust got2 pointers, no need to check for 0, this code 1738 * already puts a few entries in the table. 1739 */ 1740 li r0,__got2_entries@sectoff@l 1741 la r3,GOT(_GOT2_TABLE_) 1742 lwz r11,GOT(_GOT2_TABLE_) 1743 mtctr r0 1744 sub r11,r3,r11 1745 addi r3,r3,-4 17461: lwzu r0,4(r3) 1747 cmpwi r0,0 1748 beq- 2f 1749 add r0,r0,r11 1750 stw r0,0(r3) 17512: bdnz 1b 1752 1753 /* 1754 * Now adjust the fixups and the pointers to the fixups 1755 * in case we need to move ourselves again. 1756 */ 1757 li r0,__fixup_entries@sectoff@l 1758 lwz r3,GOT(_FIXUP_TABLE_) 1759 cmpwi r0,0 1760 mtctr r0 1761 addi r3,r3,-4 1762 beq 4f 17633: lwzu r4,4(r3) 1764 lwzux r0,r4,r11 1765 cmpwi r0,0 1766 add r0,r0,r11 1767 stw r4,0(r3) 1768 beq- 5f 1769 stw r0,0(r4) 17705: bdnz 3b 17714: 1772clear_bss: 1773 /* 1774 * Now clear BSS segment 1775 */ 1776 lwz r3,GOT(__bss_start) 1777 lwz r4,GOT(__bss_end) 1778 1779 cmplw 0,r3,r4 1780 beq 6f 1781 1782 li r0,0 17835: 1784 stw r0,0(r3) 1785 addi r3,r3,4 1786 cmplw 0,r3,r4 1787 blt 5b 17886: 1789 1790 mr r3,r9 /* Init Data pointer */ 1791 mr r4,r10 /* Destination Address */ 1792 bl board_init_r 1793 1794#ifndef MINIMAL_SPL 1795 /* 1796 * Copy exception vector code to low memory 1797 * 1798 * r3: dest_addr 1799 * r7: source address, r8: end address, r9: target address 1800 */ 1801 .globl trap_init 1802trap_init: 1803 /* Update IVORs as per relocation */ 1804 mtspr IVPR,r3 1805 1806 li r4,CriticalInput@l 1807 mtspr IVOR0,r4 /* 0: Critical input */ 1808 li r4,MachineCheck@l 1809 mtspr IVOR1,r4 /* 1: Machine check */ 1810 li r4,DataStorage@l 1811 mtspr IVOR2,r4 /* 2: Data storage */ 1812 li r4,InstStorage@l 1813 mtspr IVOR3,r4 /* 3: Instruction storage */ 1814 li r4,ExtInterrupt@l 1815 mtspr IVOR4,r4 /* 4: External interrupt */ 1816 li r4,Alignment@l 1817 mtspr IVOR5,r4 /* 5: Alignment */ 1818 li r4,ProgramCheck@l 1819 mtspr IVOR6,r4 /* 6: Program check */ 1820 li r4,FPUnavailable@l 1821 mtspr IVOR7,r4 /* 7: floating point unavailable */ 1822 li r4,SystemCall@l 1823 mtspr IVOR8,r4 /* 8: System call */ 1824 /* 9: Auxiliary processor unavailable(unsupported) */ 1825 li r4,Decrementer@l 1826 mtspr IVOR10,r4 /* 10: Decrementer */ 1827 li r4,IntervalTimer@l 1828 mtspr IVOR11,r4 /* 11: Interval timer */ 1829 li r4,WatchdogTimer@l 1830 mtspr IVOR12,r4 /* 12: Watchdog timer */ 1831 li r4,DataTLBError@l 1832 mtspr IVOR13,r4 /* 13: Data TLB error */ 1833 li r4,InstructionTLBError@l 1834 mtspr IVOR14,r4 /* 14: Instruction TLB error */ 1835 li r4,DebugBreakpoint@l 1836 mtspr IVOR15,r4 /* 15: Debug */ 1837 1838 blr 1839 1840.globl unlock_ram_in_cache 1841unlock_ram_in_cache: 1842 /* invalidate the INIT_RAM section */ 1843 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1844 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1845 mfspr r4,L1CFG0 1846 andi. r4,r4,0x1ff 1847 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1848 mtctr r4 18491: dcbi r0,r3 1850 dcblc r0,r3 1851 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1852 bdnz 1b 1853 sync 1854 1855 /* Invalidate the TLB entries for the cache */ 1856 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1857 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1858 tlbivax 0,r3 1859 addi r3,r3,0x1000 1860 tlbivax 0,r3 1861 addi r3,r3,0x1000 1862 tlbivax 0,r3 1863 addi r3,r3,0x1000 1864 tlbivax 0,r3 1865 isync 1866 blr 1867 1868.globl flush_dcache 1869flush_dcache: 1870 mfspr r3,SPRN_L1CFG0 1871 1872 rlwinm r5,r3,9,3 /* Extract cache block size */ 1873 twlgti r5,1 /* Only 32 and 64 byte cache blocks 1874 * are currently defined. 1875 */ 1876 li r4,32 1877 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1878 * log2(number of ways) 1879 */ 1880 slw r5,r4,r5 /* r5 = cache block size */ 1881 1882 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1883 mulli r7,r7,13 /* An 8-way cache will require 13 1884 * loads per set. 1885 */ 1886 slw r7,r7,r6 1887 1888 /* save off HID0 and set DCFA */ 1889 mfspr r8,SPRN_HID0 1890 ori r9,r8,HID0_DCFA@l 1891 mtspr SPRN_HID0,r9 1892 isync 1893 1894 lis r4,0 1895 mtctr r7 1896 18971: lwz r3,0(r4) /* Load... */ 1898 add r4,r4,r5 1899 bdnz 1b 1900 1901 msync 1902 lis r4,0 1903 mtctr r7 1904 19051: dcbf 0,r4 /* ...and flush. */ 1906 add r4,r4,r5 1907 bdnz 1b 1908 1909 /* restore HID0 */ 1910 mtspr SPRN_HID0,r8 1911 isync 1912 1913 blr 1914#endif /* !MINIMAL_SPL */ 1915