1/* 2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. 3 * Copyright (C) 2003 Motorola,Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 25 * 26 * The processor starts at 0xfffffffc and the code is first executed in the 27 * last 4K page(0xfffff000-0xffffffff) in flash/rom. 28 * 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <mpc85xx.h> 34#include <version.h> 35 36#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37 38#include <ppc_asm.tmpl> 39#include <ppc_defs.h> 40 41#include <asm/cache.h> 42#include <asm/mmu.h> 43 44#undef MSR_KERNEL 45#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 46 47/* 48 * Set up GOT: Global Offset Table 49 * 50 * Use r12 to access the GOT 51 */ 52 START_GOT 53 GOT_ENTRY(_GOT2_TABLE_) 54 GOT_ENTRY(_FIXUP_TABLE_) 55 56#ifndef CONFIG_NAND_SPL 57 GOT_ENTRY(_start) 58 GOT_ENTRY(_start_of_vectors) 59 GOT_ENTRY(_end_of_vectors) 60 GOT_ENTRY(transfer_to_handler) 61#endif 62 63 GOT_ENTRY(__init_end) 64 GOT_ENTRY(__bss_end__) 65 GOT_ENTRY(__bss_start) 66 END_GOT 67 68/* 69 * e500 Startup -- after reset only the last 4KB of the effective 70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 71 * section is located at THIS LAST page and basically does three 72 * things: clear some registers, set up exception tables and 73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 74 * continue the boot procedure. 75 76 * Once the boot rom is mapped by TLB entries we can proceed 77 * with normal startup. 78 * 79 */ 80 81 .section .bootpg,"ax" 82 .globl _start_e500 83 84_start_e500: 85/* Enable debug exception */ 86 li r1,MSR_DE 87 mtmsr r1 88 89#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) 90 /* ISBC uses L2 as stack. 91 * Disable L2 cache here so that u-boot can enable it later 92 * as part of it's normal flow 93 */ 94 95 /* Check if L2 is enabled */ 96 mfspr r3, SPRN_L2CSR0 97 lis r2, L2CSR0_L2E@h 98 ori r2, r2, L2CSR0_L2E@l 99 and. r4, r3, r2 100 beq l2_disabled 101 102 mfspr r3, SPRN_L2CSR0 103 /* Flush L2 cache */ 104 lis r2,(L2CSR0_L2FL)@h 105 ori r2, r2, (L2CSR0_L2FL)@l 106 or r3, r2, r3 107 sync 108 isync 109 mtspr SPRN_L2CSR0,r3 110 isync 1111: 112 mfspr r3, SPRN_L2CSR0 113 and. r1, r3, r2 114 bne 1b 115 116 mfspr r3, SPRN_L2CSR0 117 lis r2, L2CSR0_L2E@h 118 ori r2, r2, L2CSR0_L2E@l 119 andc r4, r3, r2 120 sync 121 isync 122 mtspr SPRN_L2CSR0,r4 123 isync 124 125l2_disabled: 126#endif 127 128/* clear registers/arrays not reset by hardware */ 129 130 /* L1 */ 131 li r0,2 132 mtspr L1CSR0,r0 /* invalidate d-cache */ 133 mtspr L1CSR1,r0 /* invalidate i-cache */ 134 135 mfspr r1,DBSR 136 mtspr DBSR,r1 /* Clear all valid bits */ 137 138 /* 139 * Enable L1 Caches early 140 * 141 */ 142 143#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) 144 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 145 li r2,(32 + 0) 146 mtspr L1CSR2,r2 147#endif 148 149 /* Enable/invalidate the I-Cache */ 150 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 151 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 152 mtspr SPRN_L1CSR1,r2 1531: 154 mfspr r3,SPRN_L1CSR1 155 and. r1,r3,r2 156 bne 1b 157 158 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 159 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 160 mtspr SPRN_L1CSR1,r3 161 isync 1622: 163 mfspr r3,SPRN_L1CSR1 164 andi. r1,r3,L1CSR1_ICE@l 165 beq 2b 166 167 /* Enable/invalidate the D-Cache */ 168 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 169 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 170 mtspr SPRN_L1CSR0,r2 1711: 172 mfspr r3,SPRN_L1CSR0 173 and. r1,r3,r2 174 bne 1b 175 176 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 177 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 178 mtspr SPRN_L1CSR0,r3 179 isync 1802: 181 mfspr r3,SPRN_L1CSR0 182 andi. r1,r3,L1CSR0_DCE@l 183 beq 2b 184 185/* 186 * Ne need to setup interrupt vector for NAND SPL 187 * because NAND SPL never compiles it. 188 */ 189#if !defined(CONFIG_NAND_SPL) 190 /* Setup interrupt vectors */ 191 lis r1,CONFIG_SYS_MONITOR_BASE@h 192 mtspr IVPR,r1 193 194 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h 195 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l 196 197 addi r4,r3,CriticalInput - _start + _START_OFFSET 198 mtspr IVOR0,r4 /* 0: Critical input */ 199 addi r4,r3,MachineCheck - _start + _START_OFFSET 200 mtspr IVOR1,r4 /* 1: Machine check */ 201 addi r4,r3,DataStorage - _start + _START_OFFSET 202 mtspr IVOR2,r4 /* 2: Data storage */ 203 addi r4,r3,InstStorage - _start + _START_OFFSET 204 mtspr IVOR3,r4 /* 3: Instruction storage */ 205 addi r4,r3,ExtInterrupt - _start + _START_OFFSET 206 mtspr IVOR4,r4 /* 4: External interrupt */ 207 addi r4,r3,Alignment - _start + _START_OFFSET 208 mtspr IVOR5,r4 /* 5: Alignment */ 209 addi r4,r3,ProgramCheck - _start + _START_OFFSET 210 mtspr IVOR6,r4 /* 6: Program check */ 211 addi r4,r3,FPUnavailable - _start + _START_OFFSET 212 mtspr IVOR7,r4 /* 7: floating point unavailable */ 213 addi r4,r3,SystemCall - _start + _START_OFFSET 214 mtspr IVOR8,r4 /* 8: System call */ 215 /* 9: Auxiliary processor unavailable(unsupported) */ 216 addi r4,r3,Decrementer - _start + _START_OFFSET 217 mtspr IVOR10,r4 /* 10: Decrementer */ 218 addi r4,r3,IntervalTimer - _start + _START_OFFSET 219 mtspr IVOR11,r4 /* 11: Interval timer */ 220 addi r4,r3,WatchdogTimer - _start + _START_OFFSET 221 mtspr IVOR12,r4 /* 12: Watchdog timer */ 222 addi r4,r3,DataTLBError - _start + _START_OFFSET 223 mtspr IVOR13,r4 /* 13: Data TLB error */ 224 addi r4,r3,InstructionTLBError - _start + _START_OFFSET 225 mtspr IVOR14,r4 /* 14: Instruction TLB error */ 226 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET 227 mtspr IVOR15,r4 /* 15: Debug */ 228#endif 229 230 /* Clear and set up some registers. */ 231 li r0,0x0000 232 lis r1,0xffff 233 mtspr DEC,r0 /* prevent dec exceptions */ 234 mttbl r0 /* prevent fit & wdt exceptions */ 235 mttbu r0 236 mtspr TSR,r1 /* clear all timer exception status */ 237 mtspr TCR,r0 /* disable all */ 238 mtspr ESR,r0 /* clear exception syndrome register */ 239 mtspr MCSR,r0 /* machine check syndrome register */ 240 mtxer r0 /* clear integer exception register */ 241 242#ifdef CONFIG_SYS_BOOK3E_HV 243 mtspr MAS8,r0 /* make sure MAS8 is clear */ 244#endif 245 246 /* Enable Time Base and Select Time Base Clock */ 247 lis r0,HID0_EMCP@h /* Enable machine check */ 248#if defined(CONFIG_ENABLE_36BIT_PHYS) 249 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 250#endif 251#ifndef CONFIG_E500MC 252 ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 253#endif 254 mtspr HID0,r0 255 256#ifndef CONFIG_E500MC 257 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 258 mfspr r3,PVR 259 andi. r3,r3, 0xff 260 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 261 blt 1f 262 /* Set MBDD bit also */ 263 ori r0, r0, HID1_MBDD@l 2641: 265 mtspr HID1,r0 266#endif 267 268#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 269 mfspr r3,977 270 oris r3,r3,0x0100 271 mtspr 977,r3 272#endif 273 274 /* Enable Branch Prediction */ 275#if defined(CONFIG_BTB) 276 lis r0,BUCSR_ENABLE@h 277 ori r0,r0,BUCSR_ENABLE@l 278 mtspr SPRN_BUCSR,r0 279#endif 280 281#if defined(CONFIG_SYS_INIT_DBCR) 282 lis r1,0xffff 283 ori r1,r1,0xffff 284 mtspr DBSR,r1 /* Clear all status bits */ 285 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 286 ori r0,r0,CONFIG_SYS_INIT_DBCR@l 287 mtspr DBCR0,r0 288#endif 289 290#ifdef CONFIG_MPC8569 291#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 292#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 293 294 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 295 * use address space which is more than 12bits, and it must be done in 296 * the 4K boot page. So we set this bit here. 297 */ 298 299 /* create a temp mapping TLB0[0] for LBCR */ 300 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h 301 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l 302 303 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 304 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 305 306 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h 307 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l 308 309 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 310 (MAS3_SX|MAS3_SW|MAS3_SR))@h 311 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 312 (MAS3_SX|MAS3_SW|MAS3_SR))@l 313 314 mtspr MAS0,r6 315 mtspr MAS1,r7 316 mtspr MAS2,r8 317 mtspr MAS3,r9 318 isync 319 msync 320 tlbwe 321 322 /* Set LBCR register */ 323 lis r4,CONFIG_SYS_LBCR_ADDR@h 324 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 325 326 lis r5,CONFIG_SYS_LBC_LBCR@h 327 ori r5,r5,CONFIG_SYS_LBC_LBCR@l 328 stw r5,0(r4) 329 isync 330 331 /* invalidate this temp TLB */ 332 lis r4,CONFIG_SYS_LBC_ADDR@h 333 ori r4,r4,CONFIG_SYS_LBC_ADDR@l 334 tlbivax 0,r4 335 isync 336 337#endif /* CONFIG_MPC8569 */ 338 339/* 340 * Search for the TLB that covers the code we're executing, and shrink it 341 * so that it covers only this 4K page. That will ensure that any other 342 * TLB we create won't interfere with it. We assume that the TLB exists, 343 * which is why we don't check the Valid bit of MAS1. 344 * 345 * This is necessary, for example, when booting from the on-chip ROM, 346 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. 347 * If we don't shrink this TLB now, then we'll accidentally delete it 348 * in "purge_old_ccsr_tlb" below. 349 */ 350 bl nexti /* Find our address */ 351nexti: mflr r1 /* R1 = our PC */ 352 li r2, 0 353 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ 354 isync 355 msync 356 tlbsx 0, r1 /* This must succeed */ 357 358 /* Set the size of the TLB to 4KB */ 359 mfspr r3, MAS1 360 li r2, 0xF00 361 andc r3, r3, r2 /* Clear the TSIZE bits */ 362 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l 363 mtspr MAS1, r3 364 365 /* 366 * Set the base address of the TLB to our PC. We assume that 367 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. 368 */ 369 lis r3, MAS2_EPN@h 370 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ 371 372 and r1, r1, r3 /* Our PC, rounded down to the nearest page */ 373 374 mfspr r2, MAS2 375 andc r2, r2, r3 376 or r2, r2, r1 377 mtspr MAS2, r2 /* Set the EPN to our PC base address */ 378 379 mfspr r2, MAS3 380 andc r2, r2, r3 381 or r2, r2, r1 382 mtspr MAS3, r2 /* Set the RPN to our PC base address */ 383 384 isync 385 msync 386 tlbwe 387 388/* 389 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default 390 * location is not where we want it. This typically happens on a 36-bit 391 * system, where we want to move CCSR to near the top of 36-bit address space. 392 * 393 * To move CCSR, we create two temporary TLBs, one for the old location, and 394 * another for the new location. On CoreNet systems, we also need to create 395 * a special, temporary LAW. 396 * 397 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for 398 * long-term TLBs, so we use TLB0 here. 399 */ 400#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) 401 402#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) 403#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." 404#endif 405 406purge_old_ccsr_tlb: 407 lis r8, CONFIG_SYS_CCSRBAR@h 408 ori r8, r8, CONFIG_SYS_CCSRBAR@l 409 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h 410 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l 411 412 /* 413 * In a multi-stage boot (e.g. NAND boot), a previous stage may have 414 * created a TLB for CCSR, which will interfere with our relocation 415 * code. Since we're going to create a new TLB for CCSR anyway, 416 * it should be safe to delete this old TLB here. We have to search 417 * for it, though. 418 */ 419 420 li r1, 0 421 mtspr MAS6, r1 /* Search the current address space and PID */ 422 isync 423 msync 424 tlbsx 0, r8 425 mfspr r1, MAS1 426 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ 427 beq 1f /* Skip if no TLB found */ 428 429 rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ 430 mtspr MAS1, r1 431 isync 432 msync 433 tlbwe 4341: 435 436create_ccsr_new_tlb: 437 /* 438 * Create a TLB for the new location of CCSR. Register R8 is reserved 439 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). 440 */ 441 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 442 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 443 lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 444 ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 445 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 446 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 447 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h 448 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l 449#ifdef CONFIG_ENABLE_36BIT_PHYS 450 lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 451 ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 452 mtspr MAS7, r7 453#endif 454 mtspr MAS0, r0 455 mtspr MAS1, r1 456 mtspr MAS2, r2 457 mtspr MAS3, r3 458 isync 459 msync 460 tlbwe 461 462 /* 463 * Create a TLB for the current location of CCSR. Register R9 is reserved 464 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). 465 */ 466create_ccsr_old_tlb: 467 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 468 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 469 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 470 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 471 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h 472 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l 473#ifdef CONFIG_ENABLE_36BIT_PHYS 474 li r7, 0 /* The default CCSR address is always a 32-bit number */ 475 mtspr MAS7, r7 476#endif 477 mtspr MAS0, r0 478 /* MAS1 is the same as above */ 479 mtspr MAS2, r2 480 mtspr MAS3, r3 481 isync 482 msync 483 tlbwe 484 485 /* 486 * We have a TLB for what we think is the current (old) CCSR. Let's 487 * verify that, otherwise we won't be able to move it. 488 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only 489 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. 490 */ 491verify_old_ccsr: 492 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h 493 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l 494#ifdef CONFIG_FSL_CORENET 495 lwz r1, 4(r9) /* CCSRBARL */ 496#else 497 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ 498 slwi r1, r1, 12 499#endif 500 501 cmpl 0, r0, r1 502 503 /* 504 * If the value we read from CCSRBARL is not what we expect, then 505 * enter an infinite loop. This will at least allow a debugger to 506 * halt execution and examine TLBs, etc. There's no point in going 507 * on. 508 */ 509infinite_debug_loop: 510 bne infinite_debug_loop 511 512#ifdef CONFIG_FSL_CORENET 513 514#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 515#define LAW_EN 0x80000000 516#define LAW_SIZE_4K 0xb 517#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) 518#define CCSRAR_C 0x80000000 /* Commit */ 519 520create_temp_law: 521 /* 522 * On CoreNet systems, we create the temporary LAW using a special LAW 523 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. 524 */ 525 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 526 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 527 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 528 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 529 lis r2, CCSRBAR_LAWAR@h 530 ori r2, r2, CCSRBAR_LAWAR@l 531 532 stw r0, 0xc00(r9) /* LAWBARH0 */ 533 stw r1, 0xc04(r9) /* LAWBARL0 */ 534 sync 535 stw r2, 0xc08(r9) /* LAWAR0 */ 536 537 /* 538 * Read back from LAWAR to ensure the update is complete. e500mc 539 * cores also require an isync. 540 */ 541 lwz r0, 0xc08(r9) /* LAWAR0 */ 542 isync 543 544 /* 545 * Read the current CCSRBARH and CCSRBARL using load word instructions. 546 * Follow this with an isync instruction. This forces any outstanding 547 * accesses to configuration space to completion. 548 */ 549read_old_ccsrbar: 550 lwz r0, 0(r9) /* CCSRBARH */ 551 lwz r0, 4(r9) /* CCSRBARL */ 552 isync 553 554 /* 555 * Write the new values for CCSRBARH and CCSRBARL to their old 556 * locations. The CCSRBARH has a shadow register. When the CCSRBARH 557 * has a new value written it loads a CCSRBARH shadow register. When 558 * the CCSRBARL is written, the CCSRBARH shadow register contents 559 * along with the CCSRBARL value are loaded into the CCSRBARH and 560 * CCSRBARL registers, respectively. Follow this with a sync 561 * instruction. 562 */ 563write_new_ccsrbar: 564 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 565 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 566 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 567 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 568 lis r2, CCSRAR_C@h 569 ori r2, r2, CCSRAR_C@l 570 571 stw r0, 0(r9) /* Write to CCSRBARH */ 572 sync /* Make sure we write to CCSRBARH first */ 573 stw r1, 4(r9) /* Write to CCSRBARL */ 574 sync 575 576 /* 577 * Write a 1 to the commit bit (C) of CCSRAR at the old location. 578 * Follow this with a sync instruction. 579 */ 580 stw r2, 8(r9) 581 sync 582 583 /* Delete the temporary LAW */ 584delete_temp_law: 585 li r1, 0 586 stw r1, 0xc08(r8) 587 sync 588 stw r1, 0xc00(r8) 589 stw r1, 0xc04(r8) 590 sync 591 592#else /* #ifdef CONFIG_FSL_CORENET */ 593 594write_new_ccsrbar: 595 /* 596 * Read the current value of CCSRBAR using a load word instruction 597 * followed by an isync. This forces all accesses to configuration 598 * space to complete. 599 */ 600 sync 601 lwz r0, 0(r9) 602 isync 603 604/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ 605#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ 606 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) 607 608 /* Write the new value to CCSRBAR. */ 609 lis r0, CCSRBAR_PHYS_RS12@h 610 ori r0, r0, CCSRBAR_PHYS_RS12@l 611 stw r0, 0(r9) 612 sync 613 614 /* 615 * The manual says to perform a load of an address that does not 616 * access configuration space or the on-chip SRAM using an existing TLB, 617 * but that doesn't appear to be necessary. We will do the isync, 618 * though. 619 */ 620 isync 621 622 /* 623 * Read the contents of CCSRBAR from its new location, followed by 624 * another isync. 625 */ 626 lwz r0, 0(r8) 627 isync 628 629#endif /* #ifdef CONFIG_FSL_CORENET */ 630 631 /* Delete the temporary TLBs */ 632delete_temp_tlbs: 633 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 634 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 635 li r1, 0 636 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 637 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 638 mtspr MAS0, r0 639 mtspr MAS1, r1 640 mtspr MAS2, r2 641 isync 642 msync 643 tlbwe 644 645 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 646 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 647 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 648 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 649 mtspr MAS0, r0 650 mtspr MAS2, r2 651 isync 652 msync 653 tlbwe 654#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ 655 656create_init_ram_area: 657 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 658 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 659 660#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) 661 /* create a temp mapping in AS=1 to the 4M boot window */ 662 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h 663 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l 664 665 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h 666 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l 667 668 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 669 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 670 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 671#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 672 /* create a temp mapping in AS = 1 for Flash mapping 673 * created by PBL for ISBC code 674 */ 675 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 676 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 677 678 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 679 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 680 681 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 682 (MAS3_SX|MAS3_SW|MAS3_SR))@h 683 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 684 (MAS3_SX|MAS3_SW|MAS3_SR))@l 685#else 686 /* 687 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main 688 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. 689 */ 690 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 691 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 692 693 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 694 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 695 696 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 697 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 698#endif 699 700 mtspr MAS0,r6 701 mtspr MAS1,r7 702 mtspr MAS2,r8 703 mtspr MAS3,r9 704 isync 705 msync 706 tlbwe 707 708 /* create a temp mapping in AS=1 to the stack */ 709 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h 710 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l 711 712 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h 713 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l 714 715 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h 716 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l 717 718#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ 719 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) 720 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 721 (MAS3_SX|MAS3_SW|MAS3_SR))@h 722 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 723 (MAS3_SX|MAS3_SW|MAS3_SR))@l 724 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 725 mtspr MAS7,r10 726#else 727 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 728 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 729#endif 730 731 mtspr MAS0,r6 732 mtspr MAS1,r7 733 mtspr MAS2,r8 734 mtspr MAS3,r9 735 isync 736 msync 737 tlbwe 738 739 lis r6,MSR_IS|MSR_DS|MSR_DE@h 740 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l 741 lis r7,switch_as@h 742 ori r7,r7,switch_as@l 743 744 mtspr SPRN_SRR0,r7 745 mtspr SPRN_SRR1,r6 746 rfi 747 748switch_as: 749/* L1 DCache is used for initial RAM */ 750 751 /* Allocate Initial RAM in data cache. 752 */ 753 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 754 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 755 mfspr r2, L1CFG0 756 andi. r2, r2, 0x1ff 757 /* cache size * 1024 / (2 * L1 line size) */ 758 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 759 mtctr r2 760 li r0,0 7611: 762 dcbz r0,r3 763 dcbtls 0,r0,r3 764 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 765 bdnz 1b 766 767 /* Jump out the last 4K page and continue to 'normal' start */ 768#ifdef CONFIG_SYS_RAMBOOT 769 b _start_cont 770#else 771 /* Calculate absolute address in FLASH and jump there */ 772 /*--------------------------------------------------------------*/ 773 lis r3,CONFIG_SYS_MONITOR_BASE@h 774 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 775 addi r3,r3,_start_cont - _start + _START_OFFSET 776 mtlr r3 777 blr 778#endif 779 780 .text 781 .globl _start 782_start: 783 .long 0x27051956 /* U-BOOT Magic Number */ 784 .globl version_string 785version_string: 786 .ascii U_BOOT_VERSION_STRING, "\0" 787 788 .align 4 789 .globl _start_cont 790_start_cont: 791 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 792 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h 793 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l 794 795 li r0,0 796 stwu r0,-4(r1) 797 stwu r0,-4(r1) /* Terminate call chain */ 798 799 stwu r1,-8(r1) /* Save back chain and move SP */ 800 lis r0,RESET_VECTOR@h /* Address of reset vector */ 801 ori r0,r0,RESET_VECTOR@l 802 stwu r1,-8(r1) /* Save back chain and move SP */ 803 stw r0,+12(r1) /* Save return addr (underflow vect) */ 804 805 GET_GOT 806 bl cpu_init_early_f 807 808 /* switch back to AS = 0 */ 809 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 810 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 811 mtmsr r3 812 isync 813 814 bl cpu_init_f 815 bl board_init_f 816 isync 817 818 /* NOTREACHED - board_init_f() does not return */ 819 820#ifndef CONFIG_NAND_SPL 821 . = EXC_OFF_SYS_RESET 822 .globl _start_of_vectors 823_start_of_vectors: 824 825/* Critical input. */ 826 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 827 828/* Machine check */ 829 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 830 831/* Data Storage exception. */ 832 STD_EXCEPTION(0x0300, DataStorage, UnknownException) 833 834/* Instruction Storage exception. */ 835 STD_EXCEPTION(0x0400, InstStorage, UnknownException) 836 837/* External Interrupt exception. */ 838 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 839 840/* Alignment exception. */ 841 . = 0x0600 842Alignment: 843 EXCEPTION_PROLOG(SRR0, SRR1) 844 mfspr r4,DAR 845 stw r4,_DAR(r21) 846 mfspr r5,DSISR 847 stw r5,_DSISR(r21) 848 addi r3,r1,STACK_FRAME_OVERHEAD 849 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 850 851/* Program check exception */ 852 . = 0x0700 853ProgramCheck: 854 EXCEPTION_PROLOG(SRR0, SRR1) 855 addi r3,r1,STACK_FRAME_OVERHEAD 856 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 857 MSR_KERNEL, COPY_EE) 858 859 /* No FPU on MPC85xx. This exception is not supposed to happen. 860 */ 861 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 862 863 . = 0x0900 864/* 865 * r0 - SYSCALL number 866 * r3-... arguments 867 */ 868SystemCall: 869 addis r11,r0,0 /* get functions table addr */ 870 ori r11,r11,0 /* Note: this code is patched in trap_init */ 871 addis r12,r0,0 /* get number of functions */ 872 ori r12,r12,0 873 874 cmplw 0,r0,r12 875 bge 1f 876 877 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 878 add r11,r11,r0 879 lwz r11,0(r11) 880 881 li r20,0xd00-4 /* Get stack pointer */ 882 lwz r12,0(r20) 883 subi r12,r12,12 /* Adjust stack pointer */ 884 li r0,0xc00+_end_back-SystemCall 885 cmplw 0,r0,r12 /* Check stack overflow */ 886 bgt 1f 887 stw r12,0(r20) 888 889 mflr r0 890 stw r0,0(r12) 891 mfspr r0,SRR0 892 stw r0,4(r12) 893 mfspr r0,SRR1 894 stw r0,8(r12) 895 896 li r12,0xc00+_back-SystemCall 897 mtlr r12 898 mtspr SRR0,r11 899 9001: SYNC 901 rfi 902_back: 903 904 mfmsr r11 /* Disable interrupts */ 905 li r12,0 906 ori r12,r12,MSR_EE 907 andc r11,r11,r12 908 SYNC /* Some chip revs need this... */ 909 mtmsr r11 910 SYNC 911 912 li r12,0xd00-4 /* restore regs */ 913 lwz r12,0(r12) 914 915 lwz r11,0(r12) 916 mtlr r11 917 lwz r11,4(r12) 918 mtspr SRR0,r11 919 lwz r11,8(r12) 920 mtspr SRR1,r11 921 922 addi r12,r12,12 /* Adjust stack pointer */ 923 li r20,0xd00-4 924 stw r12,0(r20) 925 926 SYNC 927 rfi 928_end_back: 929 930 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 931 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 932 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 933 934 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 935 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 936 937 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 938 939 .globl _end_of_vectors 940_end_of_vectors: 941 942 943 . = . + (0x100 - ( . & 0xff )) /* align for debug */ 944 945/* 946 * This code finishes saving the registers to the exception frame 947 * and jumps to the appropriate handler for the exception. 948 * Register r21 is pointer into trap frame, r1 has new stack pointer. 949 */ 950 .globl transfer_to_handler 951transfer_to_handler: 952 stw r22,_NIP(r21) 953 lis r22,MSR_POW@h 954 andc r23,r23,r22 955 stw r23,_MSR(r21) 956 SAVE_GPR(7, r21) 957 SAVE_4GPRS(8, r21) 958 SAVE_8GPRS(12, r21) 959 SAVE_8GPRS(24, r21) 960 961 mflr r23 962 andi. r24,r23,0x3f00 /* get vector offset */ 963 stw r24,TRAP(r21) 964 li r22,0 965 stw r22,RESULT(r21) 966 mtspr SPRG2,r22 /* r1 is now kernel sp */ 967 968 lwz r24,0(r23) /* virtual address of handler */ 969 lwz r23,4(r23) /* where to go when done */ 970 mtspr SRR0,r24 971 mtspr SRR1,r20 972 mtlr r23 973 SYNC 974 rfi /* jump to handler, enable MMU */ 975 976int_return: 977 mfmsr r28 /* Disable interrupts */ 978 li r4,0 979 ori r4,r4,MSR_EE 980 andc r28,r28,r4 981 SYNC /* Some chip revs need this... */ 982 mtmsr r28 983 SYNC 984 lwz r2,_CTR(r1) 985 lwz r0,_LINK(r1) 986 mtctr r2 987 mtlr r0 988 lwz r2,_XER(r1) 989 lwz r0,_CCR(r1) 990 mtspr XER,r2 991 mtcrf 0xFF,r0 992 REST_10GPRS(3, r1) 993 REST_10GPRS(13, r1) 994 REST_8GPRS(23, r1) 995 REST_GPR(31, r1) 996 lwz r2,_NIP(r1) /* Restore environment */ 997 lwz r0,_MSR(r1) 998 mtspr SRR0,r2 999 mtspr SRR1,r0 1000 lwz r0,GPR0(r1) 1001 lwz r2,GPR2(r1) 1002 lwz r1,GPR1(r1) 1003 SYNC 1004 rfi 1005 1006crit_return: 1007 mfmsr r28 /* Disable interrupts */ 1008 li r4,0 1009 ori r4,r4,MSR_EE 1010 andc r28,r28,r4 1011 SYNC /* Some chip revs need this... */ 1012 mtmsr r28 1013 SYNC 1014 lwz r2,_CTR(r1) 1015 lwz r0,_LINK(r1) 1016 mtctr r2 1017 mtlr r0 1018 lwz r2,_XER(r1) 1019 lwz r0,_CCR(r1) 1020 mtspr XER,r2 1021 mtcrf 0xFF,r0 1022 REST_10GPRS(3, r1) 1023 REST_10GPRS(13, r1) 1024 REST_8GPRS(23, r1) 1025 REST_GPR(31, r1) 1026 lwz r2,_NIP(r1) /* Restore environment */ 1027 lwz r0,_MSR(r1) 1028 mtspr SPRN_CSRR0,r2 1029 mtspr SPRN_CSRR1,r0 1030 lwz r0,GPR0(r1) 1031 lwz r2,GPR2(r1) 1032 lwz r1,GPR1(r1) 1033 SYNC 1034 rfci 1035 1036mck_return: 1037 mfmsr r28 /* Disable interrupts */ 1038 li r4,0 1039 ori r4,r4,MSR_EE 1040 andc r28,r28,r4 1041 SYNC /* Some chip revs need this... */ 1042 mtmsr r28 1043 SYNC 1044 lwz r2,_CTR(r1) 1045 lwz r0,_LINK(r1) 1046 mtctr r2 1047 mtlr r0 1048 lwz r2,_XER(r1) 1049 lwz r0,_CCR(r1) 1050 mtspr XER,r2 1051 mtcrf 0xFF,r0 1052 REST_10GPRS(3, r1) 1053 REST_10GPRS(13, r1) 1054 REST_8GPRS(23, r1) 1055 REST_GPR(31, r1) 1056 lwz r2,_NIP(r1) /* Restore environment */ 1057 lwz r0,_MSR(r1) 1058 mtspr SPRN_MCSRR0,r2 1059 mtspr SPRN_MCSRR1,r0 1060 lwz r0,GPR0(r1) 1061 lwz r2,GPR2(r1) 1062 lwz r1,GPR1(r1) 1063 SYNC 1064 rfmci 1065 1066/* Cache functions. 1067*/ 1068.globl flush_icache 1069flush_icache: 1070.globl invalidate_icache 1071invalidate_icache: 1072 mfspr r0,L1CSR1 1073 ori r0,r0,L1CSR1_ICFI 1074 msync 1075 isync 1076 mtspr L1CSR1,r0 1077 isync 1078 blr /* entire I cache */ 1079 1080.globl invalidate_dcache 1081invalidate_dcache: 1082 mfspr r0,L1CSR0 1083 ori r0,r0,L1CSR0_DCFI 1084 msync 1085 isync 1086 mtspr L1CSR0,r0 1087 isync 1088 blr 1089 1090 .globl icache_enable 1091icache_enable: 1092 mflr r8 1093 bl invalidate_icache 1094 mtlr r8 1095 isync 1096 mfspr r4,L1CSR1 1097 ori r4,r4,0x0001 1098 oris r4,r4,0x0001 1099 mtspr L1CSR1,r4 1100 isync 1101 blr 1102 1103 .globl icache_disable 1104icache_disable: 1105 mfspr r0,L1CSR1 1106 lis r3,0 1107 ori r3,r3,L1CSR1_ICE 1108 andc r0,r0,r3 1109 mtspr L1CSR1,r0 1110 isync 1111 blr 1112 1113 .globl icache_status 1114icache_status: 1115 mfspr r3,L1CSR1 1116 andi. r3,r3,L1CSR1_ICE 1117 blr 1118 1119 .globl dcache_enable 1120dcache_enable: 1121 mflr r8 1122 bl invalidate_dcache 1123 mtlr r8 1124 isync 1125 mfspr r0,L1CSR0 1126 ori r0,r0,0x0001 1127 oris r0,r0,0x0001 1128 msync 1129 isync 1130 mtspr L1CSR0,r0 1131 isync 1132 blr 1133 1134 .globl dcache_disable 1135dcache_disable: 1136 mfspr r3,L1CSR0 1137 lis r4,0 1138 ori r4,r4,L1CSR0_DCE 1139 andc r3,r3,r4 1140 mtspr L1CSR0,r3 1141 isync 1142 blr 1143 1144 .globl dcache_status 1145dcache_status: 1146 mfspr r3,L1CSR0 1147 andi. r3,r3,L1CSR0_DCE 1148 blr 1149 1150 .globl get_pir 1151get_pir: 1152 mfspr r3,PIR 1153 blr 1154 1155 .globl get_pvr 1156get_pvr: 1157 mfspr r3,PVR 1158 blr 1159 1160 .globl get_svr 1161get_svr: 1162 mfspr r3,SVR 1163 blr 1164 1165 .globl wr_tcr 1166wr_tcr: 1167 mtspr TCR,r3 1168 blr 1169 1170/*------------------------------------------------------------------------------- */ 1171/* Function: in8 */ 1172/* Description: Input 8 bits */ 1173/*------------------------------------------------------------------------------- */ 1174 .globl in8 1175in8: 1176 lbz r3,0x0000(r3) 1177 blr 1178 1179/*------------------------------------------------------------------------------- */ 1180/* Function: out8 */ 1181/* Description: Output 8 bits */ 1182/*------------------------------------------------------------------------------- */ 1183 .globl out8 1184out8: 1185 stb r4,0x0000(r3) 1186 sync 1187 blr 1188 1189/*------------------------------------------------------------------------------- */ 1190/* Function: out16 */ 1191/* Description: Output 16 bits */ 1192/*------------------------------------------------------------------------------- */ 1193 .globl out16 1194out16: 1195 sth r4,0x0000(r3) 1196 sync 1197 blr 1198 1199/*------------------------------------------------------------------------------- */ 1200/* Function: out16r */ 1201/* Description: Byte reverse and output 16 bits */ 1202/*------------------------------------------------------------------------------- */ 1203 .globl out16r 1204out16r: 1205 sthbrx r4,r0,r3 1206 sync 1207 blr 1208 1209/*------------------------------------------------------------------------------- */ 1210/* Function: out32 */ 1211/* Description: Output 32 bits */ 1212/*------------------------------------------------------------------------------- */ 1213 .globl out32 1214out32: 1215 stw r4,0x0000(r3) 1216 sync 1217 blr 1218 1219/*------------------------------------------------------------------------------- */ 1220/* Function: out32r */ 1221/* Description: Byte reverse and output 32 bits */ 1222/*------------------------------------------------------------------------------- */ 1223 .globl out32r 1224out32r: 1225 stwbrx r4,r0,r3 1226 sync 1227 blr 1228 1229/*------------------------------------------------------------------------------- */ 1230/* Function: in16 */ 1231/* Description: Input 16 bits */ 1232/*------------------------------------------------------------------------------- */ 1233 .globl in16 1234in16: 1235 lhz r3,0x0000(r3) 1236 blr 1237 1238/*------------------------------------------------------------------------------- */ 1239/* Function: in16r */ 1240/* Description: Input 16 bits and byte reverse */ 1241/*------------------------------------------------------------------------------- */ 1242 .globl in16r 1243in16r: 1244 lhbrx r3,r0,r3 1245 blr 1246 1247/*------------------------------------------------------------------------------- */ 1248/* Function: in32 */ 1249/* Description: Input 32 bits */ 1250/*------------------------------------------------------------------------------- */ 1251 .globl in32 1252in32: 1253 lwz 3,0x0000(3) 1254 blr 1255 1256/*------------------------------------------------------------------------------- */ 1257/* Function: in32r */ 1258/* Description: Input 32 bits and byte reverse */ 1259/*------------------------------------------------------------------------------- */ 1260 .globl in32r 1261in32r: 1262 lwbrx r3,r0,r3 1263 blr 1264#endif /* !CONFIG_NAND_SPL */ 1265 1266/*------------------------------------------------------------------------------*/ 1267 1268/* 1269 * void write_tlb(mas0, mas1, mas2, mas3, mas7) 1270 */ 1271 .globl write_tlb 1272write_tlb: 1273 mtspr MAS0,r3 1274 mtspr MAS1,r4 1275 mtspr MAS2,r5 1276 mtspr MAS3,r6 1277#ifdef CONFIG_ENABLE_36BIT_PHYS 1278 mtspr MAS7,r7 1279#endif 1280 li r3,0 1281#ifdef CONFIG_SYS_BOOK3E_HV 1282 mtspr MAS8,r3 1283#endif 1284 isync 1285 tlbwe 1286 msync 1287 isync 1288 blr 1289 1290/* 1291 * void relocate_code (addr_sp, gd, addr_moni) 1292 * 1293 * This "function" does not return, instead it continues in RAM 1294 * after relocating the monitor code. 1295 * 1296 * r3 = dest 1297 * r4 = src 1298 * r5 = length in bytes 1299 * r6 = cachelinesize 1300 */ 1301 .globl relocate_code 1302relocate_code: 1303 mr r1,r3 /* Set new stack pointer */ 1304 mr r9,r4 /* Save copy of Init Data pointer */ 1305 mr r10,r5 /* Save copy of Destination Address */ 1306 1307 GET_GOT 1308 mr r3,r5 /* Destination Address */ 1309 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1310 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 1311 lwz r5,GOT(__init_end) 1312 sub r5,r5,r4 1313 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 1314 1315 /* 1316 * Fix GOT pointer: 1317 * 1318 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1319 * 1320 * Offset: 1321 */ 1322 sub r15,r10,r4 1323 1324 /* First our own GOT */ 1325 add r12,r12,r15 1326 /* the the one used by the C code */ 1327 add r30,r30,r15 1328 1329 /* 1330 * Now relocate code 1331 */ 1332 1333 cmplw cr1,r3,r4 1334 addi r0,r5,3 1335 srwi. r0,r0,2 1336 beq cr1,4f /* In place copy is not necessary */ 1337 beq 7f /* Protect against 0 count */ 1338 mtctr r0 1339 bge cr1,2f 1340 1341 la r8,-4(r4) 1342 la r7,-4(r3) 13431: lwzu r0,4(r8) 1344 stwu r0,4(r7) 1345 bdnz 1b 1346 b 4f 1347 13482: slwi r0,r0,2 1349 add r8,r4,r0 1350 add r7,r3,r0 13513: lwzu r0,-4(r8) 1352 stwu r0,-4(r7) 1353 bdnz 3b 1354 1355/* 1356 * Now flush the cache: note that we must start from a cache aligned 1357 * address. Otherwise we might miss one cache line. 1358 */ 13594: cmpwi r6,0 1360 add r5,r3,r5 1361 beq 7f /* Always flush prefetch queue in any case */ 1362 subi r0,r6,1 1363 andc r3,r3,r0 1364 mr r4,r3 13655: dcbst 0,r4 1366 add r4,r4,r6 1367 cmplw r4,r5 1368 blt 5b 1369 sync /* Wait for all dcbst to complete on bus */ 1370 mr r4,r3 13716: icbi 0,r4 1372 add r4,r4,r6 1373 cmplw r4,r5 1374 blt 6b 13757: sync /* Wait for all icbi to complete on bus */ 1376 isync 1377 1378 /* 1379 * Re-point the IVPR at RAM 1380 */ 1381 mtspr IVPR,r10 1382 1383/* 1384 * We are done. Do not return, instead branch to second part of board 1385 * initialization, now running from RAM. 1386 */ 1387 1388 addi r0,r10,in_ram - _start + _START_OFFSET 1389 mtlr r0 1390 blr /* NEVER RETURNS! */ 1391 .globl in_ram 1392in_ram: 1393 1394 /* 1395 * Relocation Function, r12 point to got2+0x8000 1396 * 1397 * Adjust got2 pointers, no need to check for 0, this code 1398 * already puts a few entries in the table. 1399 */ 1400 li r0,__got2_entries@sectoff@l 1401 la r3,GOT(_GOT2_TABLE_) 1402 lwz r11,GOT(_GOT2_TABLE_) 1403 mtctr r0 1404 sub r11,r3,r11 1405 addi r3,r3,-4 14061: lwzu r0,4(r3) 1407 cmpwi r0,0 1408 beq- 2f 1409 add r0,r0,r11 1410 stw r0,0(r3) 14112: bdnz 1b 1412 1413 /* 1414 * Now adjust the fixups and the pointers to the fixups 1415 * in case we need to move ourselves again. 1416 */ 1417 li r0,__fixup_entries@sectoff@l 1418 lwz r3,GOT(_FIXUP_TABLE_) 1419 cmpwi r0,0 1420 mtctr r0 1421 addi r3,r3,-4 1422 beq 4f 14233: lwzu r4,4(r3) 1424 lwzux r0,r4,r11 1425 cmpwi r0,0 1426 add r0,r0,r11 1427 stw r4,0(r3) 1428 beq- 5f 1429 stw r0,0(r4) 14305: bdnz 3b 14314: 1432clear_bss: 1433 /* 1434 * Now clear BSS segment 1435 */ 1436 lwz r3,GOT(__bss_start) 1437 lwz r4,GOT(__bss_end__) 1438 1439 cmplw 0,r3,r4 1440 beq 6f 1441 1442 li r0,0 14435: 1444 stw r0,0(r3) 1445 addi r3,r3,4 1446 cmplw 0,r3,r4 1447 bne 5b 14486: 1449 1450 mr r3,r9 /* Init Data pointer */ 1451 mr r4,r10 /* Destination Address */ 1452 bl board_init_r 1453 1454#ifndef CONFIG_NAND_SPL 1455 /* 1456 * Copy exception vector code to low memory 1457 * 1458 * r3: dest_addr 1459 * r7: source address, r8: end address, r9: target address 1460 */ 1461 .globl trap_init 1462trap_init: 1463 mflr r4 /* save link register */ 1464 GET_GOT 1465 lwz r7,GOT(_start_of_vectors) 1466 lwz r8,GOT(_end_of_vectors) 1467 1468 li r9,0x100 /* reset vector always at 0x100 */ 1469 1470 cmplw 0,r7,r8 1471 bgelr /* return if r7>=r8 - just in case */ 14721: 1473 lwz r0,0(r7) 1474 stw r0,0(r9) 1475 addi r7,r7,4 1476 addi r9,r9,4 1477 cmplw 0,r7,r8 1478 bne 1b 1479 1480 /* 1481 * relocate `hdlr' and `int_return' entries 1482 */ 1483 li r7,.L_CriticalInput - _start + _START_OFFSET 1484 bl trap_reloc 1485 li r7,.L_MachineCheck - _start + _START_OFFSET 1486 bl trap_reloc 1487 li r7,.L_DataStorage - _start + _START_OFFSET 1488 bl trap_reloc 1489 li r7,.L_InstStorage - _start + _START_OFFSET 1490 bl trap_reloc 1491 li r7,.L_ExtInterrupt - _start + _START_OFFSET 1492 bl trap_reloc 1493 li r7,.L_Alignment - _start + _START_OFFSET 1494 bl trap_reloc 1495 li r7,.L_ProgramCheck - _start + _START_OFFSET 1496 bl trap_reloc 1497 li r7,.L_FPUnavailable - _start + _START_OFFSET 1498 bl trap_reloc 1499 li r7,.L_Decrementer - _start + _START_OFFSET 1500 bl trap_reloc 1501 li r7,.L_IntervalTimer - _start + _START_OFFSET 1502 li r8,_end_of_vectors - _start + _START_OFFSET 15032: 1504 bl trap_reloc 1505 addi r7,r7,0x100 /* next exception vector */ 1506 cmplw 0,r7,r8 1507 blt 2b 1508 1509 /* Update IVORs as per relocated vector table address */ 1510 li r7,0x0100 1511 mtspr IVOR0,r7 /* 0: Critical input */ 1512 li r7,0x0200 1513 mtspr IVOR1,r7 /* 1: Machine check */ 1514 li r7,0x0300 1515 mtspr IVOR2,r7 /* 2: Data storage */ 1516 li r7,0x0400 1517 mtspr IVOR3,r7 /* 3: Instruction storage */ 1518 li r7,0x0500 1519 mtspr IVOR4,r7 /* 4: External interrupt */ 1520 li r7,0x0600 1521 mtspr IVOR5,r7 /* 5: Alignment */ 1522 li r7,0x0700 1523 mtspr IVOR6,r7 /* 6: Program check */ 1524 li r7,0x0800 1525 mtspr IVOR7,r7 /* 7: floating point unavailable */ 1526 li r7,0x0900 1527 mtspr IVOR8,r7 /* 8: System call */ 1528 /* 9: Auxiliary processor unavailable(unsupported) */ 1529 li r7,0x0a00 1530 mtspr IVOR10,r7 /* 10: Decrementer */ 1531 li r7,0x0b00 1532 mtspr IVOR11,r7 /* 11: Interval timer */ 1533 li r7,0x0c00 1534 mtspr IVOR12,r7 /* 12: Watchdog timer */ 1535 li r7,0x0d00 1536 mtspr IVOR13,r7 /* 13: Data TLB error */ 1537 li r7,0x0e00 1538 mtspr IVOR14,r7 /* 14: Instruction TLB error */ 1539 li r7,0x0f00 1540 mtspr IVOR15,r7 /* 15: Debug */ 1541 1542 lis r7,0x0 1543 mtspr IVPR,r7 1544 1545 mtlr r4 /* restore link register */ 1546 blr 1547 1548.globl unlock_ram_in_cache 1549unlock_ram_in_cache: 1550 /* invalidate the INIT_RAM section */ 1551 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1552 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1553 mfspr r4,L1CFG0 1554 andi. r4,r4,0x1ff 1555 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1556 mtctr r4 15571: dcbi r0,r3 1558 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1559 bdnz 1b 1560 sync 1561 1562 /* Invalidate the TLB entries for the cache */ 1563 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1564 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1565 tlbivax 0,r3 1566 addi r3,r3,0x1000 1567 tlbivax 0,r3 1568 addi r3,r3,0x1000 1569 tlbivax 0,r3 1570 addi r3,r3,0x1000 1571 tlbivax 0,r3 1572 isync 1573 blr 1574 1575.globl flush_dcache 1576flush_dcache: 1577 mfspr r3,SPRN_L1CFG0 1578 1579 rlwinm r5,r3,9,3 /* Extract cache block size */ 1580 twlgti r5,1 /* Only 32 and 64 byte cache blocks 1581 * are currently defined. 1582 */ 1583 li r4,32 1584 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1585 * log2(number of ways) 1586 */ 1587 slw r5,r4,r5 /* r5 = cache block size */ 1588 1589 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1590 mulli r7,r7,13 /* An 8-way cache will require 13 1591 * loads per set. 1592 */ 1593 slw r7,r7,r6 1594 1595 /* save off HID0 and set DCFA */ 1596 mfspr r8,SPRN_HID0 1597 ori r9,r8,HID0_DCFA@l 1598 mtspr SPRN_HID0,r9 1599 isync 1600 1601 lis r4,0 1602 mtctr r7 1603 16041: lwz r3,0(r4) /* Load... */ 1605 add r4,r4,r5 1606 bdnz 1b 1607 1608 msync 1609 lis r4,0 1610 mtctr r7 1611 16121: dcbf 0,r4 /* ...and flush. */ 1613 add r4,r4,r5 1614 bdnz 1b 1615 1616 /* restore HID0 */ 1617 mtspr SPRN_HID0,r8 1618 isync 1619 1620 blr 1621 1622.globl setup_ivors 1623setup_ivors: 1624 1625#include "fixed_ivor.S" 1626 blr 1627#endif /* !CONFIG_NAND_SPL */ 1628