1*a47a12beSStefan Roese/* 2*a47a12beSStefan Roese * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. 3*a47a12beSStefan Roese * Copyright (C) 2003 Motorola,Inc. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6*a47a12beSStefan Roese * project. 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11*a47a12beSStefan Roese * the License, or (at your option) any later version. 12*a47a12beSStefan Roese * 13*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*a47a12beSStefan Roese * GNU General Public License for more details. 17*a47a12beSStefan Roese * 18*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*a47a12beSStefan Roese * MA 02111-1307 USA 22*a47a12beSStefan Roese */ 23*a47a12beSStefan Roese 24*a47a12beSStefan Roese/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 25*a47a12beSStefan Roese * 26*a47a12beSStefan Roese * The processor starts at 0xfffffffc and the code is first executed in the 27*a47a12beSStefan Roese * last 4K page(0xfffff000-0xffffffff) in flash/rom. 28*a47a12beSStefan Roese * 29*a47a12beSStefan Roese */ 30*a47a12beSStefan Roese 31*a47a12beSStefan Roese#include <config.h> 32*a47a12beSStefan Roese#include <mpc85xx.h> 33*a47a12beSStefan Roese#include <timestamp.h> 34*a47a12beSStefan Roese#include <version.h> 35*a47a12beSStefan Roese 36*a47a12beSStefan Roese#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37*a47a12beSStefan Roese 38*a47a12beSStefan Roese#include <ppc_asm.tmpl> 39*a47a12beSStefan Roese#include <ppc_defs.h> 40*a47a12beSStefan Roese 41*a47a12beSStefan Roese#include <asm/cache.h> 42*a47a12beSStefan Roese#include <asm/mmu.h> 43*a47a12beSStefan Roese 44*a47a12beSStefan Roese#ifndef CONFIG_IDENT_STRING 45*a47a12beSStefan Roese#define CONFIG_IDENT_STRING "" 46*a47a12beSStefan Roese#endif 47*a47a12beSStefan Roese 48*a47a12beSStefan Roese#undef MSR_KERNEL 49*a47a12beSStefan Roese#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 50*a47a12beSStefan Roese 51*a47a12beSStefan Roese/* 52*a47a12beSStefan Roese * Set up GOT: Global Offset Table 53*a47a12beSStefan Roese * 54*a47a12beSStefan Roese * Use r12 to access the GOT 55*a47a12beSStefan Roese */ 56*a47a12beSStefan Roese START_GOT 57*a47a12beSStefan Roese GOT_ENTRY(_GOT2_TABLE_) 58*a47a12beSStefan Roese GOT_ENTRY(_FIXUP_TABLE_) 59*a47a12beSStefan Roese 60*a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 61*a47a12beSStefan Roese GOT_ENTRY(_start) 62*a47a12beSStefan Roese GOT_ENTRY(_start_of_vectors) 63*a47a12beSStefan Roese GOT_ENTRY(_end_of_vectors) 64*a47a12beSStefan Roese GOT_ENTRY(transfer_to_handler) 65*a47a12beSStefan Roese#endif 66*a47a12beSStefan Roese 67*a47a12beSStefan Roese GOT_ENTRY(__init_end) 68*a47a12beSStefan Roese GOT_ENTRY(_end) 69*a47a12beSStefan Roese GOT_ENTRY(__bss_start) 70*a47a12beSStefan Roese END_GOT 71*a47a12beSStefan Roese 72*a47a12beSStefan Roese/* 73*a47a12beSStefan Roese * e500 Startup -- after reset only the last 4KB of the effective 74*a47a12beSStefan Roese * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 75*a47a12beSStefan Roese * section is located at THIS LAST page and basically does three 76*a47a12beSStefan Roese * things: clear some registers, set up exception tables and 77*a47a12beSStefan Roese * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 78*a47a12beSStefan Roese * continue the boot procedure. 79*a47a12beSStefan Roese 80*a47a12beSStefan Roese * Once the boot rom is mapped by TLB entries we can proceed 81*a47a12beSStefan Roese * with normal startup. 82*a47a12beSStefan Roese * 83*a47a12beSStefan Roese */ 84*a47a12beSStefan Roese 85*a47a12beSStefan Roese .section .bootpg,"ax" 86*a47a12beSStefan Roese .globl _start_e500 87*a47a12beSStefan Roese 88*a47a12beSStefan Roese_start_e500: 89*a47a12beSStefan Roese 90*a47a12beSStefan Roese/* clear registers/arrays not reset by hardware */ 91*a47a12beSStefan Roese 92*a47a12beSStefan Roese /* L1 */ 93*a47a12beSStefan Roese li r0,2 94*a47a12beSStefan Roese mtspr L1CSR0,r0 /* invalidate d-cache */ 95*a47a12beSStefan Roese mtspr L1CSR1,r0 /* invalidate i-cache */ 96*a47a12beSStefan Roese 97*a47a12beSStefan Roese mfspr r1,DBSR 98*a47a12beSStefan Roese mtspr DBSR,r1 /* Clear all valid bits */ 99*a47a12beSStefan Roese 100*a47a12beSStefan Roese /* 101*a47a12beSStefan Roese * Enable L1 Caches early 102*a47a12beSStefan Roese * 103*a47a12beSStefan Roese */ 104*a47a12beSStefan Roese 105*a47a12beSStefan Roese#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) 106*a47a12beSStefan Roese /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 107*a47a12beSStefan Roese li r2,(32 + 0) 108*a47a12beSStefan Roese mtspr L1CSR2,r2 109*a47a12beSStefan Roese#endif 110*a47a12beSStefan Roese 111*a47a12beSStefan Roese /* Enable/invalidate the I-Cache */ 112*a47a12beSStefan Roese lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 113*a47a12beSStefan Roese ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 114*a47a12beSStefan Roese mtspr SPRN_L1CSR1,r2 115*a47a12beSStefan Roese1: 116*a47a12beSStefan Roese mfspr r3,SPRN_L1CSR1 117*a47a12beSStefan Roese and. r1,r3,r2 118*a47a12beSStefan Roese bne 1b 119*a47a12beSStefan Roese 120*a47a12beSStefan Roese lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 121*a47a12beSStefan Roese ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 122*a47a12beSStefan Roese mtspr SPRN_L1CSR1,r3 123*a47a12beSStefan Roese isync 124*a47a12beSStefan Roese2: 125*a47a12beSStefan Roese mfspr r3,SPRN_L1CSR1 126*a47a12beSStefan Roese andi. r1,r3,L1CSR1_ICE@l 127*a47a12beSStefan Roese beq 2b 128*a47a12beSStefan Roese 129*a47a12beSStefan Roese /* Enable/invalidate the D-Cache */ 130*a47a12beSStefan Roese lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 131*a47a12beSStefan Roese ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 132*a47a12beSStefan Roese mtspr SPRN_L1CSR0,r2 133*a47a12beSStefan Roese1: 134*a47a12beSStefan Roese mfspr r3,SPRN_L1CSR0 135*a47a12beSStefan Roese and. r1,r3,r2 136*a47a12beSStefan Roese bne 1b 137*a47a12beSStefan Roese 138*a47a12beSStefan Roese lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 139*a47a12beSStefan Roese ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 140*a47a12beSStefan Roese mtspr SPRN_L1CSR0,r3 141*a47a12beSStefan Roese isync 142*a47a12beSStefan Roese2: 143*a47a12beSStefan Roese mfspr r3,SPRN_L1CSR0 144*a47a12beSStefan Roese andi. r1,r3,L1CSR0_DCE@l 145*a47a12beSStefan Roese beq 2b 146*a47a12beSStefan Roese 147*a47a12beSStefan Roese /* Setup interrupt vectors */ 148*a47a12beSStefan Roese lis r1,TEXT_BASE@h 149*a47a12beSStefan Roese mtspr IVPR,r1 150*a47a12beSStefan Roese 151*a47a12beSStefan Roese li r1,0x0100 152*a47a12beSStefan Roese mtspr IVOR0,r1 /* 0: Critical input */ 153*a47a12beSStefan Roese li r1,0x0200 154*a47a12beSStefan Roese mtspr IVOR1,r1 /* 1: Machine check */ 155*a47a12beSStefan Roese li r1,0x0300 156*a47a12beSStefan Roese mtspr IVOR2,r1 /* 2: Data storage */ 157*a47a12beSStefan Roese li r1,0x0400 158*a47a12beSStefan Roese mtspr IVOR3,r1 /* 3: Instruction storage */ 159*a47a12beSStefan Roese li r1,0x0500 160*a47a12beSStefan Roese mtspr IVOR4,r1 /* 4: External interrupt */ 161*a47a12beSStefan Roese li r1,0x0600 162*a47a12beSStefan Roese mtspr IVOR5,r1 /* 5: Alignment */ 163*a47a12beSStefan Roese li r1,0x0700 164*a47a12beSStefan Roese mtspr IVOR6,r1 /* 6: Program check */ 165*a47a12beSStefan Roese li r1,0x0800 166*a47a12beSStefan Roese mtspr IVOR7,r1 /* 7: floating point unavailable */ 167*a47a12beSStefan Roese li r1,0x0900 168*a47a12beSStefan Roese mtspr IVOR8,r1 /* 8: System call */ 169*a47a12beSStefan Roese /* 9: Auxiliary processor unavailable(unsupported) */ 170*a47a12beSStefan Roese li r1,0x0a00 171*a47a12beSStefan Roese mtspr IVOR10,r1 /* 10: Decrementer */ 172*a47a12beSStefan Roese li r1,0x0b00 173*a47a12beSStefan Roese mtspr IVOR11,r1 /* 11: Interval timer */ 174*a47a12beSStefan Roese li r1,0x0c00 175*a47a12beSStefan Roese mtspr IVOR12,r1 /* 12: Watchdog timer */ 176*a47a12beSStefan Roese li r1,0x0d00 177*a47a12beSStefan Roese mtspr IVOR13,r1 /* 13: Data TLB error */ 178*a47a12beSStefan Roese li r1,0x0e00 179*a47a12beSStefan Roese mtspr IVOR14,r1 /* 14: Instruction TLB error */ 180*a47a12beSStefan Roese li r1,0x0f00 181*a47a12beSStefan Roese mtspr IVOR15,r1 /* 15: Debug */ 182*a47a12beSStefan Roese 183*a47a12beSStefan Roese /* Clear and set up some registers. */ 184*a47a12beSStefan Roese li r0,0x0000 185*a47a12beSStefan Roese lis r1,0xffff 186*a47a12beSStefan Roese mtspr DEC,r0 /* prevent dec exceptions */ 187*a47a12beSStefan Roese mttbl r0 /* prevent fit & wdt exceptions */ 188*a47a12beSStefan Roese mttbu r0 189*a47a12beSStefan Roese mtspr TSR,r1 /* clear all timer exception status */ 190*a47a12beSStefan Roese mtspr TCR,r0 /* disable all */ 191*a47a12beSStefan Roese mtspr ESR,r0 /* clear exception syndrome register */ 192*a47a12beSStefan Roese mtspr MCSR,r0 /* machine check syndrome register */ 193*a47a12beSStefan Roese mtxer r0 /* clear integer exception register */ 194*a47a12beSStefan Roese 195*a47a12beSStefan Roese#ifdef CONFIG_SYS_BOOK3E_HV 196*a47a12beSStefan Roese mtspr MAS8,r0 /* make sure MAS8 is clear */ 197*a47a12beSStefan Roese#endif 198*a47a12beSStefan Roese 199*a47a12beSStefan Roese /* Enable Time Base and Select Time Base Clock */ 200*a47a12beSStefan Roese lis r0,HID0_EMCP@h /* Enable machine check */ 201*a47a12beSStefan Roese#if defined(CONFIG_ENABLE_36BIT_PHYS) 202*a47a12beSStefan Roese ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 203*a47a12beSStefan Roese#endif 204*a47a12beSStefan Roese#ifndef CONFIG_E500MC 205*a47a12beSStefan Roese ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 206*a47a12beSStefan Roese#endif 207*a47a12beSStefan Roese mtspr HID0,r0 208*a47a12beSStefan Roese 209*a47a12beSStefan Roese#ifndef CONFIG_E500MC 210*a47a12beSStefan Roese li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 211*a47a12beSStefan Roese mfspr r3,PVR 212*a47a12beSStefan Roese andi. r3,r3, 0xff 213*a47a12beSStefan Roese cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 214*a47a12beSStefan Roese blt 1f 215*a47a12beSStefan Roese /* Set MBDD bit also */ 216*a47a12beSStefan Roese ori r0, r0, HID1_MBDD@l 217*a47a12beSStefan Roese1: 218*a47a12beSStefan Roese mtspr HID1,r0 219*a47a12beSStefan Roese#endif 220*a47a12beSStefan Roese 221*a47a12beSStefan Roese /* Enable Branch Prediction */ 222*a47a12beSStefan Roese#if defined(CONFIG_BTB) 223*a47a12beSStefan Roese lis r0,BUCSR_ENABLE@h 224*a47a12beSStefan Roese ori r0,r0,BUCSR_ENABLE@l 225*a47a12beSStefan Roese mtspr SPRN_BUCSR,r0 226*a47a12beSStefan Roese#endif 227*a47a12beSStefan Roese 228*a47a12beSStefan Roese#if defined(CONFIG_SYS_INIT_DBCR) 229*a47a12beSStefan Roese lis r1,0xffff 230*a47a12beSStefan Roese ori r1,r1,0xffff 231*a47a12beSStefan Roese mtspr DBSR,r1 /* Clear all status bits */ 232*a47a12beSStefan Roese lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 233*a47a12beSStefan Roese ori r0,r0,CONFIG_SYS_INIT_DBCR@l 234*a47a12beSStefan Roese mtspr DBCR0,r0 235*a47a12beSStefan Roese#endif 236*a47a12beSStefan Roese 237*a47a12beSStefan Roese#ifdef CONFIG_MPC8569 238*a47a12beSStefan Roese#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 239*a47a12beSStefan Roese#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 240*a47a12beSStefan Roese 241*a47a12beSStefan Roese /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 242*a47a12beSStefan Roese * use address space which is more than 12bits, and it must be done in 243*a47a12beSStefan Roese * the 4K boot page. So we set this bit here. 244*a47a12beSStefan Roese */ 245*a47a12beSStefan Roese 246*a47a12beSStefan Roese /* create a temp mapping TLB0[0] for LBCR */ 247*a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h 248*a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l 249*a47a12beSStefan Roese 250*a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 251*a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 252*a47a12beSStefan Roese 253*a47a12beSStefan Roese lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h 254*a47a12beSStefan Roese ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l 255*a47a12beSStefan Roese 256*a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 257*a47a12beSStefan Roese (MAS3_SX|MAS3_SW|MAS3_SR))@h 258*a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 259*a47a12beSStefan Roese (MAS3_SX|MAS3_SW|MAS3_SR))@l 260*a47a12beSStefan Roese 261*a47a12beSStefan Roese mtspr MAS0,r6 262*a47a12beSStefan Roese mtspr MAS1,r7 263*a47a12beSStefan Roese mtspr MAS2,r8 264*a47a12beSStefan Roese mtspr MAS3,r9 265*a47a12beSStefan Roese isync 266*a47a12beSStefan Roese msync 267*a47a12beSStefan Roese tlbwe 268*a47a12beSStefan Roese 269*a47a12beSStefan Roese /* Set LBCR register */ 270*a47a12beSStefan Roese lis r4,CONFIG_SYS_LBCR_ADDR@h 271*a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 272*a47a12beSStefan Roese 273*a47a12beSStefan Roese lis r5,CONFIG_SYS_LBC_LBCR@h 274*a47a12beSStefan Roese ori r5,r5,CONFIG_SYS_LBC_LBCR@l 275*a47a12beSStefan Roese stw r5,0(r4) 276*a47a12beSStefan Roese isync 277*a47a12beSStefan Roese 278*a47a12beSStefan Roese /* invalidate this temp TLB */ 279*a47a12beSStefan Roese lis r4,CONFIG_SYS_LBC_ADDR@h 280*a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_LBC_ADDR@l 281*a47a12beSStefan Roese tlbivax 0,r4 282*a47a12beSStefan Roese isync 283*a47a12beSStefan Roese 284*a47a12beSStefan Roese#endif /* CONFIG_MPC8569 */ 285*a47a12beSStefan Roese 286*a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 287*a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 288*a47a12beSStefan Roese 289*a47a12beSStefan Roese#ifndef CONFIG_SYS_RAMBOOT 290*a47a12beSStefan Roese /* create a temp mapping in AS=1 to the 4M boot window */ 291*a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h 292*a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l 293*a47a12beSStefan Roese 294*a47a12beSStefan Roese lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h 295*a47a12beSStefan Roese ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l 296*a47a12beSStefan Roese 297*a47a12beSStefan Roese /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 298*a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 299*a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 300*a47a12beSStefan Roese#else 301*a47a12beSStefan Roese /* 302*a47a12beSStefan Roese * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main 303*a47a12beSStefan Roese * image has been relocated to TEXT_BASE on the second stage. 304*a47a12beSStefan Roese */ 305*a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 306*a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 307*a47a12beSStefan Roese 308*a47a12beSStefan Roese lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h 309*a47a12beSStefan Roese ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l 310*a47a12beSStefan Roese 311*a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 312*a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 313*a47a12beSStefan Roese#endif 314*a47a12beSStefan Roese 315*a47a12beSStefan Roese mtspr MAS0,r6 316*a47a12beSStefan Roese mtspr MAS1,r7 317*a47a12beSStefan Roese mtspr MAS2,r8 318*a47a12beSStefan Roese mtspr MAS3,r9 319*a47a12beSStefan Roese isync 320*a47a12beSStefan Roese msync 321*a47a12beSStefan Roese tlbwe 322*a47a12beSStefan Roese 323*a47a12beSStefan Roese /* create a temp mapping in AS=1 to the stack */ 324*a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h 325*a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l 326*a47a12beSStefan Roese 327*a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h 328*a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l 329*a47a12beSStefan Roese 330*a47a12beSStefan Roese lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h 331*a47a12beSStefan Roese ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l 332*a47a12beSStefan Roese 333*a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 334*a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 335*a47a12beSStefan Roese 336*a47a12beSStefan Roese mtspr MAS0,r6 337*a47a12beSStefan Roese mtspr MAS1,r7 338*a47a12beSStefan Roese mtspr MAS2,r8 339*a47a12beSStefan Roese mtspr MAS3,r9 340*a47a12beSStefan Roese isync 341*a47a12beSStefan Roese msync 342*a47a12beSStefan Roese tlbwe 343*a47a12beSStefan Roese 344*a47a12beSStefan Roese lis r6,MSR_IS|MSR_DS@h 345*a47a12beSStefan Roese ori r6,r6,MSR_IS|MSR_DS@l 346*a47a12beSStefan Roese lis r7,switch_as@h 347*a47a12beSStefan Roese ori r7,r7,switch_as@l 348*a47a12beSStefan Roese 349*a47a12beSStefan Roese mtspr SPRN_SRR0,r7 350*a47a12beSStefan Roese mtspr SPRN_SRR1,r6 351*a47a12beSStefan Roese rfi 352*a47a12beSStefan Roese 353*a47a12beSStefan Roeseswitch_as: 354*a47a12beSStefan Roese/* L1 DCache is used for initial RAM */ 355*a47a12beSStefan Roese 356*a47a12beSStefan Roese /* Allocate Initial RAM in data cache. 357*a47a12beSStefan Roese */ 358*a47a12beSStefan Roese lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 359*a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 360*a47a12beSStefan Roese mfspr r2, L1CFG0 361*a47a12beSStefan Roese andi. r2, r2, 0x1ff 362*a47a12beSStefan Roese /* cache size * 1024 / (2 * L1 line size) */ 363*a47a12beSStefan Roese slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 364*a47a12beSStefan Roese mtctr r2 365*a47a12beSStefan Roese li r0,0 366*a47a12beSStefan Roese1: 367*a47a12beSStefan Roese dcbz r0,r3 368*a47a12beSStefan Roese dcbtls 0,r0,r3 369*a47a12beSStefan Roese addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 370*a47a12beSStefan Roese bdnz 1b 371*a47a12beSStefan Roese 372*a47a12beSStefan Roese /* Jump out the last 4K page and continue to 'normal' start */ 373*a47a12beSStefan Roese#ifdef CONFIG_SYS_RAMBOOT 374*a47a12beSStefan Roese b _start_cont 375*a47a12beSStefan Roese#else 376*a47a12beSStefan Roese /* Calculate absolute address in FLASH and jump there */ 377*a47a12beSStefan Roese /*--------------------------------------------------------------*/ 378*a47a12beSStefan Roese lis r3,CONFIG_SYS_MONITOR_BASE@h 379*a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 380*a47a12beSStefan Roese addi r3,r3,_start_cont - _start + _START_OFFSET 381*a47a12beSStefan Roese mtlr r3 382*a47a12beSStefan Roese blr 383*a47a12beSStefan Roese#endif 384*a47a12beSStefan Roese 385*a47a12beSStefan Roese .text 386*a47a12beSStefan Roese .globl _start 387*a47a12beSStefan Roese_start: 388*a47a12beSStefan Roese .long 0x27051956 /* U-BOOT Magic Number */ 389*a47a12beSStefan Roese .globl version_string 390*a47a12beSStefan Roeseversion_string: 391*a47a12beSStefan Roese .ascii U_BOOT_VERSION 392*a47a12beSStefan Roese .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" 393*a47a12beSStefan Roese .ascii CONFIG_IDENT_STRING, "\0" 394*a47a12beSStefan Roese 395*a47a12beSStefan Roese .align 4 396*a47a12beSStefan Roese .globl _start_cont 397*a47a12beSStefan Roese_start_cont: 398*a47a12beSStefan Roese /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 399*a47a12beSStefan Roese lis r1,CONFIG_SYS_INIT_RAM_ADDR@h 400*a47a12beSStefan Roese ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l 401*a47a12beSStefan Roese 402*a47a12beSStefan Roese li r0,0 403*a47a12beSStefan Roese stwu r0,-4(r1) 404*a47a12beSStefan Roese stwu r0,-4(r1) /* Terminate call chain */ 405*a47a12beSStefan Roese 406*a47a12beSStefan Roese stwu r1,-8(r1) /* Save back chain and move SP */ 407*a47a12beSStefan Roese lis r0,RESET_VECTOR@h /* Address of reset vector */ 408*a47a12beSStefan Roese ori r0,r0,RESET_VECTOR@l 409*a47a12beSStefan Roese stwu r1,-8(r1) /* Save back chain and move SP */ 410*a47a12beSStefan Roese stw r0,+12(r1) /* Save return addr (underflow vect) */ 411*a47a12beSStefan Roese 412*a47a12beSStefan Roese GET_GOT 413*a47a12beSStefan Roese bl cpu_init_early_f 414*a47a12beSStefan Roese 415*a47a12beSStefan Roese /* switch back to AS = 0 */ 416*a47a12beSStefan Roese lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 417*a47a12beSStefan Roese ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 418*a47a12beSStefan Roese mtmsr r3 419*a47a12beSStefan Roese isync 420*a47a12beSStefan Roese 421*a47a12beSStefan Roese bl cpu_init_f 422*a47a12beSStefan Roese bl board_init_f 423*a47a12beSStefan Roese isync 424*a47a12beSStefan Roese 425*a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 426*a47a12beSStefan Roese . = EXC_OFF_SYS_RESET 427*a47a12beSStefan Roese .globl _start_of_vectors 428*a47a12beSStefan Roese_start_of_vectors: 429*a47a12beSStefan Roese 430*a47a12beSStefan Roese/* Critical input. */ 431*a47a12beSStefan Roese CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 432*a47a12beSStefan Roese 433*a47a12beSStefan Roese/* Machine check */ 434*a47a12beSStefan Roese MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 435*a47a12beSStefan Roese 436*a47a12beSStefan Roese/* Data Storage exception. */ 437*a47a12beSStefan Roese STD_EXCEPTION(0x0300, DataStorage, UnknownException) 438*a47a12beSStefan Roese 439*a47a12beSStefan Roese/* Instruction Storage exception. */ 440*a47a12beSStefan Roese STD_EXCEPTION(0x0400, InstStorage, UnknownException) 441*a47a12beSStefan Roese 442*a47a12beSStefan Roese/* External Interrupt exception. */ 443*a47a12beSStefan Roese STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 444*a47a12beSStefan Roese 445*a47a12beSStefan Roese/* Alignment exception. */ 446*a47a12beSStefan Roese . = 0x0600 447*a47a12beSStefan RoeseAlignment: 448*a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 449*a47a12beSStefan Roese mfspr r4,DAR 450*a47a12beSStefan Roese stw r4,_DAR(r21) 451*a47a12beSStefan Roese mfspr r5,DSISR 452*a47a12beSStefan Roese stw r5,_DSISR(r21) 453*a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 454*a47a12beSStefan Roese EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 455*a47a12beSStefan Roese 456*a47a12beSStefan Roese/* Program check exception */ 457*a47a12beSStefan Roese . = 0x0700 458*a47a12beSStefan RoeseProgramCheck: 459*a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 460*a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 461*a47a12beSStefan Roese EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 462*a47a12beSStefan Roese MSR_KERNEL, COPY_EE) 463*a47a12beSStefan Roese 464*a47a12beSStefan Roese /* No FPU on MPC85xx. This exception is not supposed to happen. 465*a47a12beSStefan Roese */ 466*a47a12beSStefan Roese STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 467*a47a12beSStefan Roese 468*a47a12beSStefan Roese . = 0x0900 469*a47a12beSStefan Roese/* 470*a47a12beSStefan Roese * r0 - SYSCALL number 471*a47a12beSStefan Roese * r3-... arguments 472*a47a12beSStefan Roese */ 473*a47a12beSStefan RoeseSystemCall: 474*a47a12beSStefan Roese addis r11,r0,0 /* get functions table addr */ 475*a47a12beSStefan Roese ori r11,r11,0 /* Note: this code is patched in trap_init */ 476*a47a12beSStefan Roese addis r12,r0,0 /* get number of functions */ 477*a47a12beSStefan Roese ori r12,r12,0 478*a47a12beSStefan Roese 479*a47a12beSStefan Roese cmplw 0,r0,r12 480*a47a12beSStefan Roese bge 1f 481*a47a12beSStefan Roese 482*a47a12beSStefan Roese rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 483*a47a12beSStefan Roese add r11,r11,r0 484*a47a12beSStefan Roese lwz r11,0(r11) 485*a47a12beSStefan Roese 486*a47a12beSStefan Roese li r20,0xd00-4 /* Get stack pointer */ 487*a47a12beSStefan Roese lwz r12,0(r20) 488*a47a12beSStefan Roese subi r12,r12,12 /* Adjust stack pointer */ 489*a47a12beSStefan Roese li r0,0xc00+_end_back-SystemCall 490*a47a12beSStefan Roese cmplw 0,r0,r12 /* Check stack overflow */ 491*a47a12beSStefan Roese bgt 1f 492*a47a12beSStefan Roese stw r12,0(r20) 493*a47a12beSStefan Roese 494*a47a12beSStefan Roese mflr r0 495*a47a12beSStefan Roese stw r0,0(r12) 496*a47a12beSStefan Roese mfspr r0,SRR0 497*a47a12beSStefan Roese stw r0,4(r12) 498*a47a12beSStefan Roese mfspr r0,SRR1 499*a47a12beSStefan Roese stw r0,8(r12) 500*a47a12beSStefan Roese 501*a47a12beSStefan Roese li r12,0xc00+_back-SystemCall 502*a47a12beSStefan Roese mtlr r12 503*a47a12beSStefan Roese mtspr SRR0,r11 504*a47a12beSStefan Roese 505*a47a12beSStefan Roese1: SYNC 506*a47a12beSStefan Roese rfi 507*a47a12beSStefan Roese_back: 508*a47a12beSStefan Roese 509*a47a12beSStefan Roese mfmsr r11 /* Disable interrupts */ 510*a47a12beSStefan Roese li r12,0 511*a47a12beSStefan Roese ori r12,r12,MSR_EE 512*a47a12beSStefan Roese andc r11,r11,r12 513*a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 514*a47a12beSStefan Roese mtmsr r11 515*a47a12beSStefan Roese SYNC 516*a47a12beSStefan Roese 517*a47a12beSStefan Roese li r12,0xd00-4 /* restore regs */ 518*a47a12beSStefan Roese lwz r12,0(r12) 519*a47a12beSStefan Roese 520*a47a12beSStefan Roese lwz r11,0(r12) 521*a47a12beSStefan Roese mtlr r11 522*a47a12beSStefan Roese lwz r11,4(r12) 523*a47a12beSStefan Roese mtspr SRR0,r11 524*a47a12beSStefan Roese lwz r11,8(r12) 525*a47a12beSStefan Roese mtspr SRR1,r11 526*a47a12beSStefan Roese 527*a47a12beSStefan Roese addi r12,r12,12 /* Adjust stack pointer */ 528*a47a12beSStefan Roese li r20,0xd00-4 529*a47a12beSStefan Roese stw r12,0(r20) 530*a47a12beSStefan Roese 531*a47a12beSStefan Roese SYNC 532*a47a12beSStefan Roese rfi 533*a47a12beSStefan Roese_end_back: 534*a47a12beSStefan Roese 535*a47a12beSStefan Roese STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 536*a47a12beSStefan Roese STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 537*a47a12beSStefan Roese STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 538*a47a12beSStefan Roese 539*a47a12beSStefan Roese STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 540*a47a12beSStefan Roese STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 541*a47a12beSStefan Roese 542*a47a12beSStefan Roese CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 543*a47a12beSStefan Roese 544*a47a12beSStefan Roese .globl _end_of_vectors 545*a47a12beSStefan Roese_end_of_vectors: 546*a47a12beSStefan Roese 547*a47a12beSStefan Roese 548*a47a12beSStefan Roese . = . + (0x100 - ( . & 0xff )) /* align for debug */ 549*a47a12beSStefan Roese 550*a47a12beSStefan Roese/* 551*a47a12beSStefan Roese * This code finishes saving the registers to the exception frame 552*a47a12beSStefan Roese * and jumps to the appropriate handler for the exception. 553*a47a12beSStefan Roese * Register r21 is pointer into trap frame, r1 has new stack pointer. 554*a47a12beSStefan Roese */ 555*a47a12beSStefan Roese .globl transfer_to_handler 556*a47a12beSStefan Roesetransfer_to_handler: 557*a47a12beSStefan Roese stw r22,_NIP(r21) 558*a47a12beSStefan Roese lis r22,MSR_POW@h 559*a47a12beSStefan Roese andc r23,r23,r22 560*a47a12beSStefan Roese stw r23,_MSR(r21) 561*a47a12beSStefan Roese SAVE_GPR(7, r21) 562*a47a12beSStefan Roese SAVE_4GPRS(8, r21) 563*a47a12beSStefan Roese SAVE_8GPRS(12, r21) 564*a47a12beSStefan Roese SAVE_8GPRS(24, r21) 565*a47a12beSStefan Roese 566*a47a12beSStefan Roese mflr r23 567*a47a12beSStefan Roese andi. r24,r23,0x3f00 /* get vector offset */ 568*a47a12beSStefan Roese stw r24,TRAP(r21) 569*a47a12beSStefan Roese li r22,0 570*a47a12beSStefan Roese stw r22,RESULT(r21) 571*a47a12beSStefan Roese mtspr SPRG2,r22 /* r1 is now kernel sp */ 572*a47a12beSStefan Roese 573*a47a12beSStefan Roese lwz r24,0(r23) /* virtual address of handler */ 574*a47a12beSStefan Roese lwz r23,4(r23) /* where to go when done */ 575*a47a12beSStefan Roese mtspr SRR0,r24 576*a47a12beSStefan Roese mtspr SRR1,r20 577*a47a12beSStefan Roese mtlr r23 578*a47a12beSStefan Roese SYNC 579*a47a12beSStefan Roese rfi /* jump to handler, enable MMU */ 580*a47a12beSStefan Roese 581*a47a12beSStefan Roeseint_return: 582*a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 583*a47a12beSStefan Roese li r4,0 584*a47a12beSStefan Roese ori r4,r4,MSR_EE 585*a47a12beSStefan Roese andc r28,r28,r4 586*a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 587*a47a12beSStefan Roese mtmsr r28 588*a47a12beSStefan Roese SYNC 589*a47a12beSStefan Roese lwz r2,_CTR(r1) 590*a47a12beSStefan Roese lwz r0,_LINK(r1) 591*a47a12beSStefan Roese mtctr r2 592*a47a12beSStefan Roese mtlr r0 593*a47a12beSStefan Roese lwz r2,_XER(r1) 594*a47a12beSStefan Roese lwz r0,_CCR(r1) 595*a47a12beSStefan Roese mtspr XER,r2 596*a47a12beSStefan Roese mtcrf 0xFF,r0 597*a47a12beSStefan Roese REST_10GPRS(3, r1) 598*a47a12beSStefan Roese REST_10GPRS(13, r1) 599*a47a12beSStefan Roese REST_8GPRS(23, r1) 600*a47a12beSStefan Roese REST_GPR(31, r1) 601*a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 602*a47a12beSStefan Roese lwz r0,_MSR(r1) 603*a47a12beSStefan Roese mtspr SRR0,r2 604*a47a12beSStefan Roese mtspr SRR1,r0 605*a47a12beSStefan Roese lwz r0,GPR0(r1) 606*a47a12beSStefan Roese lwz r2,GPR2(r1) 607*a47a12beSStefan Roese lwz r1,GPR1(r1) 608*a47a12beSStefan Roese SYNC 609*a47a12beSStefan Roese rfi 610*a47a12beSStefan Roese 611*a47a12beSStefan Roesecrit_return: 612*a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 613*a47a12beSStefan Roese li r4,0 614*a47a12beSStefan Roese ori r4,r4,MSR_EE 615*a47a12beSStefan Roese andc r28,r28,r4 616*a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 617*a47a12beSStefan Roese mtmsr r28 618*a47a12beSStefan Roese SYNC 619*a47a12beSStefan Roese lwz r2,_CTR(r1) 620*a47a12beSStefan Roese lwz r0,_LINK(r1) 621*a47a12beSStefan Roese mtctr r2 622*a47a12beSStefan Roese mtlr r0 623*a47a12beSStefan Roese lwz r2,_XER(r1) 624*a47a12beSStefan Roese lwz r0,_CCR(r1) 625*a47a12beSStefan Roese mtspr XER,r2 626*a47a12beSStefan Roese mtcrf 0xFF,r0 627*a47a12beSStefan Roese REST_10GPRS(3, r1) 628*a47a12beSStefan Roese REST_10GPRS(13, r1) 629*a47a12beSStefan Roese REST_8GPRS(23, r1) 630*a47a12beSStefan Roese REST_GPR(31, r1) 631*a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 632*a47a12beSStefan Roese lwz r0,_MSR(r1) 633*a47a12beSStefan Roese mtspr SPRN_CSRR0,r2 634*a47a12beSStefan Roese mtspr SPRN_CSRR1,r0 635*a47a12beSStefan Roese lwz r0,GPR0(r1) 636*a47a12beSStefan Roese lwz r2,GPR2(r1) 637*a47a12beSStefan Roese lwz r1,GPR1(r1) 638*a47a12beSStefan Roese SYNC 639*a47a12beSStefan Roese rfci 640*a47a12beSStefan Roese 641*a47a12beSStefan Roesemck_return: 642*a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 643*a47a12beSStefan Roese li r4,0 644*a47a12beSStefan Roese ori r4,r4,MSR_EE 645*a47a12beSStefan Roese andc r28,r28,r4 646*a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 647*a47a12beSStefan Roese mtmsr r28 648*a47a12beSStefan Roese SYNC 649*a47a12beSStefan Roese lwz r2,_CTR(r1) 650*a47a12beSStefan Roese lwz r0,_LINK(r1) 651*a47a12beSStefan Roese mtctr r2 652*a47a12beSStefan Roese mtlr r0 653*a47a12beSStefan Roese lwz r2,_XER(r1) 654*a47a12beSStefan Roese lwz r0,_CCR(r1) 655*a47a12beSStefan Roese mtspr XER,r2 656*a47a12beSStefan Roese mtcrf 0xFF,r0 657*a47a12beSStefan Roese REST_10GPRS(3, r1) 658*a47a12beSStefan Roese REST_10GPRS(13, r1) 659*a47a12beSStefan Roese REST_8GPRS(23, r1) 660*a47a12beSStefan Roese REST_GPR(31, r1) 661*a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 662*a47a12beSStefan Roese lwz r0,_MSR(r1) 663*a47a12beSStefan Roese mtspr SPRN_MCSRR0,r2 664*a47a12beSStefan Roese mtspr SPRN_MCSRR1,r0 665*a47a12beSStefan Roese lwz r0,GPR0(r1) 666*a47a12beSStefan Roese lwz r2,GPR2(r1) 667*a47a12beSStefan Roese lwz r1,GPR1(r1) 668*a47a12beSStefan Roese SYNC 669*a47a12beSStefan Roese rfmci 670*a47a12beSStefan Roese 671*a47a12beSStefan Roese/* Cache functions. 672*a47a12beSStefan Roese*/ 673*a47a12beSStefan Roese.globl invalidate_icache 674*a47a12beSStefan Roeseinvalidate_icache: 675*a47a12beSStefan Roese mfspr r0,L1CSR1 676*a47a12beSStefan Roese ori r0,r0,L1CSR1_ICFI 677*a47a12beSStefan Roese msync 678*a47a12beSStefan Roese isync 679*a47a12beSStefan Roese mtspr L1CSR1,r0 680*a47a12beSStefan Roese isync 681*a47a12beSStefan Roese blr /* entire I cache */ 682*a47a12beSStefan Roese 683*a47a12beSStefan Roese.globl invalidate_dcache 684*a47a12beSStefan Roeseinvalidate_dcache: 685*a47a12beSStefan Roese mfspr r0,L1CSR0 686*a47a12beSStefan Roese ori r0,r0,L1CSR0_DCFI 687*a47a12beSStefan Roese msync 688*a47a12beSStefan Roese isync 689*a47a12beSStefan Roese mtspr L1CSR0,r0 690*a47a12beSStefan Roese isync 691*a47a12beSStefan Roese blr 692*a47a12beSStefan Roese 693*a47a12beSStefan Roese .globl icache_enable 694*a47a12beSStefan Roeseicache_enable: 695*a47a12beSStefan Roese mflr r8 696*a47a12beSStefan Roese bl invalidate_icache 697*a47a12beSStefan Roese mtlr r8 698*a47a12beSStefan Roese isync 699*a47a12beSStefan Roese mfspr r4,L1CSR1 700*a47a12beSStefan Roese ori r4,r4,0x0001 701*a47a12beSStefan Roese oris r4,r4,0x0001 702*a47a12beSStefan Roese mtspr L1CSR1,r4 703*a47a12beSStefan Roese isync 704*a47a12beSStefan Roese blr 705*a47a12beSStefan Roese 706*a47a12beSStefan Roese .globl icache_disable 707*a47a12beSStefan Roeseicache_disable: 708*a47a12beSStefan Roese mfspr r0,L1CSR1 709*a47a12beSStefan Roese lis r3,0 710*a47a12beSStefan Roese ori r3,r3,L1CSR1_ICE 711*a47a12beSStefan Roese andc r0,r0,r3 712*a47a12beSStefan Roese mtspr L1CSR1,r0 713*a47a12beSStefan Roese isync 714*a47a12beSStefan Roese blr 715*a47a12beSStefan Roese 716*a47a12beSStefan Roese .globl icache_status 717*a47a12beSStefan Roeseicache_status: 718*a47a12beSStefan Roese mfspr r3,L1CSR1 719*a47a12beSStefan Roese andi. r3,r3,L1CSR1_ICE 720*a47a12beSStefan Roese blr 721*a47a12beSStefan Roese 722*a47a12beSStefan Roese .globl dcache_enable 723*a47a12beSStefan Roesedcache_enable: 724*a47a12beSStefan Roese mflr r8 725*a47a12beSStefan Roese bl invalidate_dcache 726*a47a12beSStefan Roese mtlr r8 727*a47a12beSStefan Roese isync 728*a47a12beSStefan Roese mfspr r0,L1CSR0 729*a47a12beSStefan Roese ori r0,r0,0x0001 730*a47a12beSStefan Roese oris r0,r0,0x0001 731*a47a12beSStefan Roese msync 732*a47a12beSStefan Roese isync 733*a47a12beSStefan Roese mtspr L1CSR0,r0 734*a47a12beSStefan Roese isync 735*a47a12beSStefan Roese blr 736*a47a12beSStefan Roese 737*a47a12beSStefan Roese .globl dcache_disable 738*a47a12beSStefan Roesedcache_disable: 739*a47a12beSStefan Roese mfspr r3,L1CSR0 740*a47a12beSStefan Roese lis r4,0 741*a47a12beSStefan Roese ori r4,r4,L1CSR0_DCE 742*a47a12beSStefan Roese andc r3,r3,r4 743*a47a12beSStefan Roese mtspr L1CSR0,r0 744*a47a12beSStefan Roese isync 745*a47a12beSStefan Roese blr 746*a47a12beSStefan Roese 747*a47a12beSStefan Roese .globl dcache_status 748*a47a12beSStefan Roesedcache_status: 749*a47a12beSStefan Roese mfspr r3,L1CSR0 750*a47a12beSStefan Roese andi. r3,r3,L1CSR0_DCE 751*a47a12beSStefan Roese blr 752*a47a12beSStefan Roese 753*a47a12beSStefan Roese .globl get_pir 754*a47a12beSStefan Roeseget_pir: 755*a47a12beSStefan Roese mfspr r3,PIR 756*a47a12beSStefan Roese blr 757*a47a12beSStefan Roese 758*a47a12beSStefan Roese .globl get_pvr 759*a47a12beSStefan Roeseget_pvr: 760*a47a12beSStefan Roese mfspr r3,PVR 761*a47a12beSStefan Roese blr 762*a47a12beSStefan Roese 763*a47a12beSStefan Roese .globl get_svr 764*a47a12beSStefan Roeseget_svr: 765*a47a12beSStefan Roese mfspr r3,SVR 766*a47a12beSStefan Roese blr 767*a47a12beSStefan Roese 768*a47a12beSStefan Roese .globl wr_tcr 769*a47a12beSStefan Roesewr_tcr: 770*a47a12beSStefan Roese mtspr TCR,r3 771*a47a12beSStefan Roese blr 772*a47a12beSStefan Roese 773*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 774*a47a12beSStefan Roese/* Function: in8 */ 775*a47a12beSStefan Roese/* Description: Input 8 bits */ 776*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 777*a47a12beSStefan Roese .globl in8 778*a47a12beSStefan Roesein8: 779*a47a12beSStefan Roese lbz r3,0x0000(r3) 780*a47a12beSStefan Roese blr 781*a47a12beSStefan Roese 782*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 783*a47a12beSStefan Roese/* Function: out8 */ 784*a47a12beSStefan Roese/* Description: Output 8 bits */ 785*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 786*a47a12beSStefan Roese .globl out8 787*a47a12beSStefan Roeseout8: 788*a47a12beSStefan Roese stb r4,0x0000(r3) 789*a47a12beSStefan Roese sync 790*a47a12beSStefan Roese blr 791*a47a12beSStefan Roese 792*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 793*a47a12beSStefan Roese/* Function: out16 */ 794*a47a12beSStefan Roese/* Description: Output 16 bits */ 795*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 796*a47a12beSStefan Roese .globl out16 797*a47a12beSStefan Roeseout16: 798*a47a12beSStefan Roese sth r4,0x0000(r3) 799*a47a12beSStefan Roese sync 800*a47a12beSStefan Roese blr 801*a47a12beSStefan Roese 802*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 803*a47a12beSStefan Roese/* Function: out16r */ 804*a47a12beSStefan Roese/* Description: Byte reverse and output 16 bits */ 805*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 806*a47a12beSStefan Roese .globl out16r 807*a47a12beSStefan Roeseout16r: 808*a47a12beSStefan Roese sthbrx r4,r0,r3 809*a47a12beSStefan Roese sync 810*a47a12beSStefan Roese blr 811*a47a12beSStefan Roese 812*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 813*a47a12beSStefan Roese/* Function: out32 */ 814*a47a12beSStefan Roese/* Description: Output 32 bits */ 815*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 816*a47a12beSStefan Roese .globl out32 817*a47a12beSStefan Roeseout32: 818*a47a12beSStefan Roese stw r4,0x0000(r3) 819*a47a12beSStefan Roese sync 820*a47a12beSStefan Roese blr 821*a47a12beSStefan Roese 822*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 823*a47a12beSStefan Roese/* Function: out32r */ 824*a47a12beSStefan Roese/* Description: Byte reverse and output 32 bits */ 825*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 826*a47a12beSStefan Roese .globl out32r 827*a47a12beSStefan Roeseout32r: 828*a47a12beSStefan Roese stwbrx r4,r0,r3 829*a47a12beSStefan Roese sync 830*a47a12beSStefan Roese blr 831*a47a12beSStefan Roese 832*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 833*a47a12beSStefan Roese/* Function: in16 */ 834*a47a12beSStefan Roese/* Description: Input 16 bits */ 835*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 836*a47a12beSStefan Roese .globl in16 837*a47a12beSStefan Roesein16: 838*a47a12beSStefan Roese lhz r3,0x0000(r3) 839*a47a12beSStefan Roese blr 840*a47a12beSStefan Roese 841*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 842*a47a12beSStefan Roese/* Function: in16r */ 843*a47a12beSStefan Roese/* Description: Input 16 bits and byte reverse */ 844*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 845*a47a12beSStefan Roese .globl in16r 846*a47a12beSStefan Roesein16r: 847*a47a12beSStefan Roese lhbrx r3,r0,r3 848*a47a12beSStefan Roese blr 849*a47a12beSStefan Roese 850*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 851*a47a12beSStefan Roese/* Function: in32 */ 852*a47a12beSStefan Roese/* Description: Input 32 bits */ 853*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 854*a47a12beSStefan Roese .globl in32 855*a47a12beSStefan Roesein32: 856*a47a12beSStefan Roese lwz 3,0x0000(3) 857*a47a12beSStefan Roese blr 858*a47a12beSStefan Roese 859*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 860*a47a12beSStefan Roese/* Function: in32r */ 861*a47a12beSStefan Roese/* Description: Input 32 bits and byte reverse */ 862*a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 863*a47a12beSStefan Roese .globl in32r 864*a47a12beSStefan Roesein32r: 865*a47a12beSStefan Roese lwbrx r3,r0,r3 866*a47a12beSStefan Roese blr 867*a47a12beSStefan Roese#endif /* !CONFIG_NAND_SPL */ 868*a47a12beSStefan Roese 869*a47a12beSStefan Roese/*------------------------------------------------------------------------------*/ 870*a47a12beSStefan Roese 871*a47a12beSStefan Roese/* 872*a47a12beSStefan Roese * void write_tlb(mas0, mas1, mas2, mas3, mas7) 873*a47a12beSStefan Roese */ 874*a47a12beSStefan Roese .globl write_tlb 875*a47a12beSStefan Roesewrite_tlb: 876*a47a12beSStefan Roese mtspr MAS0,r3 877*a47a12beSStefan Roese mtspr MAS1,r4 878*a47a12beSStefan Roese mtspr MAS2,r5 879*a47a12beSStefan Roese mtspr MAS3,r6 880*a47a12beSStefan Roese#ifdef CONFIG_ENABLE_36BIT_PHYS 881*a47a12beSStefan Roese mtspr MAS7,r7 882*a47a12beSStefan Roese#endif 883*a47a12beSStefan Roese li r3,0 884*a47a12beSStefan Roese#ifdef CONFIG_SYS_BOOK3E_HV 885*a47a12beSStefan Roese mtspr MAS8,r3 886*a47a12beSStefan Roese#endif 887*a47a12beSStefan Roese isync 888*a47a12beSStefan Roese tlbwe 889*a47a12beSStefan Roese msync 890*a47a12beSStefan Roese isync 891*a47a12beSStefan Roese blr 892*a47a12beSStefan Roese 893*a47a12beSStefan Roese/* 894*a47a12beSStefan Roese * void relocate_code (addr_sp, gd, addr_moni) 895*a47a12beSStefan Roese * 896*a47a12beSStefan Roese * This "function" does not return, instead it continues in RAM 897*a47a12beSStefan Roese * after relocating the monitor code. 898*a47a12beSStefan Roese * 899*a47a12beSStefan Roese * r3 = dest 900*a47a12beSStefan Roese * r4 = src 901*a47a12beSStefan Roese * r5 = length in bytes 902*a47a12beSStefan Roese * r6 = cachelinesize 903*a47a12beSStefan Roese */ 904*a47a12beSStefan Roese .globl relocate_code 905*a47a12beSStefan Roeserelocate_code: 906*a47a12beSStefan Roese mr r1,r3 /* Set new stack pointer */ 907*a47a12beSStefan Roese mr r9,r4 /* Save copy of Init Data pointer */ 908*a47a12beSStefan Roese mr r10,r5 /* Save copy of Destination Address */ 909*a47a12beSStefan Roese 910*a47a12beSStefan Roese GET_GOT 911*a47a12beSStefan Roese mr r3,r5 /* Destination Address */ 912*a47a12beSStefan Roese lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 913*a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 914*a47a12beSStefan Roese lwz r5,GOT(__init_end) 915*a47a12beSStefan Roese sub r5,r5,r4 916*a47a12beSStefan Roese li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 917*a47a12beSStefan Roese 918*a47a12beSStefan Roese /* 919*a47a12beSStefan Roese * Fix GOT pointer: 920*a47a12beSStefan Roese * 921*a47a12beSStefan Roese * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 922*a47a12beSStefan Roese * 923*a47a12beSStefan Roese * Offset: 924*a47a12beSStefan Roese */ 925*a47a12beSStefan Roese sub r15,r10,r4 926*a47a12beSStefan Roese 927*a47a12beSStefan Roese /* First our own GOT */ 928*a47a12beSStefan Roese add r12,r12,r15 929*a47a12beSStefan Roese /* the the one used by the C code */ 930*a47a12beSStefan Roese add r30,r30,r15 931*a47a12beSStefan Roese 932*a47a12beSStefan Roese /* 933*a47a12beSStefan Roese * Now relocate code 934*a47a12beSStefan Roese */ 935*a47a12beSStefan Roese 936*a47a12beSStefan Roese cmplw cr1,r3,r4 937*a47a12beSStefan Roese addi r0,r5,3 938*a47a12beSStefan Roese srwi. r0,r0,2 939*a47a12beSStefan Roese beq cr1,4f /* In place copy is not necessary */ 940*a47a12beSStefan Roese beq 7f /* Protect against 0 count */ 941*a47a12beSStefan Roese mtctr r0 942*a47a12beSStefan Roese bge cr1,2f 943*a47a12beSStefan Roese 944*a47a12beSStefan Roese la r8,-4(r4) 945*a47a12beSStefan Roese la r7,-4(r3) 946*a47a12beSStefan Roese1: lwzu r0,4(r8) 947*a47a12beSStefan Roese stwu r0,4(r7) 948*a47a12beSStefan Roese bdnz 1b 949*a47a12beSStefan Roese b 4f 950*a47a12beSStefan Roese 951*a47a12beSStefan Roese2: slwi r0,r0,2 952*a47a12beSStefan Roese add r8,r4,r0 953*a47a12beSStefan Roese add r7,r3,r0 954*a47a12beSStefan Roese3: lwzu r0,-4(r8) 955*a47a12beSStefan Roese stwu r0,-4(r7) 956*a47a12beSStefan Roese bdnz 3b 957*a47a12beSStefan Roese 958*a47a12beSStefan Roese/* 959*a47a12beSStefan Roese * Now flush the cache: note that we must start from a cache aligned 960*a47a12beSStefan Roese * address. Otherwise we might miss one cache line. 961*a47a12beSStefan Roese */ 962*a47a12beSStefan Roese4: cmpwi r6,0 963*a47a12beSStefan Roese add r5,r3,r5 964*a47a12beSStefan Roese beq 7f /* Always flush prefetch queue in any case */ 965*a47a12beSStefan Roese subi r0,r6,1 966*a47a12beSStefan Roese andc r3,r3,r0 967*a47a12beSStefan Roese mr r4,r3 968*a47a12beSStefan Roese5: dcbst 0,r4 969*a47a12beSStefan Roese add r4,r4,r6 970*a47a12beSStefan Roese cmplw r4,r5 971*a47a12beSStefan Roese blt 5b 972*a47a12beSStefan Roese sync /* Wait for all dcbst to complete on bus */ 973*a47a12beSStefan Roese mr r4,r3 974*a47a12beSStefan Roese6: icbi 0,r4 975*a47a12beSStefan Roese add r4,r4,r6 976*a47a12beSStefan Roese cmplw r4,r5 977*a47a12beSStefan Roese blt 6b 978*a47a12beSStefan Roese7: sync /* Wait for all icbi to complete on bus */ 979*a47a12beSStefan Roese isync 980*a47a12beSStefan Roese 981*a47a12beSStefan Roese /* 982*a47a12beSStefan Roese * Re-point the IVPR at RAM 983*a47a12beSStefan Roese */ 984*a47a12beSStefan Roese mtspr IVPR,r10 985*a47a12beSStefan Roese 986*a47a12beSStefan Roese/* 987*a47a12beSStefan Roese * We are done. Do not return, instead branch to second part of board 988*a47a12beSStefan Roese * initialization, now running from RAM. 989*a47a12beSStefan Roese */ 990*a47a12beSStefan Roese 991*a47a12beSStefan Roese addi r0,r10,in_ram - _start + _START_OFFSET 992*a47a12beSStefan Roese mtlr r0 993*a47a12beSStefan Roese blr /* NEVER RETURNS! */ 994*a47a12beSStefan Roese .globl in_ram 995*a47a12beSStefan Roesein_ram: 996*a47a12beSStefan Roese 997*a47a12beSStefan Roese /* 998*a47a12beSStefan Roese * Relocation Function, r12 point to got2+0x8000 999*a47a12beSStefan Roese * 1000*a47a12beSStefan Roese * Adjust got2 pointers, no need to check for 0, this code 1001*a47a12beSStefan Roese * already puts a few entries in the table. 1002*a47a12beSStefan Roese */ 1003*a47a12beSStefan Roese li r0,__got2_entries@sectoff@l 1004*a47a12beSStefan Roese la r3,GOT(_GOT2_TABLE_) 1005*a47a12beSStefan Roese lwz r11,GOT(_GOT2_TABLE_) 1006*a47a12beSStefan Roese mtctr r0 1007*a47a12beSStefan Roese sub r11,r3,r11 1008*a47a12beSStefan Roese addi r3,r3,-4 1009*a47a12beSStefan Roese1: lwzu r0,4(r3) 1010*a47a12beSStefan Roese cmpwi r0,0 1011*a47a12beSStefan Roese beq- 2f 1012*a47a12beSStefan Roese add r0,r0,r11 1013*a47a12beSStefan Roese stw r0,0(r3) 1014*a47a12beSStefan Roese2: bdnz 1b 1015*a47a12beSStefan Roese 1016*a47a12beSStefan Roese /* 1017*a47a12beSStefan Roese * Now adjust the fixups and the pointers to the fixups 1018*a47a12beSStefan Roese * in case we need to move ourselves again. 1019*a47a12beSStefan Roese */ 1020*a47a12beSStefan Roese li r0,__fixup_entries@sectoff@l 1021*a47a12beSStefan Roese lwz r3,GOT(_FIXUP_TABLE_) 1022*a47a12beSStefan Roese cmpwi r0,0 1023*a47a12beSStefan Roese mtctr r0 1024*a47a12beSStefan Roese addi r3,r3,-4 1025*a47a12beSStefan Roese beq 4f 1026*a47a12beSStefan Roese3: lwzu r4,4(r3) 1027*a47a12beSStefan Roese lwzux r0,r4,r11 1028*a47a12beSStefan Roese add r0,r0,r11 1029*a47a12beSStefan Roese stw r10,0(r3) 1030*a47a12beSStefan Roese stw r0,0(r4) 1031*a47a12beSStefan Roese bdnz 3b 1032*a47a12beSStefan Roese4: 1033*a47a12beSStefan Roeseclear_bss: 1034*a47a12beSStefan Roese /* 1035*a47a12beSStefan Roese * Now clear BSS segment 1036*a47a12beSStefan Roese */ 1037*a47a12beSStefan Roese lwz r3,GOT(__bss_start) 1038*a47a12beSStefan Roese lwz r4,GOT(_end) 1039*a47a12beSStefan Roese 1040*a47a12beSStefan Roese cmplw 0,r3,r4 1041*a47a12beSStefan Roese beq 6f 1042*a47a12beSStefan Roese 1043*a47a12beSStefan Roese li r0,0 1044*a47a12beSStefan Roese5: 1045*a47a12beSStefan Roese stw r0,0(r3) 1046*a47a12beSStefan Roese addi r3,r3,4 1047*a47a12beSStefan Roese cmplw 0,r3,r4 1048*a47a12beSStefan Roese bne 5b 1049*a47a12beSStefan Roese6: 1050*a47a12beSStefan Roese 1051*a47a12beSStefan Roese mr r3,r9 /* Init Data pointer */ 1052*a47a12beSStefan Roese mr r4,r10 /* Destination Address */ 1053*a47a12beSStefan Roese bl board_init_r 1054*a47a12beSStefan Roese 1055*a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 1056*a47a12beSStefan Roese /* 1057*a47a12beSStefan Roese * Copy exception vector code to low memory 1058*a47a12beSStefan Roese * 1059*a47a12beSStefan Roese * r3: dest_addr 1060*a47a12beSStefan Roese * r7: source address, r8: end address, r9: target address 1061*a47a12beSStefan Roese */ 1062*a47a12beSStefan Roese .globl trap_init 1063*a47a12beSStefan Roesetrap_init: 1064*a47a12beSStefan Roese mflr r4 /* save link register */ 1065*a47a12beSStefan Roese GET_GOT 1066*a47a12beSStefan Roese lwz r7,GOT(_start_of_vectors) 1067*a47a12beSStefan Roese lwz r8,GOT(_end_of_vectors) 1068*a47a12beSStefan Roese 1069*a47a12beSStefan Roese li r9,0x100 /* reset vector always at 0x100 */ 1070*a47a12beSStefan Roese 1071*a47a12beSStefan Roese cmplw 0,r7,r8 1072*a47a12beSStefan Roese bgelr /* return if r7>=r8 - just in case */ 1073*a47a12beSStefan Roese1: 1074*a47a12beSStefan Roese lwz r0,0(r7) 1075*a47a12beSStefan Roese stw r0,0(r9) 1076*a47a12beSStefan Roese addi r7,r7,4 1077*a47a12beSStefan Roese addi r9,r9,4 1078*a47a12beSStefan Roese cmplw 0,r7,r8 1079*a47a12beSStefan Roese bne 1b 1080*a47a12beSStefan Roese 1081*a47a12beSStefan Roese /* 1082*a47a12beSStefan Roese * relocate `hdlr' and `int_return' entries 1083*a47a12beSStefan Roese */ 1084*a47a12beSStefan Roese li r7,.L_CriticalInput - _start + _START_OFFSET 1085*a47a12beSStefan Roese bl trap_reloc 1086*a47a12beSStefan Roese li r7,.L_MachineCheck - _start + _START_OFFSET 1087*a47a12beSStefan Roese bl trap_reloc 1088*a47a12beSStefan Roese li r7,.L_DataStorage - _start + _START_OFFSET 1089*a47a12beSStefan Roese bl trap_reloc 1090*a47a12beSStefan Roese li r7,.L_InstStorage - _start + _START_OFFSET 1091*a47a12beSStefan Roese bl trap_reloc 1092*a47a12beSStefan Roese li r7,.L_ExtInterrupt - _start + _START_OFFSET 1093*a47a12beSStefan Roese bl trap_reloc 1094*a47a12beSStefan Roese li r7,.L_Alignment - _start + _START_OFFSET 1095*a47a12beSStefan Roese bl trap_reloc 1096*a47a12beSStefan Roese li r7,.L_ProgramCheck - _start + _START_OFFSET 1097*a47a12beSStefan Roese bl trap_reloc 1098*a47a12beSStefan Roese li r7,.L_FPUnavailable - _start + _START_OFFSET 1099*a47a12beSStefan Roese bl trap_reloc 1100*a47a12beSStefan Roese li r7,.L_Decrementer - _start + _START_OFFSET 1101*a47a12beSStefan Roese bl trap_reloc 1102*a47a12beSStefan Roese li r7,.L_IntervalTimer - _start + _START_OFFSET 1103*a47a12beSStefan Roese li r8,_end_of_vectors - _start + _START_OFFSET 1104*a47a12beSStefan Roese2: 1105*a47a12beSStefan Roese bl trap_reloc 1106*a47a12beSStefan Roese addi r7,r7,0x100 /* next exception vector */ 1107*a47a12beSStefan Roese cmplw 0,r7,r8 1108*a47a12beSStefan Roese blt 2b 1109*a47a12beSStefan Roese 1110*a47a12beSStefan Roese lis r7,0x0 1111*a47a12beSStefan Roese mtspr IVPR,r7 1112*a47a12beSStefan Roese 1113*a47a12beSStefan Roese mtlr r4 /* restore link register */ 1114*a47a12beSStefan Roese blr 1115*a47a12beSStefan Roese 1116*a47a12beSStefan Roese.globl unlock_ram_in_cache 1117*a47a12beSStefan Roeseunlock_ram_in_cache: 1118*a47a12beSStefan Roese /* invalidate the INIT_RAM section */ 1119*a47a12beSStefan Roese lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1120*a47a12beSStefan Roese ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1121*a47a12beSStefan Roese mfspr r4,L1CFG0 1122*a47a12beSStefan Roese andi. r4,r4,0x1ff 1123*a47a12beSStefan Roese slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1124*a47a12beSStefan Roese mtctr r4 1125*a47a12beSStefan Roese1: dcbi r0,r3 1126*a47a12beSStefan Roese addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1127*a47a12beSStefan Roese bdnz 1b 1128*a47a12beSStefan Roese sync 1129*a47a12beSStefan Roese 1130*a47a12beSStefan Roese /* Invalidate the TLB entries for the cache */ 1131*a47a12beSStefan Roese lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1132*a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1133*a47a12beSStefan Roese tlbivax 0,r3 1134*a47a12beSStefan Roese addi r3,r3,0x1000 1135*a47a12beSStefan Roese tlbivax 0,r3 1136*a47a12beSStefan Roese addi r3,r3,0x1000 1137*a47a12beSStefan Roese tlbivax 0,r3 1138*a47a12beSStefan Roese addi r3,r3,0x1000 1139*a47a12beSStefan Roese tlbivax 0,r3 1140*a47a12beSStefan Roese isync 1141*a47a12beSStefan Roese blr 1142*a47a12beSStefan Roese 1143*a47a12beSStefan Roese.globl flush_dcache 1144*a47a12beSStefan Roeseflush_dcache: 1145*a47a12beSStefan Roese mfspr r3,SPRN_L1CFG0 1146*a47a12beSStefan Roese 1147*a47a12beSStefan Roese rlwinm r5,r3,9,3 /* Extract cache block size */ 1148*a47a12beSStefan Roese twlgti r5,1 /* Only 32 and 64 byte cache blocks 1149*a47a12beSStefan Roese * are currently defined. 1150*a47a12beSStefan Roese */ 1151*a47a12beSStefan Roese li r4,32 1152*a47a12beSStefan Roese subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1153*a47a12beSStefan Roese * log2(number of ways) 1154*a47a12beSStefan Roese */ 1155*a47a12beSStefan Roese slw r5,r4,r5 /* r5 = cache block size */ 1156*a47a12beSStefan Roese 1157*a47a12beSStefan Roese rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1158*a47a12beSStefan Roese mulli r7,r7,13 /* An 8-way cache will require 13 1159*a47a12beSStefan Roese * loads per set. 1160*a47a12beSStefan Roese */ 1161*a47a12beSStefan Roese slw r7,r7,r6 1162*a47a12beSStefan Roese 1163*a47a12beSStefan Roese /* save off HID0 and set DCFA */ 1164*a47a12beSStefan Roese mfspr r8,SPRN_HID0 1165*a47a12beSStefan Roese ori r9,r8,HID0_DCFA@l 1166*a47a12beSStefan Roese mtspr SPRN_HID0,r9 1167*a47a12beSStefan Roese isync 1168*a47a12beSStefan Roese 1169*a47a12beSStefan Roese lis r4,0 1170*a47a12beSStefan Roese mtctr r7 1171*a47a12beSStefan Roese 1172*a47a12beSStefan Roese1: lwz r3,0(r4) /* Load... */ 1173*a47a12beSStefan Roese add r4,r4,r5 1174*a47a12beSStefan Roese bdnz 1b 1175*a47a12beSStefan Roese 1176*a47a12beSStefan Roese msync 1177*a47a12beSStefan Roese lis r4,0 1178*a47a12beSStefan Roese mtctr r7 1179*a47a12beSStefan Roese 1180*a47a12beSStefan Roese1: dcbf 0,r4 /* ...and flush. */ 1181*a47a12beSStefan Roese add r4,r4,r5 1182*a47a12beSStefan Roese bdnz 1b 1183*a47a12beSStefan Roese 1184*a47a12beSStefan Roese /* restore HID0 */ 1185*a47a12beSStefan Roese mtspr SPRN_HID0,r8 1186*a47a12beSStefan Roese isync 1187*a47a12beSStefan Roese 1188*a47a12beSStefan Roese blr 1189*a47a12beSStefan Roese 1190*a47a12beSStefan Roese.globl setup_ivors 1191*a47a12beSStefan Roesesetup_ivors: 1192*a47a12beSStefan Roese 1193*a47a12beSStefan Roese#include "fixed_ivor.S" 1194*a47a12beSStefan Roese blr 1195*a47a12beSStefan Roese#endif /* !CONFIG_NAND_SPL */ 1196