1a47a12beSStefan Roese/* 2a4107f86SPrabhakar Kushwaha * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * Copyright (C) 2003 Motorola,Inc. 4a47a12beSStefan Roese * 5a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6a47a12beSStefan Roese * project. 7a47a12beSStefan Roese * 8a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11a47a12beSStefan Roese * the License, or (at your option) any later version. 12a47a12beSStefan Roese * 13a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16a47a12beSStefan Roese * GNU General Public License for more details. 17a47a12beSStefan Roese * 18a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21a47a12beSStefan Roese * MA 02111-1307 USA 22a47a12beSStefan Roese */ 23a47a12beSStefan Roese 24a47a12beSStefan Roese/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 25a47a12beSStefan Roese * 26a47a12beSStefan Roese * The processor starts at 0xfffffffc and the code is first executed in the 27a47a12beSStefan Roese * last 4K page(0xfffff000-0xffffffff) in flash/rom. 28a47a12beSStefan Roese * 29a47a12beSStefan Roese */ 30a47a12beSStefan Roese 3125ddd1fbSWolfgang Denk#include <asm-offsets.h> 32a47a12beSStefan Roese#include <config.h> 33a47a12beSStefan Roese#include <mpc85xx.h> 34a47a12beSStefan Roese#include <version.h> 35a47a12beSStefan Roese 36a47a12beSStefan Roese#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37a47a12beSStefan Roese 38a47a12beSStefan Roese#include <ppc_asm.tmpl> 39a47a12beSStefan Roese#include <ppc_defs.h> 40a47a12beSStefan Roese 41a47a12beSStefan Roese#include <asm/cache.h> 42a47a12beSStefan Roese#include <asm/mmu.h> 43a47a12beSStefan Roese 44a47a12beSStefan Roese#undef MSR_KERNEL 45a47a12beSStefan Roese#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 46a47a12beSStefan Roese 47a47a12beSStefan Roese/* 48a47a12beSStefan Roese * Set up GOT: Global Offset Table 49a47a12beSStefan Roese * 50a47a12beSStefan Roese * Use r12 to access the GOT 51a47a12beSStefan Roese */ 52a47a12beSStefan Roese START_GOT 53a47a12beSStefan Roese GOT_ENTRY(_GOT2_TABLE_) 54a47a12beSStefan Roese GOT_ENTRY(_FIXUP_TABLE_) 55a47a12beSStefan Roese 56a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 57a47a12beSStefan Roese GOT_ENTRY(_start) 58a47a12beSStefan Roese GOT_ENTRY(_start_of_vectors) 59a47a12beSStefan Roese GOT_ENTRY(_end_of_vectors) 60a47a12beSStefan Roese GOT_ENTRY(transfer_to_handler) 61a47a12beSStefan Roese#endif 62a47a12beSStefan Roese 63a47a12beSStefan Roese GOT_ENTRY(__init_end) 6444c6e659SPo-Yu Chuang GOT_ENTRY(__bss_end__) 65a47a12beSStefan Roese GOT_ENTRY(__bss_start) 66a47a12beSStefan Roese END_GOT 67a47a12beSStefan Roese 68a47a12beSStefan Roese/* 69a47a12beSStefan Roese * e500 Startup -- after reset only the last 4KB of the effective 70a47a12beSStefan Roese * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 71a47a12beSStefan Roese * section is located at THIS LAST page and basically does three 72a47a12beSStefan Roese * things: clear some registers, set up exception tables and 73a47a12beSStefan Roese * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 74a47a12beSStefan Roese * continue the boot procedure. 75a47a12beSStefan Roese 76a47a12beSStefan Roese * Once the boot rom is mapped by TLB entries we can proceed 77a47a12beSStefan Roese * with normal startup. 78a47a12beSStefan Roese * 79a47a12beSStefan Roese */ 80a47a12beSStefan Roese 81a47a12beSStefan Roese .section .bootpg,"ax" 82a47a12beSStefan Roese .globl _start_e500 83a47a12beSStefan Roese 84a47a12beSStefan Roese_start_e500: 855344f7a2SPrabhakar Kushwaha/* Enable debug exception */ 865344f7a2SPrabhakar Kushwaha li r1,MSR_DE 875344f7a2SPrabhakar Kushwaha mtmsr r1 88a47a12beSStefan Roese 8933eee330SScott Wood#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 9033eee330SScott Wood mfspr r3,SPRN_SVR 9133eee330SScott Wood rlwinm r3,r3,0,0xff 9233eee330SScott Wood li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 9333eee330SScott Wood cmpw r3,r4 9433eee330SScott Wood beq 1f 9533eee330SScott Wood 9633eee330SScott Wood#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 9733eee330SScott Wood li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 9833eee330SScott Wood cmpw r3,r4 9933eee330SScott Wood beq 1f 10033eee330SScott Wood#endif 10133eee330SScott Wood 10233eee330SScott Wood /* Not a supported revision affected by erratum */ 10333eee330SScott Wood li r27,0 10433eee330SScott Wood b 2f 10533eee330SScott Wood 10633eee330SScott Wood1: li r27,1 /* Remember for later that we have the erratum */ 10733eee330SScott Wood /* Erratum says set bits 55:60 to 001001 */ 10833eee330SScott Wood msync 10933eee330SScott Wood isync 11033eee330SScott Wood mfspr r3,976 11133eee330SScott Wood li r4,0x48 11233eee330SScott Wood rlwimi r3,r4,0,0x1f8 11333eee330SScott Wood mtspr 976,r3 11433eee330SScott Wood isync 11533eee330SScott Wood2: 11633eee330SScott Wood#endif 11733eee330SScott Wood 1187065b7d4SRuchika Gupta#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) 1197065b7d4SRuchika Gupta /* ISBC uses L2 as stack. 1207065b7d4SRuchika Gupta * Disable L2 cache here so that u-boot can enable it later 1217065b7d4SRuchika Gupta * as part of it's normal flow 1227065b7d4SRuchika Gupta */ 1237065b7d4SRuchika Gupta 1247065b7d4SRuchika Gupta /* Check if L2 is enabled */ 1257065b7d4SRuchika Gupta mfspr r3, SPRN_L2CSR0 1267065b7d4SRuchika Gupta lis r2, L2CSR0_L2E@h 1277065b7d4SRuchika Gupta ori r2, r2, L2CSR0_L2E@l 1287065b7d4SRuchika Gupta and. r4, r3, r2 1297065b7d4SRuchika Gupta beq l2_disabled 1307065b7d4SRuchika Gupta 1317065b7d4SRuchika Gupta mfspr r3, SPRN_L2CSR0 1327065b7d4SRuchika Gupta /* Flush L2 cache */ 1337065b7d4SRuchika Gupta lis r2,(L2CSR0_L2FL)@h 1347065b7d4SRuchika Gupta ori r2, r2, (L2CSR0_L2FL)@l 1357065b7d4SRuchika Gupta or r3, r2, r3 1367065b7d4SRuchika Gupta sync 1377065b7d4SRuchika Gupta isync 1387065b7d4SRuchika Gupta mtspr SPRN_L2CSR0,r3 1397065b7d4SRuchika Gupta isync 1407065b7d4SRuchika Gupta1: 1417065b7d4SRuchika Gupta mfspr r3, SPRN_L2CSR0 1427065b7d4SRuchika Gupta and. r1, r3, r2 1437065b7d4SRuchika Gupta bne 1b 1447065b7d4SRuchika Gupta 1457065b7d4SRuchika Gupta mfspr r3, SPRN_L2CSR0 1467065b7d4SRuchika Gupta lis r2, L2CSR0_L2E@h 1477065b7d4SRuchika Gupta ori r2, r2, L2CSR0_L2E@l 1487065b7d4SRuchika Gupta andc r4, r3, r2 1497065b7d4SRuchika Gupta sync 1507065b7d4SRuchika Gupta isync 1517065b7d4SRuchika Gupta mtspr SPRN_L2CSR0,r4 1527065b7d4SRuchika Gupta isync 1537065b7d4SRuchika Gupta 1547065b7d4SRuchika Guptal2_disabled: 1557065b7d4SRuchika Gupta#endif 1567065b7d4SRuchika Gupta 157a47a12beSStefan Roese/* clear registers/arrays not reset by hardware */ 158a47a12beSStefan Roese 159a47a12beSStefan Roese /* L1 */ 160a47a12beSStefan Roese li r0,2 161a47a12beSStefan Roese mtspr L1CSR0,r0 /* invalidate d-cache */ 162a47a12beSStefan Roese mtspr L1CSR1,r0 /* invalidate i-cache */ 163a47a12beSStefan Roese 164a47a12beSStefan Roese mfspr r1,DBSR 165a47a12beSStefan Roese mtspr DBSR,r1 /* Clear all valid bits */ 166a47a12beSStefan Roese 167a47a12beSStefan Roese /* 168a47a12beSStefan Roese * Enable L1 Caches early 169a47a12beSStefan Roese * 170a47a12beSStefan Roese */ 171a47a12beSStefan Roese 172a47a12beSStefan Roese#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) 173a47a12beSStefan Roese /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 174a47a12beSStefan Roese li r2,(32 + 0) 175a47a12beSStefan Roese mtspr L1CSR2,r2 176a47a12beSStefan Roese#endif 177a47a12beSStefan Roese 178a47a12beSStefan Roese /* Enable/invalidate the I-Cache */ 179a47a12beSStefan Roese lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 180a47a12beSStefan Roese ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 181a47a12beSStefan Roese mtspr SPRN_L1CSR1,r2 182a47a12beSStefan Roese1: 183a47a12beSStefan Roese mfspr r3,SPRN_L1CSR1 184a47a12beSStefan Roese and. r1,r3,r2 185a47a12beSStefan Roese bne 1b 186a47a12beSStefan Roese 187a47a12beSStefan Roese lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 188a47a12beSStefan Roese ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 189a47a12beSStefan Roese mtspr SPRN_L1CSR1,r3 190a47a12beSStefan Roese isync 191a47a12beSStefan Roese2: 192a47a12beSStefan Roese mfspr r3,SPRN_L1CSR1 193a47a12beSStefan Roese andi. r1,r3,L1CSR1_ICE@l 194a47a12beSStefan Roese beq 2b 195a47a12beSStefan Roese 196a47a12beSStefan Roese /* Enable/invalidate the D-Cache */ 197a47a12beSStefan Roese lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 198a47a12beSStefan Roese ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 199a47a12beSStefan Roese mtspr SPRN_L1CSR0,r2 200a47a12beSStefan Roese1: 201a47a12beSStefan Roese mfspr r3,SPRN_L1CSR0 202a47a12beSStefan Roese and. r1,r3,r2 203a47a12beSStefan Roese bne 1b 204a47a12beSStefan Roese 205a47a12beSStefan Roese lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 206a47a12beSStefan Roese ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 207a47a12beSStefan Roese mtspr SPRN_L1CSR0,r3 208a47a12beSStefan Roese isync 209a47a12beSStefan Roese2: 210a47a12beSStefan Roese mfspr r3,SPRN_L1CSR0 211a47a12beSStefan Roese andi. r1,r3,L1CSR0_DCE@l 212a47a12beSStefan Roese beq 2b 213a47a12beSStefan Roese 214d16a37b8SPrabhakar Kushwaha#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) 215689f00fcSPrabhakar Kushwaha/* 216689f00fcSPrabhakar Kushwaha * TLB entry for debuggging in AS1 217689f00fcSPrabhakar Kushwaha * Create temporary TLB entry in AS0 to handle debug exception 218689f00fcSPrabhakar Kushwaha * As on debug exception MSR is cleared i.e. Address space is changed 219689f00fcSPrabhakar Kushwaha * to 0. A TLB entry (in AS0) is required to handle debug exception generated 220689f00fcSPrabhakar Kushwaha * in AS1. 221689f00fcSPrabhakar Kushwaha */ 222689f00fcSPrabhakar Kushwaha 223689f00fcSPrabhakar Kushwaha lis r6,FSL_BOOKE_MAS0(1, 224689f00fcSPrabhakar Kushwaha CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h 225689f00fcSPrabhakar Kushwaha ori r6,r6,FSL_BOOKE_MAS0(1, 226689f00fcSPrabhakar Kushwaha CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l 227689f00fcSPrabhakar Kushwaha 228689f00fcSPrabhakar Kushwaha#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) 229689f00fcSPrabhakar Kushwaha/* 230689f00fcSPrabhakar Kushwaha * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 231689f00fcSPrabhakar Kushwaha * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. 232689f00fcSPrabhakar Kushwaha * and this window is outside of 4K boot window. 233689f00fcSPrabhakar Kushwaha */ 234689f00fcSPrabhakar Kushwaha lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h 235689f00fcSPrabhakar Kushwaha ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l 236689f00fcSPrabhakar Kushwaha 237689f00fcSPrabhakar Kushwaha lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, 238689f00fcSPrabhakar Kushwaha (MAS2_I|MAS2_G))@h 239689f00fcSPrabhakar Kushwaha ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, 240689f00fcSPrabhakar Kushwaha (MAS2_I|MAS2_G))@l 241689f00fcSPrabhakar Kushwaha 242689f00fcSPrabhakar Kushwaha /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 243689f00fcSPrabhakar Kushwaha lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 244689f00fcSPrabhakar Kushwaha ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 245689f00fcSPrabhakar Kushwaha#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 246689f00fcSPrabhakar Kushwaha lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h 247689f00fcSPrabhakar Kushwaha ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l 248689f00fcSPrabhakar Kushwaha 249689f00fcSPrabhakar Kushwaha lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h 250689f00fcSPrabhakar Kushwaha ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l 251689f00fcSPrabhakar Kushwaha 252689f00fcSPrabhakar Kushwaha lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 253689f00fcSPrabhakar Kushwaha (MAS3_SX|MAS3_SW|MAS3_SR))@h 254689f00fcSPrabhakar Kushwaha ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 255689f00fcSPrabhakar Kushwaha (MAS3_SX|MAS3_SW|MAS3_SR))@l 256689f00fcSPrabhakar Kushwaha#else 257689f00fcSPrabhakar Kushwaha/* 258689f00fcSPrabhakar Kushwaha * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 259689f00fcSPrabhakar Kushwaha * because "nexti" will resize TLB to 4K 260689f00fcSPrabhakar Kushwaha */ 261689f00fcSPrabhakar Kushwaha lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h 262689f00fcSPrabhakar Kushwaha ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l 263689f00fcSPrabhakar Kushwaha 264689f00fcSPrabhakar Kushwaha lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h 265689f00fcSPrabhakar Kushwaha ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, 266689f00fcSPrabhakar Kushwaha (MAS2_I))@l 267689f00fcSPrabhakar Kushwaha lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, 268689f00fcSPrabhakar Kushwaha (MAS3_SX|MAS3_SW|MAS3_SR))@h 269689f00fcSPrabhakar Kushwaha ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, 270689f00fcSPrabhakar Kushwaha (MAS3_SX|MAS3_SW|MAS3_SR))@l 271689f00fcSPrabhakar Kushwaha#endif 272689f00fcSPrabhakar Kushwaha mtspr MAS0,r6 273689f00fcSPrabhakar Kushwaha mtspr MAS1,r7 274689f00fcSPrabhakar Kushwaha mtspr MAS2,r8 275689f00fcSPrabhakar Kushwaha mtspr MAS3,r9 276689f00fcSPrabhakar Kushwaha tlbwe 277689f00fcSPrabhakar Kushwaha isync 278689f00fcSPrabhakar Kushwaha#endif 279689f00fcSPrabhakar Kushwaha 280119a55f9SPrabhakar Kushwaha/* 281119a55f9SPrabhakar Kushwaha * Ne need to setup interrupt vector for NAND SPL 282119a55f9SPrabhakar Kushwaha * because NAND SPL never compiles it. 283119a55f9SPrabhakar Kushwaha */ 284119a55f9SPrabhakar Kushwaha#if !defined(CONFIG_NAND_SPL) 285a47a12beSStefan Roese /* Setup interrupt vectors */ 2860635b09cSHaiying Wang lis r1,CONFIG_SYS_MONITOR_BASE@h 287a47a12beSStefan Roese mtspr IVPR,r1 288a47a12beSStefan Roese 289a4107f86SPrabhakar Kushwaha lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h 290a4107f86SPrabhakar Kushwaha ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l 291a4107f86SPrabhakar Kushwaha 292a4107f86SPrabhakar Kushwaha addi r4,r3,CriticalInput - _start + _START_OFFSET 293a4107f86SPrabhakar Kushwaha mtspr IVOR0,r4 /* 0: Critical input */ 294a4107f86SPrabhakar Kushwaha addi r4,r3,MachineCheck - _start + _START_OFFSET 295a4107f86SPrabhakar Kushwaha mtspr IVOR1,r4 /* 1: Machine check */ 296a4107f86SPrabhakar Kushwaha addi r4,r3,DataStorage - _start + _START_OFFSET 297a4107f86SPrabhakar Kushwaha mtspr IVOR2,r4 /* 2: Data storage */ 298a4107f86SPrabhakar Kushwaha addi r4,r3,InstStorage - _start + _START_OFFSET 299a4107f86SPrabhakar Kushwaha mtspr IVOR3,r4 /* 3: Instruction storage */ 300a4107f86SPrabhakar Kushwaha addi r4,r3,ExtInterrupt - _start + _START_OFFSET 301a4107f86SPrabhakar Kushwaha mtspr IVOR4,r4 /* 4: External interrupt */ 302a4107f86SPrabhakar Kushwaha addi r4,r3,Alignment - _start + _START_OFFSET 303a4107f86SPrabhakar Kushwaha mtspr IVOR5,r4 /* 5: Alignment */ 304a4107f86SPrabhakar Kushwaha addi r4,r3,ProgramCheck - _start + _START_OFFSET 305a4107f86SPrabhakar Kushwaha mtspr IVOR6,r4 /* 6: Program check */ 306a4107f86SPrabhakar Kushwaha addi r4,r3,FPUnavailable - _start + _START_OFFSET 307a4107f86SPrabhakar Kushwaha mtspr IVOR7,r4 /* 7: floating point unavailable */ 308a4107f86SPrabhakar Kushwaha addi r4,r3,SystemCall - _start + _START_OFFSET 309a4107f86SPrabhakar Kushwaha mtspr IVOR8,r4 /* 8: System call */ 310a47a12beSStefan Roese /* 9: Auxiliary processor unavailable(unsupported) */ 311a4107f86SPrabhakar Kushwaha addi r4,r3,Decrementer - _start + _START_OFFSET 312a4107f86SPrabhakar Kushwaha mtspr IVOR10,r4 /* 10: Decrementer */ 313a4107f86SPrabhakar Kushwaha addi r4,r3,IntervalTimer - _start + _START_OFFSET 314a4107f86SPrabhakar Kushwaha mtspr IVOR11,r4 /* 11: Interval timer */ 315a4107f86SPrabhakar Kushwaha addi r4,r3,WatchdogTimer - _start + _START_OFFSET 316a4107f86SPrabhakar Kushwaha mtspr IVOR12,r4 /* 12: Watchdog timer */ 317a4107f86SPrabhakar Kushwaha addi r4,r3,DataTLBError - _start + _START_OFFSET 318a4107f86SPrabhakar Kushwaha mtspr IVOR13,r4 /* 13: Data TLB error */ 319a4107f86SPrabhakar Kushwaha addi r4,r3,InstructionTLBError - _start + _START_OFFSET 320a4107f86SPrabhakar Kushwaha mtspr IVOR14,r4 /* 14: Instruction TLB error */ 321a4107f86SPrabhakar Kushwaha addi r4,r3,DebugBreakpoint - _start + _START_OFFSET 322a4107f86SPrabhakar Kushwaha mtspr IVOR15,r4 /* 15: Debug */ 323119a55f9SPrabhakar Kushwaha#endif 324a47a12beSStefan Roese 325a47a12beSStefan Roese /* Clear and set up some registers. */ 326a47a12beSStefan Roese li r0,0x0000 327a47a12beSStefan Roese lis r1,0xffff 328a47a12beSStefan Roese mtspr DEC,r0 /* prevent dec exceptions */ 329a47a12beSStefan Roese mttbl r0 /* prevent fit & wdt exceptions */ 330a47a12beSStefan Roese mttbu r0 331a47a12beSStefan Roese mtspr TSR,r1 /* clear all timer exception status */ 332a47a12beSStefan Roese mtspr TCR,r0 /* disable all */ 333a47a12beSStefan Roese mtspr ESR,r0 /* clear exception syndrome register */ 334a47a12beSStefan Roese mtspr MCSR,r0 /* machine check syndrome register */ 335a47a12beSStefan Roese mtxer r0 /* clear integer exception register */ 336a47a12beSStefan Roese 337a47a12beSStefan Roese#ifdef CONFIG_SYS_BOOK3E_HV 338a47a12beSStefan Roese mtspr MAS8,r0 /* make sure MAS8 is clear */ 339a47a12beSStefan Roese#endif 340a47a12beSStefan Roese 341a47a12beSStefan Roese /* Enable Time Base and Select Time Base Clock */ 342a47a12beSStefan Roese lis r0,HID0_EMCP@h /* Enable machine check */ 343a47a12beSStefan Roese#if defined(CONFIG_ENABLE_36BIT_PHYS) 344a47a12beSStefan Roese ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 345a47a12beSStefan Roese#endif 346a47a12beSStefan Roese#ifndef CONFIG_E500MC 347a47a12beSStefan Roese ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 348a47a12beSStefan Roese#endif 349a47a12beSStefan Roese mtspr HID0,r0 350a47a12beSStefan Roese 351a47a12beSStefan Roese#ifndef CONFIG_E500MC 352a47a12beSStefan Roese li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 353a47a12beSStefan Roese mfspr r3,PVR 354a47a12beSStefan Roese andi. r3,r3, 0xff 355a47a12beSStefan Roese cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 356a47a12beSStefan Roese blt 1f 357a47a12beSStefan Roese /* Set MBDD bit also */ 358a47a12beSStefan Roese ori r0, r0, HID1_MBDD@l 359a47a12beSStefan Roese1: 360a47a12beSStefan Roese mtspr HID1,r0 361a47a12beSStefan Roese#endif 362a47a12beSStefan Roese 36343f082bbSKumar Gala#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 36443f082bbSKumar Gala mfspr r3,977 36543f082bbSKumar Gala oris r3,r3,0x0100 36643f082bbSKumar Gala mtspr 977,r3 36743f082bbSKumar Gala#endif 36843f082bbSKumar Gala 369a47a12beSStefan Roese /* Enable Branch Prediction */ 370a47a12beSStefan Roese#if defined(CONFIG_BTB) 371a47a12beSStefan Roese lis r0,BUCSR_ENABLE@h 372a47a12beSStefan Roese ori r0,r0,BUCSR_ENABLE@l 373a47a12beSStefan Roese mtspr SPRN_BUCSR,r0 374a47a12beSStefan Roese#endif 375a47a12beSStefan Roese 376a47a12beSStefan Roese#if defined(CONFIG_SYS_INIT_DBCR) 377a47a12beSStefan Roese lis r1,0xffff 378a47a12beSStefan Roese ori r1,r1,0xffff 379a47a12beSStefan Roese mtspr DBSR,r1 /* Clear all status bits */ 380a47a12beSStefan Roese lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 381a47a12beSStefan Roese ori r0,r0,CONFIG_SYS_INIT_DBCR@l 382a47a12beSStefan Roese mtspr DBCR0,r0 383a47a12beSStefan Roese#endif 384a47a12beSStefan Roese 385a47a12beSStefan Roese#ifdef CONFIG_MPC8569 386a47a12beSStefan Roese#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 387a47a12beSStefan Roese#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 388a47a12beSStefan Roese 389a47a12beSStefan Roese /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 390a47a12beSStefan Roese * use address space which is more than 12bits, and it must be done in 391a47a12beSStefan Roese * the 4K boot page. So we set this bit here. 392a47a12beSStefan Roese */ 393a47a12beSStefan Roese 394a47a12beSStefan Roese /* create a temp mapping TLB0[0] for LBCR */ 395a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h 396a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l 397a47a12beSStefan Roese 398a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 399a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 400a47a12beSStefan Roese 401a47a12beSStefan Roese lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h 402a47a12beSStefan Roese ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l 403a47a12beSStefan Roese 404a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 405a47a12beSStefan Roese (MAS3_SX|MAS3_SW|MAS3_SR))@h 406a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 407a47a12beSStefan Roese (MAS3_SX|MAS3_SW|MAS3_SR))@l 408a47a12beSStefan Roese 409a47a12beSStefan Roese mtspr MAS0,r6 410a47a12beSStefan Roese mtspr MAS1,r7 411a47a12beSStefan Roese mtspr MAS2,r8 412a47a12beSStefan Roese mtspr MAS3,r9 413a47a12beSStefan Roese isync 414a47a12beSStefan Roese msync 415a47a12beSStefan Roese tlbwe 416a47a12beSStefan Roese 417a47a12beSStefan Roese /* Set LBCR register */ 418a47a12beSStefan Roese lis r4,CONFIG_SYS_LBCR_ADDR@h 419a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 420a47a12beSStefan Roese 421a47a12beSStefan Roese lis r5,CONFIG_SYS_LBC_LBCR@h 422a47a12beSStefan Roese ori r5,r5,CONFIG_SYS_LBC_LBCR@l 423a47a12beSStefan Roese stw r5,0(r4) 424a47a12beSStefan Roese isync 425a47a12beSStefan Roese 426a47a12beSStefan Roese /* invalidate this temp TLB */ 427a47a12beSStefan Roese lis r4,CONFIG_SYS_LBC_ADDR@h 428a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_LBC_ADDR@l 429a47a12beSStefan Roese tlbivax 0,r4 430a47a12beSStefan Roese isync 431a47a12beSStefan Roese 432a47a12beSStefan Roese#endif /* CONFIG_MPC8569 */ 433a47a12beSStefan Roese 4346ca88b09STimur Tabi/* 43572243c01STimur Tabi * Search for the TLB that covers the code we're executing, and shrink it 43672243c01STimur Tabi * so that it covers only this 4K page. That will ensure that any other 43772243c01STimur Tabi * TLB we create won't interfere with it. We assume that the TLB exists, 438*3ea21536SScott Wood * which is why we don't check the Valid bit of MAS1. We also assume 439*3ea21536SScott Wood * it is in TLB1. 44072243c01STimur Tabi * 44172243c01STimur Tabi * This is necessary, for example, when booting from the on-chip ROM, 44272243c01STimur Tabi * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. 44372243c01STimur Tabi */ 44472243c01STimur Tabi bl nexti /* Find our address */ 44572243c01STimur Tabinexti: mflr r1 /* R1 = our PC */ 44672243c01STimur Tabi li r2, 0 44772243c01STimur Tabi mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ 44872243c01STimur Tabi isync 44972243c01STimur Tabi msync 45072243c01STimur Tabi tlbsx 0, r1 /* This must succeed */ 45172243c01STimur Tabi 452*3ea21536SScott Wood mfspr r14, MAS0 /* Save ESEL for later */ 453*3ea21536SScott Wood rlwinm r14, r14, 16, 0xfff 454*3ea21536SScott Wood 45572243c01STimur Tabi /* Set the size of the TLB to 4KB */ 45672243c01STimur Tabi mfspr r3, MAS1 45772243c01STimur Tabi li r2, 0xF00 45872243c01STimur Tabi andc r3, r3, r2 /* Clear the TSIZE bits */ 45972243c01STimur Tabi ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l 460*3ea21536SScott Wood oris r3, r3, MAS1_IPROT@h 46172243c01STimur Tabi mtspr MAS1, r3 46272243c01STimur Tabi 46372243c01STimur Tabi /* 46472243c01STimur Tabi * Set the base address of the TLB to our PC. We assume that 46572243c01STimur Tabi * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. 46672243c01STimur Tabi */ 46772243c01STimur Tabi lis r3, MAS2_EPN@h 46872243c01STimur Tabi ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ 46972243c01STimur Tabi 47072243c01STimur Tabi and r1, r1, r3 /* Our PC, rounded down to the nearest page */ 47172243c01STimur Tabi 47272243c01STimur Tabi mfspr r2, MAS2 47372243c01STimur Tabi andc r2, r2, r3 47472243c01STimur Tabi or r2, r2, r1 47533eee330SScott Wood#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 47633eee330SScott Wood cmpwi r27,0 47733eee330SScott Wood beq 1f 47833eee330SScott Wood andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */ 47933eee330SScott Wood rlwinm r2, r2, 0, ~MAS2_I 48033eee330SScott Wood ori r2, r2, MAS2_G 48133eee330SScott Wood1: 48233eee330SScott Wood#endif 48372243c01STimur Tabi mtspr MAS2, r2 /* Set the EPN to our PC base address */ 48472243c01STimur Tabi 48572243c01STimur Tabi mfspr r2, MAS3 48672243c01STimur Tabi andc r2, r2, r3 48772243c01STimur Tabi or r2, r2, r1 48872243c01STimur Tabi mtspr MAS3, r2 /* Set the RPN to our PC base address */ 48972243c01STimur Tabi 49072243c01STimur Tabi isync 49172243c01STimur Tabi msync 49272243c01STimur Tabi tlbwe 49372243c01STimur Tabi 49472243c01STimur Tabi/* 495*3ea21536SScott Wood * Clear out any other TLB entries that may exist, to avoid conflicts. 496*3ea21536SScott Wood * Our TLB entry is in r14. 497*3ea21536SScott Wood */ 498*3ea21536SScott Wood li r0, TLBIVAX_ALL | TLBIVAX_TLB0 499*3ea21536SScott Wood tlbivax 0, r0 500*3ea21536SScott Wood tlbsync 501*3ea21536SScott Wood 502*3ea21536SScott Wood mfspr r4, SPRN_TLB1CFG 503*3ea21536SScott Wood rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK 504*3ea21536SScott Wood 505*3ea21536SScott Wood li r3, 0 506*3ea21536SScott Wood mtspr MAS1, r3 507*3ea21536SScott Wood1: cmpw r3, r14 508*3ea21536SScott Wood#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) 509*3ea21536SScott Wood cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB 510*3ea21536SScott Wood cror cr0*4+eq, cr0*4+eq, cr1*4+eq 511*3ea21536SScott Wood#endif 512*3ea21536SScott Wood rlwinm r5, r3, 16, MAS0_ESEL_MSK 513*3ea21536SScott Wood addi r3, r3, 1 514*3ea21536SScott Wood beq 2f /* skip the entry we're executing from */ 515*3ea21536SScott Wood 516*3ea21536SScott Wood oris r5, r5, MAS0_TLBSEL(1)@h 517*3ea21536SScott Wood mtspr MAS0, r5 518*3ea21536SScott Wood 519*3ea21536SScott Wood isync 520*3ea21536SScott Wood tlbwe 521*3ea21536SScott Wood isync 522*3ea21536SScott Wood msync 523*3ea21536SScott Wood 524*3ea21536SScott Wood2: cmpw r3, r4 525*3ea21536SScott Wood blt 1b 526*3ea21536SScott Wood 527*3ea21536SScott Wood/* 5286ca88b09STimur Tabi * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default 5296ca88b09STimur Tabi * location is not where we want it. This typically happens on a 36-bit 5306ca88b09STimur Tabi * system, where we want to move CCSR to near the top of 36-bit address space. 5316ca88b09STimur Tabi * 5326ca88b09STimur Tabi * To move CCSR, we create two temporary TLBs, one for the old location, and 5336ca88b09STimur Tabi * another for the new location. On CoreNet systems, we also need to create 5346ca88b09STimur Tabi * a special, temporary LAW. 5356ca88b09STimur Tabi * 5366ca88b09STimur Tabi * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for 5376ca88b09STimur Tabi * long-term TLBs, so we use TLB0 here. 5386ca88b09STimur Tabi */ 5396ca88b09STimur Tabi#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) 5406ca88b09STimur Tabi 5416ca88b09STimur Tabi#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) 5426ca88b09STimur Tabi#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." 5436ca88b09STimur Tabi#endif 5446ca88b09STimur Tabi 5456ca88b09STimur Tabicreate_ccsr_new_tlb: 5466ca88b09STimur Tabi /* 5476ca88b09STimur Tabi * Create a TLB for the new location of CCSR. Register R8 is reserved 5486ca88b09STimur Tabi * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). 5496ca88b09STimur Tabi */ 550*3ea21536SScott Wood lis r8, CONFIG_SYS_CCSRBAR@h 551*3ea21536SScott Wood ori r8, r8, CONFIG_SYS_CCSRBAR@l 552*3ea21536SScott Wood lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h 553*3ea21536SScott Wood ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l 5546ca88b09STimur Tabi lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 5556ca88b09STimur Tabi ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 5566ca88b09STimur Tabi lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 5576ca88b09STimur Tabi ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 5586ca88b09STimur Tabi lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 5596ca88b09STimur Tabi ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 5606ca88b09STimur Tabi lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h 5616ca88b09STimur Tabi ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l 562822ad60fSTimur Tabi#ifdef CONFIG_ENABLE_36BIT_PHYS 5636ca88b09STimur Tabi lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 5646ca88b09STimur Tabi ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 565822ad60fSTimur Tabi mtspr MAS7, r7 566822ad60fSTimur Tabi#endif 5676ca88b09STimur Tabi mtspr MAS0, r0 5686ca88b09STimur Tabi mtspr MAS1, r1 5696ca88b09STimur Tabi mtspr MAS2, r2 5706ca88b09STimur Tabi mtspr MAS3, r3 5716ca88b09STimur Tabi isync 5726ca88b09STimur Tabi msync 5736ca88b09STimur Tabi tlbwe 5746ca88b09STimur Tabi 5756ca88b09STimur Tabi /* 576c2efa0aaSTimur Tabi * Create a TLB for the current location of CCSR. Register R9 is reserved 5776ca88b09STimur Tabi * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). 5786ca88b09STimur Tabi */ 5796ca88b09STimur Tabicreate_ccsr_old_tlb: 5806ca88b09STimur Tabi lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 5816ca88b09STimur Tabi ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 5826ca88b09STimur Tabi lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 5836ca88b09STimur Tabi ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 5846ca88b09STimur Tabi lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h 5856ca88b09STimur Tabi ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l 586822ad60fSTimur Tabi#ifdef CONFIG_ENABLE_36BIT_PHYS 5876ca88b09STimur Tabi li r7, 0 /* The default CCSR address is always a 32-bit number */ 588822ad60fSTimur Tabi mtspr MAS7, r7 589822ad60fSTimur Tabi#endif 5906ca88b09STimur Tabi mtspr MAS0, r0 5916ca88b09STimur Tabi /* MAS1 is the same as above */ 5926ca88b09STimur Tabi mtspr MAS2, r2 5936ca88b09STimur Tabi mtspr MAS3, r3 5946ca88b09STimur Tabi isync 5956ca88b09STimur Tabi msync 5966ca88b09STimur Tabi tlbwe 5976ca88b09STimur Tabi 59819e43841STimur Tabi /* 59919e43841STimur Tabi * We have a TLB for what we think is the current (old) CCSR. Let's 60019e43841STimur Tabi * verify that, otherwise we won't be able to move it. 60119e43841STimur Tabi * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only 60219e43841STimur Tabi * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. 60319e43841STimur Tabi */ 60419e43841STimur Tabiverify_old_ccsr: 60519e43841STimur Tabi lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h 60619e43841STimur Tabi ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l 60719e43841STimur Tabi#ifdef CONFIG_FSL_CORENET 60819e43841STimur Tabi lwz r1, 4(r9) /* CCSRBARL */ 60919e43841STimur Tabi#else 61019e43841STimur Tabi lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ 61119e43841STimur Tabi slwi r1, r1, 12 61219e43841STimur Tabi#endif 61319e43841STimur Tabi 61419e43841STimur Tabi cmpl 0, r0, r1 61519e43841STimur Tabi 61619e43841STimur Tabi /* 61719e43841STimur Tabi * If the value we read from CCSRBARL is not what we expect, then 61819e43841STimur Tabi * enter an infinite loop. This will at least allow a debugger to 61919e43841STimur Tabi * halt execution and examine TLBs, etc. There's no point in going 62019e43841STimur Tabi * on. 62119e43841STimur Tabi */ 62219e43841STimur Tabiinfinite_debug_loop: 62319e43841STimur Tabi bne infinite_debug_loop 62419e43841STimur Tabi 6256ca88b09STimur Tabi#ifdef CONFIG_FSL_CORENET 6266ca88b09STimur Tabi 6276ca88b09STimur Tabi#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 6286ca88b09STimur Tabi#define LAW_EN 0x80000000 6296ca88b09STimur Tabi#define LAW_SIZE_4K 0xb 6306ca88b09STimur Tabi#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) 6316ca88b09STimur Tabi#define CCSRAR_C 0x80000000 /* Commit */ 6326ca88b09STimur Tabi 6336ca88b09STimur Tabicreate_temp_law: 6346ca88b09STimur Tabi /* 6356ca88b09STimur Tabi * On CoreNet systems, we create the temporary LAW using a special LAW 6366ca88b09STimur Tabi * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. 6376ca88b09STimur Tabi */ 6386ca88b09STimur Tabi lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 6396ca88b09STimur Tabi ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 6406ca88b09STimur Tabi lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 6416ca88b09STimur Tabi ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 6426ca88b09STimur Tabi lis r2, CCSRBAR_LAWAR@h 6436ca88b09STimur Tabi ori r2, r2, CCSRBAR_LAWAR@l 6446ca88b09STimur Tabi 6456ca88b09STimur Tabi stw r0, 0xc00(r9) /* LAWBARH0 */ 6466ca88b09STimur Tabi stw r1, 0xc04(r9) /* LAWBARL0 */ 6476ca88b09STimur Tabi sync 6486ca88b09STimur Tabi stw r2, 0xc08(r9) /* LAWAR0 */ 6496ca88b09STimur Tabi 6506ca88b09STimur Tabi /* 6516ca88b09STimur Tabi * Read back from LAWAR to ensure the update is complete. e500mc 6526ca88b09STimur Tabi * cores also require an isync. 6536ca88b09STimur Tabi */ 6546ca88b09STimur Tabi lwz r0, 0xc08(r9) /* LAWAR0 */ 6556ca88b09STimur Tabi isync 6566ca88b09STimur Tabi 6576ca88b09STimur Tabi /* 6586ca88b09STimur Tabi * Read the current CCSRBARH and CCSRBARL using load word instructions. 6596ca88b09STimur Tabi * Follow this with an isync instruction. This forces any outstanding 6606ca88b09STimur Tabi * accesses to configuration space to completion. 6616ca88b09STimur Tabi */ 6626ca88b09STimur Tabiread_old_ccsrbar: 6636ca88b09STimur Tabi lwz r0, 0(r9) /* CCSRBARH */ 664c2efa0aaSTimur Tabi lwz r0, 4(r9) /* CCSRBARL */ 6656ca88b09STimur Tabi isync 6666ca88b09STimur Tabi 6676ca88b09STimur Tabi /* 6686ca88b09STimur Tabi * Write the new values for CCSRBARH and CCSRBARL to their old 6696ca88b09STimur Tabi * locations. The CCSRBARH has a shadow register. When the CCSRBARH 6706ca88b09STimur Tabi * has a new value written it loads a CCSRBARH shadow register. When 6716ca88b09STimur Tabi * the CCSRBARL is written, the CCSRBARH shadow register contents 6726ca88b09STimur Tabi * along with the CCSRBARL value are loaded into the CCSRBARH and 6736ca88b09STimur Tabi * CCSRBARL registers, respectively. Follow this with a sync 6746ca88b09STimur Tabi * instruction. 6756ca88b09STimur Tabi */ 6766ca88b09STimur Tabiwrite_new_ccsrbar: 6776ca88b09STimur Tabi lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 6786ca88b09STimur Tabi ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 6796ca88b09STimur Tabi lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 6806ca88b09STimur Tabi ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 6816ca88b09STimur Tabi lis r2, CCSRAR_C@h 6826ca88b09STimur Tabi ori r2, r2, CCSRAR_C@l 6836ca88b09STimur Tabi 6846ca88b09STimur Tabi stw r0, 0(r9) /* Write to CCSRBARH */ 6856ca88b09STimur Tabi sync /* Make sure we write to CCSRBARH first */ 6866ca88b09STimur Tabi stw r1, 4(r9) /* Write to CCSRBARL */ 6876ca88b09STimur Tabi sync 6886ca88b09STimur Tabi 6896ca88b09STimur Tabi /* 6906ca88b09STimur Tabi * Write a 1 to the commit bit (C) of CCSRAR at the old location. 6916ca88b09STimur Tabi * Follow this with a sync instruction. 6926ca88b09STimur Tabi */ 6936ca88b09STimur Tabi stw r2, 8(r9) 6946ca88b09STimur Tabi sync 6956ca88b09STimur Tabi 6966ca88b09STimur Tabi /* Delete the temporary LAW */ 6976ca88b09STimur Tabidelete_temp_law: 6986ca88b09STimur Tabi li r1, 0 6996ca88b09STimur Tabi stw r1, 0xc08(r8) 7006ca88b09STimur Tabi sync 7016ca88b09STimur Tabi stw r1, 0xc00(r8) 7026ca88b09STimur Tabi stw r1, 0xc04(r8) 7036ca88b09STimur Tabi sync 7046ca88b09STimur Tabi 7056ca88b09STimur Tabi#else /* #ifdef CONFIG_FSL_CORENET */ 7066ca88b09STimur Tabi 7076ca88b09STimur Tabiwrite_new_ccsrbar: 7086ca88b09STimur Tabi /* 7096ca88b09STimur Tabi * Read the current value of CCSRBAR using a load word instruction 7106ca88b09STimur Tabi * followed by an isync. This forces all accesses to configuration 7116ca88b09STimur Tabi * space to complete. 7126ca88b09STimur Tabi */ 7136ca88b09STimur Tabi sync 7146ca88b09STimur Tabi lwz r0, 0(r9) 7156ca88b09STimur Tabi isync 7166ca88b09STimur Tabi 7176ca88b09STimur Tabi/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ 7186ca88b09STimur Tabi#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ 7196ca88b09STimur Tabi (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) 7206ca88b09STimur Tabi 7216ca88b09STimur Tabi /* Write the new value to CCSRBAR. */ 7226ca88b09STimur Tabi lis r0, CCSRBAR_PHYS_RS12@h 7236ca88b09STimur Tabi ori r0, r0, CCSRBAR_PHYS_RS12@l 7246ca88b09STimur Tabi stw r0, 0(r9) 7256ca88b09STimur Tabi sync 7266ca88b09STimur Tabi 7276ca88b09STimur Tabi /* 7286ca88b09STimur Tabi * The manual says to perform a load of an address that does not 7296ca88b09STimur Tabi * access configuration space or the on-chip SRAM using an existing TLB, 7306ca88b09STimur Tabi * but that doesn't appear to be necessary. We will do the isync, 7316ca88b09STimur Tabi * though. 7326ca88b09STimur Tabi */ 7336ca88b09STimur Tabi isync 7346ca88b09STimur Tabi 7356ca88b09STimur Tabi /* 7366ca88b09STimur Tabi * Read the contents of CCSRBAR from its new location, followed by 7376ca88b09STimur Tabi * another isync. 7386ca88b09STimur Tabi */ 7396ca88b09STimur Tabi lwz r0, 0(r8) 7406ca88b09STimur Tabi isync 7416ca88b09STimur Tabi 7426ca88b09STimur Tabi#endif /* #ifdef CONFIG_FSL_CORENET */ 7436ca88b09STimur Tabi 7446ca88b09STimur Tabi /* Delete the temporary TLBs */ 7456ca88b09STimur Tabidelete_temp_tlbs: 7466ca88b09STimur Tabi lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 7476ca88b09STimur Tabi ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 7486ca88b09STimur Tabi li r1, 0 7496ca88b09STimur Tabi lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 7506ca88b09STimur Tabi ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 7516ca88b09STimur Tabi mtspr MAS0, r0 7526ca88b09STimur Tabi mtspr MAS1, r1 7536ca88b09STimur Tabi mtspr MAS2, r2 7546ca88b09STimur Tabi isync 7556ca88b09STimur Tabi msync 7566ca88b09STimur Tabi tlbwe 7576ca88b09STimur Tabi 7586ca88b09STimur Tabi lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 7596ca88b09STimur Tabi ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 7606ca88b09STimur Tabi lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 7616ca88b09STimur Tabi ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 7626ca88b09STimur Tabi mtspr MAS0, r0 7636ca88b09STimur Tabi mtspr MAS2, r2 7646ca88b09STimur Tabi isync 7656ca88b09STimur Tabi msync 7666ca88b09STimur Tabi tlbwe 7676ca88b09STimur Tabi#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ 7686ca88b09STimur Tabi 76933eee330SScott Wood#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 77033eee330SScott Wood#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 77133eee330SScott Wood#define LAW_SIZE_1M 0x13 77233eee330SScott Wood#define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M) 77333eee330SScott Wood 77433eee330SScott Wood cmpwi r27,0 77533eee330SScott Wood beq 9f 77633eee330SScott Wood 77733eee330SScott Wood /* 77833eee330SScott Wood * Create a TLB entry for CCSR 77933eee330SScott Wood * 78033eee330SScott Wood * We're executing out of TLB1 entry in r14, and that's the only 78133eee330SScott Wood * TLB entry that exists. To allocate some TLB entries for our 78233eee330SScott Wood * own use, flip a bit high enough that we won't flip it again 78333eee330SScott Wood * via incrementing. 78433eee330SScott Wood */ 78533eee330SScott Wood 78633eee330SScott Wood xori r8, r14, 32 78733eee330SScott Wood lis r0, MAS0_TLBSEL(1)@h 78833eee330SScott Wood rlwimi r0, r8, 16, MAS0_ESEL_MSK 78933eee330SScott Wood lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h 79033eee330SScott Wood ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l 79133eee330SScott Wood lis r7, CONFIG_SYS_CCSRBAR@h 79233eee330SScott Wood ori r7, r7, CONFIG_SYS_CCSRBAR@l 79333eee330SScott Wood ori r2, r7, MAS2_I|MAS2_G 79433eee330SScott Wood lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h 79533eee330SScott Wood ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l 79633eee330SScott Wood lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 79733eee330SScott Wood ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 79833eee330SScott Wood mtspr MAS0, r0 79933eee330SScott Wood mtspr MAS1, r1 80033eee330SScott Wood mtspr MAS2, r2 80133eee330SScott Wood mtspr MAS3, r3 80233eee330SScott Wood mtspr MAS7, r4 80333eee330SScott Wood isync 80433eee330SScott Wood tlbwe 80533eee330SScott Wood isync 80633eee330SScott Wood msync 80733eee330SScott Wood 80833eee330SScott Wood /* Map DCSR temporarily to physical address zero */ 80933eee330SScott Wood li r0, 0 81033eee330SScott Wood lis r3, DCSRBAR_LAWAR@h 81133eee330SScott Wood ori r3, r3, DCSRBAR_LAWAR@l 81233eee330SScott Wood 81333eee330SScott Wood stw r0, 0xc00(r7) /* LAWBARH0 */ 81433eee330SScott Wood stw r0, 0xc04(r7) /* LAWBARL0 */ 81533eee330SScott Wood sync 81633eee330SScott Wood stw r3, 0xc08(r7) /* LAWAR0 */ 81733eee330SScott Wood 81833eee330SScott Wood /* Read back from LAWAR to ensure the update is complete. */ 81933eee330SScott Wood lwz r3, 0xc08(r7) /* LAWAR0 */ 82033eee330SScott Wood isync 82133eee330SScott Wood 82233eee330SScott Wood /* Create a TLB entry for DCSR at zero */ 82333eee330SScott Wood 82433eee330SScott Wood addi r9, r8, 1 82533eee330SScott Wood lis r0, MAS0_TLBSEL(1)@h 82633eee330SScott Wood rlwimi r0, r9, 16, MAS0_ESEL_MSK 82733eee330SScott Wood lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h 82833eee330SScott Wood ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l 82933eee330SScott Wood li r6, 0 /* DCSR effective address */ 83033eee330SScott Wood ori r2, r6, MAS2_I|MAS2_G 83133eee330SScott Wood li r3, MAS3_SW|MAS3_SR 83233eee330SScott Wood li r4, 0 83333eee330SScott Wood mtspr MAS0, r0 83433eee330SScott Wood mtspr MAS1, r1 83533eee330SScott Wood mtspr MAS2, r2 83633eee330SScott Wood mtspr MAS3, r3 83733eee330SScott Wood mtspr MAS7, r4 83833eee330SScott Wood isync 83933eee330SScott Wood tlbwe 84033eee330SScott Wood isync 84133eee330SScott Wood msync 84233eee330SScott Wood 84333eee330SScott Wood /* enable the timebase */ 84433eee330SScott Wood#define CTBENR 0xe2084 84533eee330SScott Wood li r3, 1 84633eee330SScott Wood addis r4, r7, CTBENR@ha 84733eee330SScott Wood stw r3, CTBENR@l(r4) 84833eee330SScott Wood lwz r3, CTBENR@l(r4) 84933eee330SScott Wood twi 0,r3,0 85033eee330SScott Wood isync 85133eee330SScott Wood 85233eee330SScott Wood .macro erratum_set_ccsr offset value 85333eee330SScott Wood addis r3, r7, \offset@ha 85433eee330SScott Wood lis r4, \value@h 85533eee330SScott Wood addi r3, r3, \offset@l 85633eee330SScott Wood ori r4, r4, \value@l 85733eee330SScott Wood bl erratum_set_value 85833eee330SScott Wood .endm 85933eee330SScott Wood 86033eee330SScott Wood .macro erratum_set_dcsr offset value 86133eee330SScott Wood addis r3, r6, \offset@ha 86233eee330SScott Wood lis r4, \value@h 86333eee330SScott Wood addi r3, r3, \offset@l 86433eee330SScott Wood ori r4, r4, \value@l 86533eee330SScott Wood bl erratum_set_value 86633eee330SScott Wood .endm 86733eee330SScott Wood 86833eee330SScott Wood erratum_set_dcsr 0xb0e08 0xe0201800 86933eee330SScott Wood erratum_set_dcsr 0xb0e18 0xe0201800 87033eee330SScott Wood erratum_set_dcsr 0xb0e38 0xe0400000 87133eee330SScott Wood erratum_set_dcsr 0xb0008 0x00900000 87233eee330SScott Wood erratum_set_dcsr 0xb0e40 0xe00a0000 87333eee330SScott Wood erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 87433eee330SScott Wood erratum_set_ccsr 0x10f00 0x415e5000 87533eee330SScott Wood erratum_set_ccsr 0x11f00 0x415e5000 87633eee330SScott Wood 87733eee330SScott Wood /* Make temp mapping uncacheable again, if it was initially */ 87833eee330SScott Wood bl 2f 87933eee330SScott Wood2: mflr r3 88033eee330SScott Wood tlbsx 0, r3 88133eee330SScott Wood mfspr r4, MAS2 88233eee330SScott Wood rlwimi r4, r15, 0, MAS2_I 88333eee330SScott Wood rlwimi r4, r15, 0, MAS2_G 88433eee330SScott Wood mtspr MAS2, r4 88533eee330SScott Wood isync 88633eee330SScott Wood tlbwe 88733eee330SScott Wood isync 88833eee330SScott Wood msync 88933eee330SScott Wood 89033eee330SScott Wood /* Clear the cache */ 89133eee330SScott Wood lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 89233eee330SScott Wood ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 89333eee330SScott Wood sync 89433eee330SScott Wood isync 89533eee330SScott Wood mtspr SPRN_L1CSR1,r3 89633eee330SScott Wood isync 89733eee330SScott Wood2: sync 89833eee330SScott Wood mfspr r4,SPRN_L1CSR1 89933eee330SScott Wood and. r4,r4,r3 90033eee330SScott Wood bne 2b 90133eee330SScott Wood 90233eee330SScott Wood lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 90333eee330SScott Wood ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 90433eee330SScott Wood sync 90533eee330SScott Wood isync 90633eee330SScott Wood mtspr SPRN_L1CSR1,r3 90733eee330SScott Wood isync 90833eee330SScott Wood2: sync 90933eee330SScott Wood mfspr r4,SPRN_L1CSR1 91033eee330SScott Wood and. r4,r4,r3 91133eee330SScott Wood beq 2b 91233eee330SScott Wood 91333eee330SScott Wood /* Remove temporary mappings */ 91433eee330SScott Wood lis r0, MAS0_TLBSEL(1)@h 91533eee330SScott Wood rlwimi r0, r9, 16, MAS0_ESEL_MSK 91633eee330SScott Wood li r3, 0 91733eee330SScott Wood mtspr MAS0, r0 91833eee330SScott Wood mtspr MAS1, r3 91933eee330SScott Wood isync 92033eee330SScott Wood tlbwe 92133eee330SScott Wood isync 92233eee330SScott Wood msync 92333eee330SScott Wood 92433eee330SScott Wood li r3, 0 92533eee330SScott Wood stw r3, 0xc08(r7) /* LAWAR0 */ 92633eee330SScott Wood lwz r3, 0xc08(r7) 92733eee330SScott Wood isync 92833eee330SScott Wood 92933eee330SScott Wood lis r0, MAS0_TLBSEL(1)@h 93033eee330SScott Wood rlwimi r0, r8, 16, MAS0_ESEL_MSK 93133eee330SScott Wood li r3, 0 93233eee330SScott Wood mtspr MAS0, r0 93333eee330SScott Wood mtspr MAS1, r3 93433eee330SScott Wood isync 93533eee330SScott Wood tlbwe 93633eee330SScott Wood isync 93733eee330SScott Wood msync 93833eee330SScott Wood 93933eee330SScott Wood b 9f 94033eee330SScott Wood 94133eee330SScott Wood /* r3 = addr, r4 = value, clobbers r5, r11, r12 */ 94233eee330SScott Wooderratum_set_value: 94333eee330SScott Wood /* Lock two cache lines into I-Cache */ 94433eee330SScott Wood sync 94533eee330SScott Wood mfspr r11, SPRN_L1CSR1 94633eee330SScott Wood rlwinm r11, r11, 0, ~L1CSR1_ICUL 94733eee330SScott Wood sync 94833eee330SScott Wood isync 94933eee330SScott Wood mtspr SPRN_L1CSR1, r11 95033eee330SScott Wood isync 95133eee330SScott Wood 95233eee330SScott Wood mflr r12 95333eee330SScott Wood bl 5f 95433eee330SScott Wood5: mflr r5 95533eee330SScott Wood addi r5, r5, 2f - 5b 95633eee330SScott Wood icbtls 0, 0, r5 95733eee330SScott Wood addi r5, r5, 64 95833eee330SScott Wood 95933eee330SScott Wood sync 96033eee330SScott Wood mfspr r11, SPRN_L1CSR1 96133eee330SScott Wood3: andi. r11, r11, L1CSR1_ICUL 96233eee330SScott Wood bne 3b 96333eee330SScott Wood 96433eee330SScott Wood icbtls 0, 0, r5 96533eee330SScott Wood addi r5, r5, 64 96633eee330SScott Wood 96733eee330SScott Wood sync 96833eee330SScott Wood mfspr r11, SPRN_L1CSR1 96933eee330SScott Wood3: andi. r11, r11, L1CSR1_ICUL 97033eee330SScott Wood bne 3b 97133eee330SScott Wood 97233eee330SScott Wood b 2f 97333eee330SScott Wood .align 6 97433eee330SScott Wood /* Inside a locked cacheline, wait a while, write, then wait a while */ 97533eee330SScott Wood2: sync 97633eee330SScott Wood 97733eee330SScott Wood mfspr r5, SPRN_TBRL 97833eee330SScott Wood addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ 97933eee330SScott Wood4: mfspr r5, SPRN_TBRL 98033eee330SScott Wood subf. r5, r5, r11 98133eee330SScott Wood bgt 4b 98233eee330SScott Wood 98333eee330SScott Wood stw r4, 0(r3) 98433eee330SScott Wood 98533eee330SScott Wood mfspr r5, SPRN_TBRL 98633eee330SScott Wood addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ 98733eee330SScott Wood4: mfspr r5, SPRN_TBRL 98833eee330SScott Wood subf. r5, r5, r11 98933eee330SScott Wood bgt 4b 99033eee330SScott Wood 99133eee330SScott Wood sync 99233eee330SScott Wood 99333eee330SScott Wood /* 99433eee330SScott Wood * Fill out the rest of this cache line and the next with nops, 99533eee330SScott Wood * to ensure that nothing outside the locked area will be 99633eee330SScott Wood * fetched due to a branch. 99733eee330SScott Wood */ 99833eee330SScott Wood .rept 19 99933eee330SScott Wood nop 100033eee330SScott Wood .endr 100133eee330SScott Wood 100233eee330SScott Wood sync 100333eee330SScott Wood mfspr r11, SPRN_L1CSR1 100433eee330SScott Wood rlwinm r11, r11, 0, ~L1CSR1_ICUL 100533eee330SScott Wood sync 100633eee330SScott Wood isync 100733eee330SScott Wood mtspr SPRN_L1CSR1, r11 100833eee330SScott Wood isync 100933eee330SScott Wood 101033eee330SScott Wood mtlr r12 101133eee330SScott Wood blr 101233eee330SScott Wood 101333eee330SScott Wood9: 101433eee330SScott Wood#endif 101533eee330SScott Wood 10166ca88b09STimur Tabicreate_init_ram_area: 1017a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 1018a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 1019a47a12beSStefan Roese 10207065b7d4SRuchika Gupta#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) 1021a47a12beSStefan Roese /* create a temp mapping in AS=1 to the 4M boot window */ 1022a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h 1023a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l 1024a47a12beSStefan Roese 10250635b09cSHaiying Wang lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h 10260635b09cSHaiying Wang ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l 1027a47a12beSStefan Roese 1028a47a12beSStefan Roese /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 1029a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 1030a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 10317065b7d4SRuchika Gupta#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 10327065b7d4SRuchika Gupta /* create a temp mapping in AS = 1 for Flash mapping 10337065b7d4SRuchika Gupta * created by PBL for ISBC code 10347065b7d4SRuchika Gupta */ 10357065b7d4SRuchika Gupta lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 10367065b7d4SRuchika Gupta ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 10377065b7d4SRuchika Gupta 10387065b7d4SRuchika Gupta lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 10397065b7d4SRuchika Gupta ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 10407065b7d4SRuchika Gupta 10417065b7d4SRuchika Gupta lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 10427065b7d4SRuchika Gupta (MAS3_SX|MAS3_SW|MAS3_SR))@h 10437065b7d4SRuchika Gupta ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 10447065b7d4SRuchika Gupta (MAS3_SX|MAS3_SW|MAS3_SR))@l 1045a47a12beSStefan Roese#else 1046a47a12beSStefan Roese /* 10470635b09cSHaiying Wang * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main 10480635b09cSHaiying Wang * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. 1049a47a12beSStefan Roese */ 1050a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 1051a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 1052a47a12beSStefan Roese 10530635b09cSHaiying Wang lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 10540635b09cSHaiying Wang ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 1055a47a12beSStefan Roese 10560635b09cSHaiying Wang lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 10570635b09cSHaiying Wang ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 1058a47a12beSStefan Roese#endif 1059a47a12beSStefan Roese 1060a47a12beSStefan Roese mtspr MAS0,r6 1061a47a12beSStefan Roese mtspr MAS1,r7 1062a47a12beSStefan Roese mtspr MAS2,r8 1063a47a12beSStefan Roese mtspr MAS3,r9 1064a47a12beSStefan Roese isync 1065a47a12beSStefan Roese msync 1066a47a12beSStefan Roese tlbwe 1067a47a12beSStefan Roese 1068a47a12beSStefan Roese /* create a temp mapping in AS=1 to the stack */ 1069a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h 1070a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l 1071a47a12beSStefan Roese 1072a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h 1073a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l 1074a47a12beSStefan Roese 1075a47a12beSStefan Roese lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h 1076a47a12beSStefan Roese ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l 1077a47a12beSStefan Roese 1078a3f18529Syork#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ 1079a3f18529Syork defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) 1080a3f18529Syork lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 1081a3f18529Syork (MAS3_SX|MAS3_SW|MAS3_SR))@h 1082a3f18529Syork ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 1083a3f18529Syork (MAS3_SX|MAS3_SW|MAS3_SR))@l 1084a3f18529Syork li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 1085a3f18529Syork mtspr MAS7,r10 1086a3f18529Syork#else 1087a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 1088a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 1089a3f18529Syork#endif 1090a47a12beSStefan Roese 1091a47a12beSStefan Roese mtspr MAS0,r6 1092a47a12beSStefan Roese mtspr MAS1,r7 1093a47a12beSStefan Roese mtspr MAS2,r8 1094a47a12beSStefan Roese mtspr MAS3,r9 1095a47a12beSStefan Roese isync 1096a47a12beSStefan Roese msync 1097a47a12beSStefan Roese tlbwe 1098a47a12beSStefan Roese 10995344f7a2SPrabhakar Kushwaha lis r6,MSR_IS|MSR_DS|MSR_DE@h 11005344f7a2SPrabhakar Kushwaha ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l 1101a47a12beSStefan Roese lis r7,switch_as@h 1102a47a12beSStefan Roese ori r7,r7,switch_as@l 1103a47a12beSStefan Roese 1104a47a12beSStefan Roese mtspr SPRN_SRR0,r7 1105a47a12beSStefan Roese mtspr SPRN_SRR1,r6 1106a47a12beSStefan Roese rfi 1107a47a12beSStefan Roese 1108a47a12beSStefan Roeseswitch_as: 1109a47a12beSStefan Roese/* L1 DCache is used for initial RAM */ 1110a47a12beSStefan Roese 1111a47a12beSStefan Roese /* Allocate Initial RAM in data cache. 1112a47a12beSStefan Roese */ 1113a47a12beSStefan Roese lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1114a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1115a47a12beSStefan Roese mfspr r2, L1CFG0 1116a47a12beSStefan Roese andi. r2, r2, 0x1ff 1117a47a12beSStefan Roese /* cache size * 1024 / (2 * L1 line size) */ 1118a47a12beSStefan Roese slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 1119a47a12beSStefan Roese mtctr r2 1120a47a12beSStefan Roese li r0,0 1121a47a12beSStefan Roese1: 1122a47a12beSStefan Roese dcbz r0,r3 1123a47a12beSStefan Roese dcbtls 0,r0,r3 1124a47a12beSStefan Roese addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1125a47a12beSStefan Roese bdnz 1b 1126a47a12beSStefan Roese 1127a47a12beSStefan Roese /* Jump out the last 4K page and continue to 'normal' start */ 1128a47a12beSStefan Roese#ifdef CONFIG_SYS_RAMBOOT 1129a47a12beSStefan Roese b _start_cont 1130a47a12beSStefan Roese#else 1131a47a12beSStefan Roese /* Calculate absolute address in FLASH and jump there */ 1132a47a12beSStefan Roese /*--------------------------------------------------------------*/ 1133a47a12beSStefan Roese lis r3,CONFIG_SYS_MONITOR_BASE@h 1134a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 1135a47a12beSStefan Roese addi r3,r3,_start_cont - _start + _START_OFFSET 1136a47a12beSStefan Roese mtlr r3 1137a47a12beSStefan Roese blr 1138a47a12beSStefan Roese#endif 1139a47a12beSStefan Roese 1140a47a12beSStefan Roese .text 1141a47a12beSStefan Roese .globl _start 1142a47a12beSStefan Roese_start: 1143a47a12beSStefan Roese .long 0x27051956 /* U-BOOT Magic Number */ 1144a47a12beSStefan Roese .globl version_string 1145a47a12beSStefan Roeseversion_string: 114609c2e90cSAndreas Bießmann .ascii U_BOOT_VERSION_STRING, "\0" 1147a47a12beSStefan Roese 1148a47a12beSStefan Roese .align 4 1149a47a12beSStefan Roese .globl _start_cont 1150a47a12beSStefan Roese_start_cont: 1151a47a12beSStefan Roese /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 115289f42899SJoakim Tjernlund lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h 115389f42899SJoakim Tjernlund ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ 1154a47a12beSStefan Roese li r0,0 115589f42899SJoakim Tjernlund stw r0,0(r3) /* Terminate Back Chain */ 115689f42899SJoakim Tjernlund stw r0,+4(r3) /* NULL return address. */ 115789f42899SJoakim Tjernlund mr r1,r3 /* Transfer to SP(r1) */ 1158a47a12beSStefan Roese 1159a47a12beSStefan Roese GET_GOT 1160a47a12beSStefan Roese bl cpu_init_early_f 1161a47a12beSStefan Roese 1162a47a12beSStefan Roese /* switch back to AS = 0 */ 1163a47a12beSStefan Roese lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 1164a47a12beSStefan Roese ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 1165a47a12beSStefan Roese mtmsr r3 1166a47a12beSStefan Roese isync 1167a47a12beSStefan Roese 1168a47a12beSStefan Roese bl cpu_init_f 1169a47a12beSStefan Roese bl board_init_f 1170a47a12beSStefan Roese isync 1171a47a12beSStefan Roese 117252ebd9c1SPeter Tyser /* NOTREACHED - board_init_f() does not return */ 117352ebd9c1SPeter Tyser 1174a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 1175a47a12beSStefan Roese . = EXC_OFF_SYS_RESET 1176a47a12beSStefan Roese .globl _start_of_vectors 1177a47a12beSStefan Roese_start_of_vectors: 1178a47a12beSStefan Roese 1179a47a12beSStefan Roese/* Critical input. */ 1180a47a12beSStefan Roese CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 1181a47a12beSStefan Roese 1182a47a12beSStefan Roese/* Machine check */ 1183a47a12beSStefan Roese MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 1184a47a12beSStefan Roese 1185a47a12beSStefan Roese/* Data Storage exception. */ 1186a47a12beSStefan Roese STD_EXCEPTION(0x0300, DataStorage, UnknownException) 1187a47a12beSStefan Roese 1188a47a12beSStefan Roese/* Instruction Storage exception. */ 1189a47a12beSStefan Roese STD_EXCEPTION(0x0400, InstStorage, UnknownException) 1190a47a12beSStefan Roese 1191a47a12beSStefan Roese/* External Interrupt exception. */ 1192a47a12beSStefan Roese STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 1193a47a12beSStefan Roese 1194a47a12beSStefan Roese/* Alignment exception. */ 1195a47a12beSStefan Roese . = 0x0600 1196a47a12beSStefan RoeseAlignment: 1197a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 1198a47a12beSStefan Roese mfspr r4,DAR 1199a47a12beSStefan Roese stw r4,_DAR(r21) 1200a47a12beSStefan Roese mfspr r5,DSISR 1201a47a12beSStefan Roese stw r5,_DSISR(r21) 1202a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 1203a47a12beSStefan Roese EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 1204a47a12beSStefan Roese 1205a47a12beSStefan Roese/* Program check exception */ 1206a47a12beSStefan Roese . = 0x0700 1207a47a12beSStefan RoeseProgramCheck: 1208a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 1209a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 1210a47a12beSStefan Roese EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 1211a47a12beSStefan Roese MSR_KERNEL, COPY_EE) 1212a47a12beSStefan Roese 1213a47a12beSStefan Roese /* No FPU on MPC85xx. This exception is not supposed to happen. 1214a47a12beSStefan Roese */ 1215a47a12beSStefan Roese STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 1216a47a12beSStefan Roese 1217a47a12beSStefan Roese . = 0x0900 1218a47a12beSStefan Roese/* 1219a47a12beSStefan Roese * r0 - SYSCALL number 1220a47a12beSStefan Roese * r3-... arguments 1221a47a12beSStefan Roese */ 1222a47a12beSStefan RoeseSystemCall: 1223a47a12beSStefan Roese addis r11,r0,0 /* get functions table addr */ 1224a47a12beSStefan Roese ori r11,r11,0 /* Note: this code is patched in trap_init */ 1225a47a12beSStefan Roese addis r12,r0,0 /* get number of functions */ 1226a47a12beSStefan Roese ori r12,r12,0 1227a47a12beSStefan Roese 1228a47a12beSStefan Roese cmplw 0,r0,r12 1229a47a12beSStefan Roese bge 1f 1230a47a12beSStefan Roese 1231a47a12beSStefan Roese rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 1232a47a12beSStefan Roese add r11,r11,r0 1233a47a12beSStefan Roese lwz r11,0(r11) 1234a47a12beSStefan Roese 1235a47a12beSStefan Roese li r20,0xd00-4 /* Get stack pointer */ 1236a47a12beSStefan Roese lwz r12,0(r20) 1237a47a12beSStefan Roese subi r12,r12,12 /* Adjust stack pointer */ 1238a47a12beSStefan Roese li r0,0xc00+_end_back-SystemCall 1239a47a12beSStefan Roese cmplw 0,r0,r12 /* Check stack overflow */ 1240a47a12beSStefan Roese bgt 1f 1241a47a12beSStefan Roese stw r12,0(r20) 1242a47a12beSStefan Roese 1243a47a12beSStefan Roese mflr r0 1244a47a12beSStefan Roese stw r0,0(r12) 1245a47a12beSStefan Roese mfspr r0,SRR0 1246a47a12beSStefan Roese stw r0,4(r12) 1247a47a12beSStefan Roese mfspr r0,SRR1 1248a47a12beSStefan Roese stw r0,8(r12) 1249a47a12beSStefan Roese 1250a47a12beSStefan Roese li r12,0xc00+_back-SystemCall 1251a47a12beSStefan Roese mtlr r12 1252a47a12beSStefan Roese mtspr SRR0,r11 1253a47a12beSStefan Roese 1254a47a12beSStefan Roese1: SYNC 1255a47a12beSStefan Roese rfi 1256a47a12beSStefan Roese_back: 1257a47a12beSStefan Roese 1258a47a12beSStefan Roese mfmsr r11 /* Disable interrupts */ 1259a47a12beSStefan Roese li r12,0 1260a47a12beSStefan Roese ori r12,r12,MSR_EE 1261a47a12beSStefan Roese andc r11,r11,r12 1262a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 1263a47a12beSStefan Roese mtmsr r11 1264a47a12beSStefan Roese SYNC 1265a47a12beSStefan Roese 1266a47a12beSStefan Roese li r12,0xd00-4 /* restore regs */ 1267a47a12beSStefan Roese lwz r12,0(r12) 1268a47a12beSStefan Roese 1269a47a12beSStefan Roese lwz r11,0(r12) 1270a47a12beSStefan Roese mtlr r11 1271a47a12beSStefan Roese lwz r11,4(r12) 1272a47a12beSStefan Roese mtspr SRR0,r11 1273a47a12beSStefan Roese lwz r11,8(r12) 1274a47a12beSStefan Roese mtspr SRR1,r11 1275a47a12beSStefan Roese 1276a47a12beSStefan Roese addi r12,r12,12 /* Adjust stack pointer */ 1277a47a12beSStefan Roese li r20,0xd00-4 1278a47a12beSStefan Roese stw r12,0(r20) 1279a47a12beSStefan Roese 1280a47a12beSStefan Roese SYNC 1281a47a12beSStefan Roese rfi 1282a47a12beSStefan Roese_end_back: 1283a47a12beSStefan Roese 1284a47a12beSStefan Roese STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 1285a47a12beSStefan Roese STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 1286a47a12beSStefan Roese STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 1287a47a12beSStefan Roese 1288a47a12beSStefan Roese STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 1289a47a12beSStefan Roese STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 1290a47a12beSStefan Roese 1291a47a12beSStefan Roese CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 1292a47a12beSStefan Roese 1293a47a12beSStefan Roese .globl _end_of_vectors 1294a47a12beSStefan Roese_end_of_vectors: 1295a47a12beSStefan Roese 1296a47a12beSStefan Roese 1297a47a12beSStefan Roese . = . + (0x100 - ( . & 0xff )) /* align for debug */ 1298a47a12beSStefan Roese 1299a47a12beSStefan Roese/* 1300a47a12beSStefan Roese * This code finishes saving the registers to the exception frame 1301a47a12beSStefan Roese * and jumps to the appropriate handler for the exception. 1302a47a12beSStefan Roese * Register r21 is pointer into trap frame, r1 has new stack pointer. 1303a47a12beSStefan Roese */ 1304a47a12beSStefan Roese .globl transfer_to_handler 1305a47a12beSStefan Roesetransfer_to_handler: 1306a47a12beSStefan Roese stw r22,_NIP(r21) 1307a47a12beSStefan Roese lis r22,MSR_POW@h 1308a47a12beSStefan Roese andc r23,r23,r22 1309a47a12beSStefan Roese stw r23,_MSR(r21) 1310a47a12beSStefan Roese SAVE_GPR(7, r21) 1311a47a12beSStefan Roese SAVE_4GPRS(8, r21) 1312a47a12beSStefan Roese SAVE_8GPRS(12, r21) 1313a47a12beSStefan Roese SAVE_8GPRS(24, r21) 1314a47a12beSStefan Roese 1315a47a12beSStefan Roese mflr r23 1316a47a12beSStefan Roese andi. r24,r23,0x3f00 /* get vector offset */ 1317a47a12beSStefan Roese stw r24,TRAP(r21) 1318a47a12beSStefan Roese li r22,0 1319a47a12beSStefan Roese stw r22,RESULT(r21) 1320a47a12beSStefan Roese mtspr SPRG2,r22 /* r1 is now kernel sp */ 1321a47a12beSStefan Roese 1322a47a12beSStefan Roese lwz r24,0(r23) /* virtual address of handler */ 1323a47a12beSStefan Roese lwz r23,4(r23) /* where to go when done */ 1324a47a12beSStefan Roese mtspr SRR0,r24 1325a47a12beSStefan Roese mtspr SRR1,r20 1326a47a12beSStefan Roese mtlr r23 1327a47a12beSStefan Roese SYNC 1328a47a12beSStefan Roese rfi /* jump to handler, enable MMU */ 1329a47a12beSStefan Roese 1330a47a12beSStefan Roeseint_return: 1331a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 1332a47a12beSStefan Roese li r4,0 1333a47a12beSStefan Roese ori r4,r4,MSR_EE 1334a47a12beSStefan Roese andc r28,r28,r4 1335a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 1336a47a12beSStefan Roese mtmsr r28 1337a47a12beSStefan Roese SYNC 1338a47a12beSStefan Roese lwz r2,_CTR(r1) 1339a47a12beSStefan Roese lwz r0,_LINK(r1) 1340a47a12beSStefan Roese mtctr r2 1341a47a12beSStefan Roese mtlr r0 1342a47a12beSStefan Roese lwz r2,_XER(r1) 1343a47a12beSStefan Roese lwz r0,_CCR(r1) 1344a47a12beSStefan Roese mtspr XER,r2 1345a47a12beSStefan Roese mtcrf 0xFF,r0 1346a47a12beSStefan Roese REST_10GPRS(3, r1) 1347a47a12beSStefan Roese REST_10GPRS(13, r1) 1348a47a12beSStefan Roese REST_8GPRS(23, r1) 1349a47a12beSStefan Roese REST_GPR(31, r1) 1350a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 1351a47a12beSStefan Roese lwz r0,_MSR(r1) 1352a47a12beSStefan Roese mtspr SRR0,r2 1353a47a12beSStefan Roese mtspr SRR1,r0 1354a47a12beSStefan Roese lwz r0,GPR0(r1) 1355a47a12beSStefan Roese lwz r2,GPR2(r1) 1356a47a12beSStefan Roese lwz r1,GPR1(r1) 1357a47a12beSStefan Roese SYNC 1358a47a12beSStefan Roese rfi 1359a47a12beSStefan Roese 1360a47a12beSStefan Roesecrit_return: 1361a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 1362a47a12beSStefan Roese li r4,0 1363a47a12beSStefan Roese ori r4,r4,MSR_EE 1364a47a12beSStefan Roese andc r28,r28,r4 1365a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 1366a47a12beSStefan Roese mtmsr r28 1367a47a12beSStefan Roese SYNC 1368a47a12beSStefan Roese lwz r2,_CTR(r1) 1369a47a12beSStefan Roese lwz r0,_LINK(r1) 1370a47a12beSStefan Roese mtctr r2 1371a47a12beSStefan Roese mtlr r0 1372a47a12beSStefan Roese lwz r2,_XER(r1) 1373a47a12beSStefan Roese lwz r0,_CCR(r1) 1374a47a12beSStefan Roese mtspr XER,r2 1375a47a12beSStefan Roese mtcrf 0xFF,r0 1376a47a12beSStefan Roese REST_10GPRS(3, r1) 1377a47a12beSStefan Roese REST_10GPRS(13, r1) 1378a47a12beSStefan Roese REST_8GPRS(23, r1) 1379a47a12beSStefan Roese REST_GPR(31, r1) 1380a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 1381a47a12beSStefan Roese lwz r0,_MSR(r1) 1382a47a12beSStefan Roese mtspr SPRN_CSRR0,r2 1383a47a12beSStefan Roese mtspr SPRN_CSRR1,r0 1384a47a12beSStefan Roese lwz r0,GPR0(r1) 1385a47a12beSStefan Roese lwz r2,GPR2(r1) 1386a47a12beSStefan Roese lwz r1,GPR1(r1) 1387a47a12beSStefan Roese SYNC 1388a47a12beSStefan Roese rfci 1389a47a12beSStefan Roese 1390a47a12beSStefan Roesemck_return: 1391a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 1392a47a12beSStefan Roese li r4,0 1393a47a12beSStefan Roese ori r4,r4,MSR_EE 1394a47a12beSStefan Roese andc r28,r28,r4 1395a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 1396a47a12beSStefan Roese mtmsr r28 1397a47a12beSStefan Roese SYNC 1398a47a12beSStefan Roese lwz r2,_CTR(r1) 1399a47a12beSStefan Roese lwz r0,_LINK(r1) 1400a47a12beSStefan Roese mtctr r2 1401a47a12beSStefan Roese mtlr r0 1402a47a12beSStefan Roese lwz r2,_XER(r1) 1403a47a12beSStefan Roese lwz r0,_CCR(r1) 1404a47a12beSStefan Roese mtspr XER,r2 1405a47a12beSStefan Roese mtcrf 0xFF,r0 1406a47a12beSStefan Roese REST_10GPRS(3, r1) 1407a47a12beSStefan Roese REST_10GPRS(13, r1) 1408a47a12beSStefan Roese REST_8GPRS(23, r1) 1409a47a12beSStefan Roese REST_GPR(31, r1) 1410a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 1411a47a12beSStefan Roese lwz r0,_MSR(r1) 1412a47a12beSStefan Roese mtspr SPRN_MCSRR0,r2 1413a47a12beSStefan Roese mtspr SPRN_MCSRR1,r0 1414a47a12beSStefan Roese lwz r0,GPR0(r1) 1415a47a12beSStefan Roese lwz r2,GPR2(r1) 1416a47a12beSStefan Roese lwz r1,GPR1(r1) 1417a47a12beSStefan Roese SYNC 1418a47a12beSStefan Roese rfmci 1419a47a12beSStefan Roese 1420a47a12beSStefan Roese/* Cache functions. 1421a47a12beSStefan Roese*/ 14220a9fe8eeSMatthew McClintock.globl flush_icache 14230a9fe8eeSMatthew McClintockflush_icache: 1424a47a12beSStefan Roese.globl invalidate_icache 1425a47a12beSStefan Roeseinvalidate_icache: 1426a47a12beSStefan Roese mfspr r0,L1CSR1 1427a47a12beSStefan Roese ori r0,r0,L1CSR1_ICFI 1428a47a12beSStefan Roese msync 1429a47a12beSStefan Roese isync 1430a47a12beSStefan Roese mtspr L1CSR1,r0 1431a47a12beSStefan Roese isync 1432a47a12beSStefan Roese blr /* entire I cache */ 1433a47a12beSStefan Roese 1434a47a12beSStefan Roese.globl invalidate_dcache 1435a47a12beSStefan Roeseinvalidate_dcache: 1436a47a12beSStefan Roese mfspr r0,L1CSR0 1437a47a12beSStefan Roese ori r0,r0,L1CSR0_DCFI 1438a47a12beSStefan Roese msync 1439a47a12beSStefan Roese isync 1440a47a12beSStefan Roese mtspr L1CSR0,r0 1441a47a12beSStefan Roese isync 1442a47a12beSStefan Roese blr 1443a47a12beSStefan Roese 1444a47a12beSStefan Roese .globl icache_enable 1445a47a12beSStefan Roeseicache_enable: 1446a47a12beSStefan Roese mflr r8 1447a47a12beSStefan Roese bl invalidate_icache 1448a47a12beSStefan Roese mtlr r8 1449a47a12beSStefan Roese isync 1450a47a12beSStefan Roese mfspr r4,L1CSR1 1451a47a12beSStefan Roese ori r4,r4,0x0001 1452a47a12beSStefan Roese oris r4,r4,0x0001 1453a47a12beSStefan Roese mtspr L1CSR1,r4 1454a47a12beSStefan Roese isync 1455a47a12beSStefan Roese blr 1456a47a12beSStefan Roese 1457a47a12beSStefan Roese .globl icache_disable 1458a47a12beSStefan Roeseicache_disable: 1459a47a12beSStefan Roese mfspr r0,L1CSR1 1460a47a12beSStefan Roese lis r3,0 1461a47a12beSStefan Roese ori r3,r3,L1CSR1_ICE 1462a47a12beSStefan Roese andc r0,r0,r3 1463a47a12beSStefan Roese mtspr L1CSR1,r0 1464a47a12beSStefan Roese isync 1465a47a12beSStefan Roese blr 1466a47a12beSStefan Roese 1467a47a12beSStefan Roese .globl icache_status 1468a47a12beSStefan Roeseicache_status: 1469a47a12beSStefan Roese mfspr r3,L1CSR1 1470a47a12beSStefan Roese andi. r3,r3,L1CSR1_ICE 1471a47a12beSStefan Roese blr 1472a47a12beSStefan Roese 1473a47a12beSStefan Roese .globl dcache_enable 1474a47a12beSStefan Roesedcache_enable: 1475a47a12beSStefan Roese mflr r8 1476a47a12beSStefan Roese bl invalidate_dcache 1477a47a12beSStefan Roese mtlr r8 1478a47a12beSStefan Roese isync 1479a47a12beSStefan Roese mfspr r0,L1CSR0 1480a47a12beSStefan Roese ori r0,r0,0x0001 1481a47a12beSStefan Roese oris r0,r0,0x0001 1482a47a12beSStefan Roese msync 1483a47a12beSStefan Roese isync 1484a47a12beSStefan Roese mtspr L1CSR0,r0 1485a47a12beSStefan Roese isync 1486a47a12beSStefan Roese blr 1487a47a12beSStefan Roese 1488a47a12beSStefan Roese .globl dcache_disable 1489a47a12beSStefan Roesedcache_disable: 1490a47a12beSStefan Roese mfspr r3,L1CSR0 1491a47a12beSStefan Roese lis r4,0 1492a47a12beSStefan Roese ori r4,r4,L1CSR0_DCE 1493a47a12beSStefan Roese andc r3,r3,r4 149445a68135SKumar Gala mtspr L1CSR0,r3 1495a47a12beSStefan Roese isync 1496a47a12beSStefan Roese blr 1497a47a12beSStefan Roese 1498a47a12beSStefan Roese .globl dcache_status 1499a47a12beSStefan Roesedcache_status: 1500a47a12beSStefan Roese mfspr r3,L1CSR0 1501a47a12beSStefan Roese andi. r3,r3,L1CSR0_DCE 1502a47a12beSStefan Roese blr 1503a47a12beSStefan Roese 1504a47a12beSStefan Roese .globl get_pir 1505a47a12beSStefan Roeseget_pir: 1506a47a12beSStefan Roese mfspr r3,PIR 1507a47a12beSStefan Roese blr 1508a47a12beSStefan Roese 1509a47a12beSStefan Roese .globl get_pvr 1510a47a12beSStefan Roeseget_pvr: 1511a47a12beSStefan Roese mfspr r3,PVR 1512a47a12beSStefan Roese blr 1513a47a12beSStefan Roese 1514a47a12beSStefan Roese .globl get_svr 1515a47a12beSStefan Roeseget_svr: 1516a47a12beSStefan Roese mfspr r3,SVR 1517a47a12beSStefan Roese blr 1518a47a12beSStefan Roese 1519a47a12beSStefan Roese .globl wr_tcr 1520a47a12beSStefan Roesewr_tcr: 1521a47a12beSStefan Roese mtspr TCR,r3 1522a47a12beSStefan Roese blr 1523a47a12beSStefan Roese 1524a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1525a47a12beSStefan Roese/* Function: in8 */ 1526a47a12beSStefan Roese/* Description: Input 8 bits */ 1527a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1528a47a12beSStefan Roese .globl in8 1529a47a12beSStefan Roesein8: 1530a47a12beSStefan Roese lbz r3,0x0000(r3) 1531a47a12beSStefan Roese blr 1532a47a12beSStefan Roese 1533a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1534a47a12beSStefan Roese/* Function: out8 */ 1535a47a12beSStefan Roese/* Description: Output 8 bits */ 1536a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1537a47a12beSStefan Roese .globl out8 1538a47a12beSStefan Roeseout8: 1539a47a12beSStefan Roese stb r4,0x0000(r3) 1540a47a12beSStefan Roese sync 1541a47a12beSStefan Roese blr 1542a47a12beSStefan Roese 1543a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1544a47a12beSStefan Roese/* Function: out16 */ 1545a47a12beSStefan Roese/* Description: Output 16 bits */ 1546a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1547a47a12beSStefan Roese .globl out16 1548a47a12beSStefan Roeseout16: 1549a47a12beSStefan Roese sth r4,0x0000(r3) 1550a47a12beSStefan Roese sync 1551a47a12beSStefan Roese blr 1552a47a12beSStefan Roese 1553a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1554a47a12beSStefan Roese/* Function: out16r */ 1555a47a12beSStefan Roese/* Description: Byte reverse and output 16 bits */ 1556a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1557a47a12beSStefan Roese .globl out16r 1558a47a12beSStefan Roeseout16r: 1559a47a12beSStefan Roese sthbrx r4,r0,r3 1560a47a12beSStefan Roese sync 1561a47a12beSStefan Roese blr 1562a47a12beSStefan Roese 1563a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1564a47a12beSStefan Roese/* Function: out32 */ 1565a47a12beSStefan Roese/* Description: Output 32 bits */ 1566a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1567a47a12beSStefan Roese .globl out32 1568a47a12beSStefan Roeseout32: 1569a47a12beSStefan Roese stw r4,0x0000(r3) 1570a47a12beSStefan Roese sync 1571a47a12beSStefan Roese blr 1572a47a12beSStefan Roese 1573a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1574a47a12beSStefan Roese/* Function: out32r */ 1575a47a12beSStefan Roese/* Description: Byte reverse and output 32 bits */ 1576a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1577a47a12beSStefan Roese .globl out32r 1578a47a12beSStefan Roeseout32r: 1579a47a12beSStefan Roese stwbrx r4,r0,r3 1580a47a12beSStefan Roese sync 1581a47a12beSStefan Roese blr 1582a47a12beSStefan Roese 1583a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1584a47a12beSStefan Roese/* Function: in16 */ 1585a47a12beSStefan Roese/* Description: Input 16 bits */ 1586a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1587a47a12beSStefan Roese .globl in16 1588a47a12beSStefan Roesein16: 1589a47a12beSStefan Roese lhz r3,0x0000(r3) 1590a47a12beSStefan Roese blr 1591a47a12beSStefan Roese 1592a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1593a47a12beSStefan Roese/* Function: in16r */ 1594a47a12beSStefan Roese/* Description: Input 16 bits and byte reverse */ 1595a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1596a47a12beSStefan Roese .globl in16r 1597a47a12beSStefan Roesein16r: 1598a47a12beSStefan Roese lhbrx r3,r0,r3 1599a47a12beSStefan Roese blr 1600a47a12beSStefan Roese 1601a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1602a47a12beSStefan Roese/* Function: in32 */ 1603a47a12beSStefan Roese/* Description: Input 32 bits */ 1604a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1605a47a12beSStefan Roese .globl in32 1606a47a12beSStefan Roesein32: 1607a47a12beSStefan Roese lwz 3,0x0000(3) 1608a47a12beSStefan Roese blr 1609a47a12beSStefan Roese 1610a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1611a47a12beSStefan Roese/* Function: in32r */ 1612a47a12beSStefan Roese/* Description: Input 32 bits and byte reverse */ 1613a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1614a47a12beSStefan Roese .globl in32r 1615a47a12beSStefan Roesein32r: 1616a47a12beSStefan Roese lwbrx r3,r0,r3 1617a47a12beSStefan Roese blr 1618a47a12beSStefan Roese#endif /* !CONFIG_NAND_SPL */ 1619a47a12beSStefan Roese 1620a47a12beSStefan Roese/*------------------------------------------------------------------------------*/ 1621a47a12beSStefan Roese 1622a47a12beSStefan Roese/* 1623a47a12beSStefan Roese * void write_tlb(mas0, mas1, mas2, mas3, mas7) 1624a47a12beSStefan Roese */ 1625a47a12beSStefan Roese .globl write_tlb 1626a47a12beSStefan Roesewrite_tlb: 1627a47a12beSStefan Roese mtspr MAS0,r3 1628a47a12beSStefan Roese mtspr MAS1,r4 1629a47a12beSStefan Roese mtspr MAS2,r5 1630a47a12beSStefan Roese mtspr MAS3,r6 1631a47a12beSStefan Roese#ifdef CONFIG_ENABLE_36BIT_PHYS 1632a47a12beSStefan Roese mtspr MAS7,r7 1633a47a12beSStefan Roese#endif 1634a47a12beSStefan Roese li r3,0 1635a47a12beSStefan Roese#ifdef CONFIG_SYS_BOOK3E_HV 1636a47a12beSStefan Roese mtspr MAS8,r3 1637a47a12beSStefan Roese#endif 1638a47a12beSStefan Roese isync 1639a47a12beSStefan Roese tlbwe 1640a47a12beSStefan Roese msync 1641a47a12beSStefan Roese isync 1642a47a12beSStefan Roese blr 1643a47a12beSStefan Roese 1644a47a12beSStefan Roese/* 1645a47a12beSStefan Roese * void relocate_code (addr_sp, gd, addr_moni) 1646a47a12beSStefan Roese * 1647a47a12beSStefan Roese * This "function" does not return, instead it continues in RAM 1648a47a12beSStefan Roese * after relocating the monitor code. 1649a47a12beSStefan Roese * 1650a47a12beSStefan Roese * r3 = dest 1651a47a12beSStefan Roese * r4 = src 1652a47a12beSStefan Roese * r5 = length in bytes 1653a47a12beSStefan Roese * r6 = cachelinesize 1654a47a12beSStefan Roese */ 1655a47a12beSStefan Roese .globl relocate_code 1656a47a12beSStefan Roeserelocate_code: 1657a47a12beSStefan Roese mr r1,r3 /* Set new stack pointer */ 1658a47a12beSStefan Roese mr r9,r4 /* Save copy of Init Data pointer */ 1659a47a12beSStefan Roese mr r10,r5 /* Save copy of Destination Address */ 1660a47a12beSStefan Roese 1661a47a12beSStefan Roese GET_GOT 1662a47a12beSStefan Roese mr r3,r5 /* Destination Address */ 1663a47a12beSStefan Roese lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1664a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 1665a47a12beSStefan Roese lwz r5,GOT(__init_end) 1666a47a12beSStefan Roese sub r5,r5,r4 1667a47a12beSStefan Roese li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 1668a47a12beSStefan Roese 1669a47a12beSStefan Roese /* 1670a47a12beSStefan Roese * Fix GOT pointer: 1671a47a12beSStefan Roese * 1672a47a12beSStefan Roese * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1673a47a12beSStefan Roese * 1674a47a12beSStefan Roese * Offset: 1675a47a12beSStefan Roese */ 1676a47a12beSStefan Roese sub r15,r10,r4 1677a47a12beSStefan Roese 1678a47a12beSStefan Roese /* First our own GOT */ 1679a47a12beSStefan Roese add r12,r12,r15 1680a47a12beSStefan Roese /* the the one used by the C code */ 1681a47a12beSStefan Roese add r30,r30,r15 1682a47a12beSStefan Roese 1683a47a12beSStefan Roese /* 1684a47a12beSStefan Roese * Now relocate code 1685a47a12beSStefan Roese */ 1686a47a12beSStefan Roese 1687a47a12beSStefan Roese cmplw cr1,r3,r4 1688a47a12beSStefan Roese addi r0,r5,3 1689a47a12beSStefan Roese srwi. r0,r0,2 1690a47a12beSStefan Roese beq cr1,4f /* In place copy is not necessary */ 1691a47a12beSStefan Roese beq 7f /* Protect against 0 count */ 1692a47a12beSStefan Roese mtctr r0 1693a47a12beSStefan Roese bge cr1,2f 1694a47a12beSStefan Roese 1695a47a12beSStefan Roese la r8,-4(r4) 1696a47a12beSStefan Roese la r7,-4(r3) 1697a47a12beSStefan Roese1: lwzu r0,4(r8) 1698a47a12beSStefan Roese stwu r0,4(r7) 1699a47a12beSStefan Roese bdnz 1b 1700a47a12beSStefan Roese b 4f 1701a47a12beSStefan Roese 1702a47a12beSStefan Roese2: slwi r0,r0,2 1703a47a12beSStefan Roese add r8,r4,r0 1704a47a12beSStefan Roese add r7,r3,r0 1705a47a12beSStefan Roese3: lwzu r0,-4(r8) 1706a47a12beSStefan Roese stwu r0,-4(r7) 1707a47a12beSStefan Roese bdnz 3b 1708a47a12beSStefan Roese 1709a47a12beSStefan Roese/* 1710a47a12beSStefan Roese * Now flush the cache: note that we must start from a cache aligned 1711a47a12beSStefan Roese * address. Otherwise we might miss one cache line. 1712a47a12beSStefan Roese */ 1713a47a12beSStefan Roese4: cmpwi r6,0 1714a47a12beSStefan Roese add r5,r3,r5 1715a47a12beSStefan Roese beq 7f /* Always flush prefetch queue in any case */ 1716a47a12beSStefan Roese subi r0,r6,1 1717a47a12beSStefan Roese andc r3,r3,r0 1718a47a12beSStefan Roese mr r4,r3 1719a47a12beSStefan Roese5: dcbst 0,r4 1720a47a12beSStefan Roese add r4,r4,r6 1721a47a12beSStefan Roese cmplw r4,r5 1722a47a12beSStefan Roese blt 5b 1723a47a12beSStefan Roese sync /* Wait for all dcbst to complete on bus */ 1724a47a12beSStefan Roese mr r4,r3 1725a47a12beSStefan Roese6: icbi 0,r4 1726a47a12beSStefan Roese add r4,r4,r6 1727a47a12beSStefan Roese cmplw r4,r5 1728a47a12beSStefan Roese blt 6b 1729a47a12beSStefan Roese7: sync /* Wait for all icbi to complete on bus */ 1730a47a12beSStefan Roese isync 1731a47a12beSStefan Roese 1732a47a12beSStefan Roese/* 1733a47a12beSStefan Roese * We are done. Do not return, instead branch to second part of board 1734a47a12beSStefan Roese * initialization, now running from RAM. 1735a47a12beSStefan Roese */ 1736a47a12beSStefan Roese 1737a47a12beSStefan Roese addi r0,r10,in_ram - _start + _START_OFFSET 1738689f00fcSPrabhakar Kushwaha 1739689f00fcSPrabhakar Kushwaha /* 1740689f00fcSPrabhakar Kushwaha * As IVPR is going to point RAM address, 1741689f00fcSPrabhakar Kushwaha * Make sure IVOR15 has valid opcode to support debugger 1742689f00fcSPrabhakar Kushwaha */ 1743689f00fcSPrabhakar Kushwaha mtspr IVOR15,r0 1744689f00fcSPrabhakar Kushwaha 1745689f00fcSPrabhakar Kushwaha /* 1746689f00fcSPrabhakar Kushwaha * Re-point the IVPR at RAM 1747689f00fcSPrabhakar Kushwaha */ 1748689f00fcSPrabhakar Kushwaha mtspr IVPR,r10 1749689f00fcSPrabhakar Kushwaha 1750a47a12beSStefan Roese mtlr r0 1751a47a12beSStefan Roese blr /* NEVER RETURNS! */ 1752a47a12beSStefan Roese .globl in_ram 1753a47a12beSStefan Roesein_ram: 1754a47a12beSStefan Roese 1755a47a12beSStefan Roese /* 1756a47a12beSStefan Roese * Relocation Function, r12 point to got2+0x8000 1757a47a12beSStefan Roese * 1758a47a12beSStefan Roese * Adjust got2 pointers, no need to check for 0, this code 1759a47a12beSStefan Roese * already puts a few entries in the table. 1760a47a12beSStefan Roese */ 1761a47a12beSStefan Roese li r0,__got2_entries@sectoff@l 1762a47a12beSStefan Roese la r3,GOT(_GOT2_TABLE_) 1763a47a12beSStefan Roese lwz r11,GOT(_GOT2_TABLE_) 1764a47a12beSStefan Roese mtctr r0 1765a47a12beSStefan Roese sub r11,r3,r11 1766a47a12beSStefan Roese addi r3,r3,-4 1767a47a12beSStefan Roese1: lwzu r0,4(r3) 1768a47a12beSStefan Roese cmpwi r0,0 1769a47a12beSStefan Roese beq- 2f 1770a47a12beSStefan Roese add r0,r0,r11 1771a47a12beSStefan Roese stw r0,0(r3) 1772a47a12beSStefan Roese2: bdnz 1b 1773a47a12beSStefan Roese 1774a47a12beSStefan Roese /* 1775a47a12beSStefan Roese * Now adjust the fixups and the pointers to the fixups 1776a47a12beSStefan Roese * in case we need to move ourselves again. 1777a47a12beSStefan Roese */ 1778a47a12beSStefan Roese li r0,__fixup_entries@sectoff@l 1779a47a12beSStefan Roese lwz r3,GOT(_FIXUP_TABLE_) 1780a47a12beSStefan Roese cmpwi r0,0 1781a47a12beSStefan Roese mtctr r0 1782a47a12beSStefan Roese addi r3,r3,-4 1783a47a12beSStefan Roese beq 4f 1784a47a12beSStefan Roese3: lwzu r4,4(r3) 1785a47a12beSStefan Roese lwzux r0,r4,r11 1786d1e0b10aSJoakim Tjernlund cmpwi r0,0 1787a47a12beSStefan Roese add r0,r0,r11 178834bbf618SJoakim Tjernlund stw r4,0(r3) 1789d1e0b10aSJoakim Tjernlund beq- 5f 1790a47a12beSStefan Roese stw r0,0(r4) 1791d1e0b10aSJoakim Tjernlund5: bdnz 3b 1792a47a12beSStefan Roese4: 1793a47a12beSStefan Roeseclear_bss: 1794a47a12beSStefan Roese /* 1795a47a12beSStefan Roese * Now clear BSS segment 1796a47a12beSStefan Roese */ 1797a47a12beSStefan Roese lwz r3,GOT(__bss_start) 179844c6e659SPo-Yu Chuang lwz r4,GOT(__bss_end__) 1799a47a12beSStefan Roese 1800a47a12beSStefan Roese cmplw 0,r3,r4 1801a47a12beSStefan Roese beq 6f 1802a47a12beSStefan Roese 1803a47a12beSStefan Roese li r0,0 1804a47a12beSStefan Roese5: 1805a47a12beSStefan Roese stw r0,0(r3) 1806a47a12beSStefan Roese addi r3,r3,4 1807a47a12beSStefan Roese cmplw 0,r3,r4 1808a47a12beSStefan Roese bne 5b 1809a47a12beSStefan Roese6: 1810a47a12beSStefan Roese 1811a47a12beSStefan Roese mr r3,r9 /* Init Data pointer */ 1812a47a12beSStefan Roese mr r4,r10 /* Destination Address */ 1813a47a12beSStefan Roese bl board_init_r 1814a47a12beSStefan Roese 1815a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 1816a47a12beSStefan Roese /* 1817a47a12beSStefan Roese * Copy exception vector code to low memory 1818a47a12beSStefan Roese * 1819a47a12beSStefan Roese * r3: dest_addr 1820a47a12beSStefan Roese * r7: source address, r8: end address, r9: target address 1821a47a12beSStefan Roese */ 1822a47a12beSStefan Roese .globl trap_init 1823a47a12beSStefan Roesetrap_init: 1824a47a12beSStefan Roese mflr r4 /* save link register */ 1825a47a12beSStefan Roese GET_GOT 1826a47a12beSStefan Roese lwz r7,GOT(_start_of_vectors) 1827a47a12beSStefan Roese lwz r8,GOT(_end_of_vectors) 1828a47a12beSStefan Roese 1829a47a12beSStefan Roese li r9,0x100 /* reset vector always at 0x100 */ 1830a47a12beSStefan Roese 1831a47a12beSStefan Roese cmplw 0,r7,r8 1832a47a12beSStefan Roese bgelr /* return if r7>=r8 - just in case */ 1833a47a12beSStefan Roese1: 1834a47a12beSStefan Roese lwz r0,0(r7) 1835a47a12beSStefan Roese stw r0,0(r9) 1836a47a12beSStefan Roese addi r7,r7,4 1837a47a12beSStefan Roese addi r9,r9,4 1838a47a12beSStefan Roese cmplw 0,r7,r8 1839a47a12beSStefan Roese bne 1b 1840a47a12beSStefan Roese 1841a47a12beSStefan Roese /* 1842a47a12beSStefan Roese * relocate `hdlr' and `int_return' entries 1843a47a12beSStefan Roese */ 1844a47a12beSStefan Roese li r7,.L_CriticalInput - _start + _START_OFFSET 1845a47a12beSStefan Roese bl trap_reloc 1846a47a12beSStefan Roese li r7,.L_MachineCheck - _start + _START_OFFSET 1847a47a12beSStefan Roese bl trap_reloc 1848a47a12beSStefan Roese li r7,.L_DataStorage - _start + _START_OFFSET 1849a47a12beSStefan Roese bl trap_reloc 1850a47a12beSStefan Roese li r7,.L_InstStorage - _start + _START_OFFSET 1851a47a12beSStefan Roese bl trap_reloc 1852a47a12beSStefan Roese li r7,.L_ExtInterrupt - _start + _START_OFFSET 1853a47a12beSStefan Roese bl trap_reloc 1854a47a12beSStefan Roese li r7,.L_Alignment - _start + _START_OFFSET 1855a47a12beSStefan Roese bl trap_reloc 1856a47a12beSStefan Roese li r7,.L_ProgramCheck - _start + _START_OFFSET 1857a47a12beSStefan Roese bl trap_reloc 1858a47a12beSStefan Roese li r7,.L_FPUnavailable - _start + _START_OFFSET 1859a47a12beSStefan Roese bl trap_reloc 1860a47a12beSStefan Roese li r7,.L_Decrementer - _start + _START_OFFSET 1861a47a12beSStefan Roese bl trap_reloc 1862a47a12beSStefan Roese li r7,.L_IntervalTimer - _start + _START_OFFSET 1863a47a12beSStefan Roese li r8,_end_of_vectors - _start + _START_OFFSET 1864a47a12beSStefan Roese2: 1865a47a12beSStefan Roese bl trap_reloc 1866a47a12beSStefan Roese addi r7,r7,0x100 /* next exception vector */ 1867a47a12beSStefan Roese cmplw 0,r7,r8 1868a47a12beSStefan Roese blt 2b 1869a47a12beSStefan Roese 187064829bafSPrabhakar Kushwaha /* Update IVORs as per relocated vector table address */ 187164829bafSPrabhakar Kushwaha li r7,0x0100 187264829bafSPrabhakar Kushwaha mtspr IVOR0,r7 /* 0: Critical input */ 187364829bafSPrabhakar Kushwaha li r7,0x0200 187464829bafSPrabhakar Kushwaha mtspr IVOR1,r7 /* 1: Machine check */ 187564829bafSPrabhakar Kushwaha li r7,0x0300 187664829bafSPrabhakar Kushwaha mtspr IVOR2,r7 /* 2: Data storage */ 187764829bafSPrabhakar Kushwaha li r7,0x0400 187864829bafSPrabhakar Kushwaha mtspr IVOR3,r7 /* 3: Instruction storage */ 187964829bafSPrabhakar Kushwaha li r7,0x0500 188064829bafSPrabhakar Kushwaha mtspr IVOR4,r7 /* 4: External interrupt */ 188164829bafSPrabhakar Kushwaha li r7,0x0600 188264829bafSPrabhakar Kushwaha mtspr IVOR5,r7 /* 5: Alignment */ 188364829bafSPrabhakar Kushwaha li r7,0x0700 188464829bafSPrabhakar Kushwaha mtspr IVOR6,r7 /* 6: Program check */ 188564829bafSPrabhakar Kushwaha li r7,0x0800 188664829bafSPrabhakar Kushwaha mtspr IVOR7,r7 /* 7: floating point unavailable */ 188764829bafSPrabhakar Kushwaha li r7,0x0900 188864829bafSPrabhakar Kushwaha mtspr IVOR8,r7 /* 8: System call */ 188964829bafSPrabhakar Kushwaha /* 9: Auxiliary processor unavailable(unsupported) */ 189064829bafSPrabhakar Kushwaha li r7,0x0a00 189164829bafSPrabhakar Kushwaha mtspr IVOR10,r7 /* 10: Decrementer */ 189264829bafSPrabhakar Kushwaha li r7,0x0b00 189364829bafSPrabhakar Kushwaha mtspr IVOR11,r7 /* 11: Interval timer */ 189464829bafSPrabhakar Kushwaha li r7,0x0c00 189564829bafSPrabhakar Kushwaha mtspr IVOR12,r7 /* 12: Watchdog timer */ 189664829bafSPrabhakar Kushwaha li r7,0x0d00 189764829bafSPrabhakar Kushwaha mtspr IVOR13,r7 /* 13: Data TLB error */ 189864829bafSPrabhakar Kushwaha li r7,0x0e00 189964829bafSPrabhakar Kushwaha mtspr IVOR14,r7 /* 14: Instruction TLB error */ 190064829bafSPrabhakar Kushwaha li r7,0x0f00 190164829bafSPrabhakar Kushwaha mtspr IVOR15,r7 /* 15: Debug */ 190264829bafSPrabhakar Kushwaha 1903a47a12beSStefan Roese lis r7,0x0 1904a47a12beSStefan Roese mtspr IVPR,r7 1905a47a12beSStefan Roese 1906a47a12beSStefan Roese mtlr r4 /* restore link register */ 1907a47a12beSStefan Roese blr 1908a47a12beSStefan Roese 1909a47a12beSStefan Roese.globl unlock_ram_in_cache 1910a47a12beSStefan Roeseunlock_ram_in_cache: 1911a47a12beSStefan Roese /* invalidate the INIT_RAM section */ 1912a47a12beSStefan Roese lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1913a47a12beSStefan Roese ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1914a47a12beSStefan Roese mfspr r4,L1CFG0 1915a47a12beSStefan Roese andi. r4,r4,0x1ff 1916a47a12beSStefan Roese slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1917a47a12beSStefan Roese mtctr r4 1918a47a12beSStefan Roese1: dcbi r0,r3 1919a47a12beSStefan Roese addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1920a47a12beSStefan Roese bdnz 1b 1921a47a12beSStefan Roese sync 1922a47a12beSStefan Roese 1923a47a12beSStefan Roese /* Invalidate the TLB entries for the cache */ 1924a47a12beSStefan Roese lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1925a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1926a47a12beSStefan Roese tlbivax 0,r3 1927a47a12beSStefan Roese addi r3,r3,0x1000 1928a47a12beSStefan Roese tlbivax 0,r3 1929a47a12beSStefan Roese addi r3,r3,0x1000 1930a47a12beSStefan Roese tlbivax 0,r3 1931a47a12beSStefan Roese addi r3,r3,0x1000 1932a47a12beSStefan Roese tlbivax 0,r3 1933a47a12beSStefan Roese isync 1934a47a12beSStefan Roese blr 1935a47a12beSStefan Roese 1936a47a12beSStefan Roese.globl flush_dcache 1937a47a12beSStefan Roeseflush_dcache: 1938a47a12beSStefan Roese mfspr r3,SPRN_L1CFG0 1939a47a12beSStefan Roese 1940a47a12beSStefan Roese rlwinm r5,r3,9,3 /* Extract cache block size */ 1941a47a12beSStefan Roese twlgti r5,1 /* Only 32 and 64 byte cache blocks 1942a47a12beSStefan Roese * are currently defined. 1943a47a12beSStefan Roese */ 1944a47a12beSStefan Roese li r4,32 1945a47a12beSStefan Roese subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1946a47a12beSStefan Roese * log2(number of ways) 1947a47a12beSStefan Roese */ 1948a47a12beSStefan Roese slw r5,r4,r5 /* r5 = cache block size */ 1949a47a12beSStefan Roese 1950a47a12beSStefan Roese rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1951a47a12beSStefan Roese mulli r7,r7,13 /* An 8-way cache will require 13 1952a47a12beSStefan Roese * loads per set. 1953a47a12beSStefan Roese */ 1954a47a12beSStefan Roese slw r7,r7,r6 1955a47a12beSStefan Roese 1956a47a12beSStefan Roese /* save off HID0 and set DCFA */ 1957a47a12beSStefan Roese mfspr r8,SPRN_HID0 1958a47a12beSStefan Roese ori r9,r8,HID0_DCFA@l 1959a47a12beSStefan Roese mtspr SPRN_HID0,r9 1960a47a12beSStefan Roese isync 1961a47a12beSStefan Roese 1962a47a12beSStefan Roese lis r4,0 1963a47a12beSStefan Roese mtctr r7 1964a47a12beSStefan Roese 1965a47a12beSStefan Roese1: lwz r3,0(r4) /* Load... */ 1966a47a12beSStefan Roese add r4,r4,r5 1967a47a12beSStefan Roese bdnz 1b 1968a47a12beSStefan Roese 1969a47a12beSStefan Roese msync 1970a47a12beSStefan Roese lis r4,0 1971a47a12beSStefan Roese mtctr r7 1972a47a12beSStefan Roese 1973a47a12beSStefan Roese1: dcbf 0,r4 /* ...and flush. */ 1974a47a12beSStefan Roese add r4,r4,r5 1975a47a12beSStefan Roese bdnz 1b 1976a47a12beSStefan Roese 1977a47a12beSStefan Roese /* restore HID0 */ 1978a47a12beSStefan Roese mtspr SPRN_HID0,r8 1979a47a12beSStefan Roese isync 1980a47a12beSStefan Roese 1981a47a12beSStefan Roese blr 1982a47a12beSStefan Roese 1983a47a12beSStefan Roese.globl setup_ivors 1984a47a12beSStefan Roesesetup_ivors: 1985a47a12beSStefan Roese 1986a47a12beSStefan Roese#include "fixed_ivor.S" 1987a47a12beSStefan Roese blr 1988a47a12beSStefan Roese#endif /* !CONFIG_NAND_SPL */ 1989