1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <ppc_asm.tmpl> 31 #include <asm/processor.h> 32 #include <asm/io.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* --------------------------------------------------------------- */ 37 38 void get_sys_info (sys_info_t * sysInfo) 39 { 40 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 41 #ifdef CONFIG_FSL_CORENET 42 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 43 44 const u8 core_cplx_PLL[16] = { 45 [ 0] = 0, /* CC1 PPL / 1 */ 46 [ 1] = 0, /* CC1 PPL / 2 */ 47 [ 2] = 0, /* CC1 PPL / 4 */ 48 [ 4] = 1, /* CC2 PPL / 1 */ 49 [ 5] = 1, /* CC2 PPL / 2 */ 50 [ 6] = 1, /* CC2 PPL / 4 */ 51 [ 8] = 2, /* CC3 PPL / 1 */ 52 [ 9] = 2, /* CC3 PPL / 2 */ 53 [10] = 2, /* CC3 PPL / 4 */ 54 [12] = 3, /* CC4 PPL / 1 */ 55 [13] = 3, /* CC4 PPL / 2 */ 56 [14] = 3, /* CC4 PPL / 4 */ 57 }; 58 59 const u8 core_cplx_PLL_div[16] = { 60 [ 0] = 1, /* CC1 PPL / 1 */ 61 [ 1] = 2, /* CC1 PPL / 2 */ 62 [ 2] = 4, /* CC1 PPL / 4 */ 63 [ 4] = 1, /* CC2 PPL / 1 */ 64 [ 5] = 2, /* CC2 PPL / 2 */ 65 [ 6] = 4, /* CC2 PPL / 4 */ 66 [ 8] = 1, /* CC3 PPL / 1 */ 67 [ 9] = 2, /* CC3 PPL / 2 */ 68 [10] = 4, /* CC3 PPL / 4 */ 69 [12] = 1, /* CC4 PPL / 1 */ 70 [13] = 2, /* CC4 PPL / 2 */ 71 [14] = 4, /* CC4 PPL / 4 */ 72 }; 73 uint lcrr_div, i, freqCC_PLL[4], rcw_tmp; 74 uint ratio[4]; 75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 76 uint mem_pll_rat; 77 78 sysInfo->freqSystemBus = sysclk; 79 sysInfo->freqDDRBus = sysclk; 80 81 sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 82 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f; 83 if (mem_pll_rat > 2) 84 sysInfo->freqDDRBus *= mem_pll_rat; 85 else 86 sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat; 87 88 ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; 89 ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; 90 ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; 91 ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; 92 for (i = 0; i < 4; i++) { 93 if (ratio[i] > 4) 94 freqCC_PLL[i] = sysclk * ratio[i]; 95 else 96 freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i]; 97 } 98 rcw_tmp = in_be32(&gur->rcwsr[3]); 99 for (i = 0; i < cpu_numcores(); i++) { 100 u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf; 101 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 102 103 sysInfo->freqProcessor[i] = 104 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; 105 } 106 107 #define PME_CLK_SEL 0x80000000 108 #define FM1_CLK_SEL 0x40000000 109 #define FM2_CLK_SEL 0x20000000 110 #define HWA_ASYNC_DIV 0x04000000 111 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 112 #define HWA_CC_PLL 1 113 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 114 #define HWA_CC_PLL 2 115 #else 116 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 117 #endif 118 rcw_tmp = in_be32(&gur->rcwsr[7]); 119 120 #ifdef CONFIG_SYS_DPAA_PME 121 if (rcw_tmp & PME_CLK_SEL) { 122 if (rcw_tmp & HWA_ASYNC_DIV) 123 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; 124 else 125 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; 126 } else { 127 sysInfo->freqPME = sysInfo->freqSystemBus / 2; 128 } 129 #endif 130 131 #ifdef CONFIG_SYS_DPAA_FMAN 132 if (rcw_tmp & FM1_CLK_SEL) { 133 if (rcw_tmp & HWA_ASYNC_DIV) 134 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; 135 else 136 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; 137 } else { 138 sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; 139 } 140 #if (CONFIG_SYS_NUM_FMAN) == 2 141 if (rcw_tmp & FM2_CLK_SEL) { 142 if (rcw_tmp & HWA_ASYNC_DIV) 143 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; 144 else 145 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; 146 } else { 147 sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; 148 } 149 #endif 150 #endif 151 152 #else 153 uint plat_ratio,e500_ratio,half_freqSystemBus; 154 #if defined(CONFIG_FSL_LBC) 155 uint lcrr_div; 156 #endif 157 int i; 158 #ifdef CONFIG_QE 159 u32 qe_ratio; 160 #endif 161 162 plat_ratio = (gur->porpllsr) & 0x0000003e; 163 plat_ratio >>= 1; 164 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; 165 166 /* Divide before multiply to avoid integer 167 * overflow for processor speeds above 2GHz */ 168 half_freqSystemBus = sysInfo->freqSystemBus/2; 169 for (i = 0; i < cpu_numcores(); i++) { 170 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 171 sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus; 172 } 173 174 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ 175 sysInfo->freqDDRBus = sysInfo->freqSystemBus; 176 177 #ifdef CONFIG_DDR_CLK_FREQ 178 { 179 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 180 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 181 if (ddr_ratio != 0x7) 182 sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 183 } 184 #endif 185 186 #ifdef CONFIG_QE 187 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 188 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 189 sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; 190 #endif 191 192 #ifdef CONFIG_SYS_DPAA_FMAN 193 sysInfo->freqFMan[0] = sysInfo->freqSystemBus; 194 #endif 195 196 #endif /* CONFIG_FSL_CORENET */ 197 198 #if defined(CONFIG_FSL_LBC) 199 #if defined(CONFIG_SYS_LBC_LCRR) 200 /* We will program LCRR to this value later */ 201 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 202 #else 203 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 204 #endif 205 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 206 #if defined(CONFIG_FSL_CORENET) 207 /* If this is corenet based SoC, bit-representation 208 * for four times the clock divider values. 209 */ 210 lcrr_div *= 4; 211 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 212 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 213 /* 214 * Yes, the entire PQ38 family use the same 215 * bit-representation for twice the clock divider values. 216 */ 217 lcrr_div *= 2; 218 #endif 219 sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div; 220 } else { 221 /* In case anyone cares what the unknown value is */ 222 sysInfo->freqLocalBus = lcrr_div; 223 } 224 #endif 225 } 226 227 228 int get_clocks (void) 229 { 230 sys_info_t sys_info; 231 #ifdef CONFIG_MPC8544 232 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 233 #endif 234 #if defined(CONFIG_CPM2) 235 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 236 uint sccr, dfbrg; 237 238 /* set VCO = 4 * BRG */ 239 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 240 sccr = cpm->im_cpm_intctl.sccr; 241 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 242 #endif 243 get_sys_info (&sys_info); 244 gd->cpu_clk = sys_info.freqProcessor[0]; 245 gd->bus_clk = sys_info.freqSystemBus; 246 gd->mem_clk = sys_info.freqDDRBus; 247 gd->lbc_clk = sys_info.freqLocalBus; 248 249 #ifdef CONFIG_QE 250 gd->qe_clk = sys_info.freqQE; 251 gd->brg_clk = gd->qe_clk / 2; 252 #endif 253 /* 254 * The base clock for I2C depends on the actual SOC. Unfortunately, 255 * there is no pattern that can be used to determine the frequency, so 256 * the only choice is to look up the actual SOC number and use the value 257 * for that SOC. This information is taken from application note 258 * AN2919. 259 */ 260 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 261 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) 262 gd->i2c1_clk = sys_info.freqSystemBus; 263 #elif defined(CONFIG_MPC8544) 264 /* 265 * On the 8544, the I2C clock is the same as the SEC clock. This can be 266 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 267 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 268 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 269 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 270 */ 271 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 272 gd->i2c1_clk = sys_info.freqSystemBus / 3; 273 else 274 gd->i2c1_clk = sys_info.freqSystemBus / 2; 275 #else 276 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 277 gd->i2c1_clk = sys_info.freqSystemBus / 2; 278 #endif 279 gd->i2c2_clk = gd->i2c1_clk; 280 281 #if defined(CONFIG_FSL_ESDHC) 282 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 283 defined(CONFIG_P1014) 284 gd->sdhc_clk = gd->bus_clk; 285 #else 286 gd->sdhc_clk = gd->bus_clk / 2; 287 #endif 288 #endif /* defined(CONFIG_FSL_ESDHC) */ 289 290 #if defined(CONFIG_CPM2) 291 gd->vco_out = 2*sys_info.freqSystemBus; 292 gd->cpm_clk = gd->vco_out / 2; 293 gd->scc_clk = gd->vco_out / 4; 294 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); 295 #endif 296 297 if(gd->cpu_clk != 0) return (0); 298 else return (1); 299 } 300 301 302 /******************************************** 303 * get_bus_freq 304 * return system bus freq in Hz 305 *********************************************/ 306 ulong get_bus_freq (ulong dummy) 307 { 308 return gd->bus_clk; 309 } 310 311 /******************************************** 312 * get_ddr_freq 313 * return ddr bus freq in Hz 314 *********************************************/ 315 ulong get_ddr_freq (ulong dummy) 316 { 317 return gd->mem_clk; 318 } 319