1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <ppc_asm.tmpl> 31 #include <linux/compiler.h> 32 #include <asm/processor.h> 33 #include <asm/io.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 /* --------------------------------------------------------------- */ 38 39 void get_sys_info (sys_info_t * sysInfo) 40 { 41 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 42 #ifdef CONFIG_FSL_IFC 43 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 44 u32 ccr; 45 #endif 46 #ifdef CONFIG_FSL_CORENET 47 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 48 unsigned int cpu; 49 50 const u8 core_cplx_PLL[16] = { 51 [ 0] = 0, /* CC1 PPL / 1 */ 52 [ 1] = 0, /* CC1 PPL / 2 */ 53 [ 2] = 0, /* CC1 PPL / 4 */ 54 [ 4] = 1, /* CC2 PPL / 1 */ 55 [ 5] = 1, /* CC2 PPL / 2 */ 56 [ 6] = 1, /* CC2 PPL / 4 */ 57 [ 8] = 2, /* CC3 PPL / 1 */ 58 [ 9] = 2, /* CC3 PPL / 2 */ 59 [10] = 2, /* CC3 PPL / 4 */ 60 [12] = 3, /* CC4 PPL / 1 */ 61 [13] = 3, /* CC4 PPL / 2 */ 62 [14] = 3, /* CC4 PPL / 4 */ 63 }; 64 65 const u8 core_cplx_PLL_div[16] = { 66 [ 0] = 1, /* CC1 PPL / 1 */ 67 [ 1] = 2, /* CC1 PPL / 2 */ 68 [ 2] = 4, /* CC1 PPL / 4 */ 69 [ 4] = 1, /* CC2 PPL / 1 */ 70 [ 5] = 2, /* CC2 PPL / 2 */ 71 [ 6] = 4, /* CC2 PPL / 4 */ 72 [ 8] = 1, /* CC3 PPL / 1 */ 73 [ 9] = 2, /* CC3 PPL / 2 */ 74 [10] = 4, /* CC3 PPL / 4 */ 75 [12] = 1, /* CC4 PPL / 1 */ 76 [13] = 2, /* CC4 PPL / 2 */ 77 [14] = 4, /* CC4 PPL / 4 */ 78 }; 79 uint lcrr_div, i, freqCC_PLL[4], rcw_tmp; 80 uint ratio[4]; 81 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 82 uint mem_pll_rat; 83 84 sysInfo->freqSystemBus = sysclk; 85 sysInfo->freqDDRBus = sysclk; 86 87 sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 88 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f; 89 if (mem_pll_rat > 2) 90 sysInfo->freqDDRBus *= mem_pll_rat; 91 else 92 sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat; 93 94 ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; 95 ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; 96 ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; 97 ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; 98 for (i = 0; i < 4; i++) { 99 if (ratio[i] > 4) 100 freqCC_PLL[i] = sysclk * ratio[i]; 101 else 102 freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i]; 103 } 104 rcw_tmp = in_be32(&gur->rcwsr[3]); 105 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 106 u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf; 107 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 108 109 sysInfo->freqProcessor[cpu] = 110 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; 111 } 112 113 #define PME_CLK_SEL 0x80000000 114 #define FM1_CLK_SEL 0x40000000 115 #define FM2_CLK_SEL 0x20000000 116 #define HWA_ASYNC_DIV 0x04000000 117 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 118 #define HWA_CC_PLL 1 119 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 120 #define HWA_CC_PLL 2 121 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 122 #define HWA_CC_PLL 2 123 #else 124 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 125 #endif 126 rcw_tmp = in_be32(&gur->rcwsr[7]); 127 128 #ifdef CONFIG_SYS_DPAA_PME 129 if (rcw_tmp & PME_CLK_SEL) { 130 if (rcw_tmp & HWA_ASYNC_DIV) 131 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; 132 else 133 sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; 134 } else { 135 sysInfo->freqPME = sysInfo->freqSystemBus / 2; 136 } 137 #endif 138 139 #ifdef CONFIG_SYS_DPAA_FMAN 140 if (rcw_tmp & FM1_CLK_SEL) { 141 if (rcw_tmp & HWA_ASYNC_DIV) 142 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; 143 else 144 sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; 145 } else { 146 sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; 147 } 148 #if (CONFIG_SYS_NUM_FMAN) == 2 149 if (rcw_tmp & FM2_CLK_SEL) { 150 if (rcw_tmp & HWA_ASYNC_DIV) 151 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; 152 else 153 sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; 154 } else { 155 sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; 156 } 157 #endif 158 #endif 159 160 #else 161 uint plat_ratio,e500_ratio,half_freqSystemBus; 162 #if defined(CONFIG_FSL_LBC) 163 uint lcrr_div; 164 #endif 165 int i; 166 #ifdef CONFIG_QE 167 __maybe_unused u32 qe_ratio; 168 #endif 169 170 plat_ratio = (gur->porpllsr) & 0x0000003e; 171 plat_ratio >>= 1; 172 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; 173 174 /* Divide before multiply to avoid integer 175 * overflow for processor speeds above 2GHz */ 176 half_freqSystemBus = sysInfo->freqSystemBus/2; 177 for (i = 0; i < cpu_numcores(); i++) { 178 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 179 sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus; 180 } 181 182 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ 183 sysInfo->freqDDRBus = sysInfo->freqSystemBus; 184 185 #ifdef CONFIG_DDR_CLK_FREQ 186 { 187 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 188 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 189 if (ddr_ratio != 0x7) 190 sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 191 } 192 #endif 193 194 #ifdef CONFIG_QE 195 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 196 sysInfo->freqQE = sysInfo->freqSystemBus; 197 #else 198 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 199 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 200 sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; 201 #endif 202 #endif 203 204 #ifdef CONFIG_SYS_DPAA_FMAN 205 sysInfo->freqFMan[0] = sysInfo->freqSystemBus; 206 #endif 207 208 #endif /* CONFIG_FSL_CORENET */ 209 210 #if defined(CONFIG_FSL_LBC) 211 #if defined(CONFIG_SYS_LBC_LCRR) 212 /* We will program LCRR to this value later */ 213 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 214 #else 215 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 216 #endif 217 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 218 #if defined(CONFIG_FSL_CORENET) 219 /* If this is corenet based SoC, bit-representation 220 * for four times the clock divider values. 221 */ 222 lcrr_div *= 4; 223 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 224 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 225 /* 226 * Yes, the entire PQ38 family use the same 227 * bit-representation for twice the clock divider values. 228 */ 229 lcrr_div *= 2; 230 #endif 231 sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div; 232 } else { 233 /* In case anyone cares what the unknown value is */ 234 sysInfo->freqLocalBus = lcrr_div; 235 } 236 #endif 237 238 #if defined(CONFIG_FSL_IFC) 239 ccr = in_be32(&ifc_regs->ifc_ccr); 240 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 241 242 sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr; 243 #endif 244 } 245 246 247 int get_clocks (void) 248 { 249 sys_info_t sys_info; 250 #ifdef CONFIG_MPC8544 251 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 252 #endif 253 #if defined(CONFIG_CPM2) 254 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 255 uint sccr, dfbrg; 256 257 /* set VCO = 4 * BRG */ 258 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 259 sccr = cpm->im_cpm_intctl.sccr; 260 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 261 #endif 262 get_sys_info (&sys_info); 263 gd->cpu_clk = sys_info.freqProcessor[0]; 264 gd->bus_clk = sys_info.freqSystemBus; 265 gd->mem_clk = sys_info.freqDDRBus; 266 gd->lbc_clk = sys_info.freqLocalBus; 267 268 #ifdef CONFIG_QE 269 gd->qe_clk = sys_info.freqQE; 270 gd->brg_clk = gd->qe_clk / 2; 271 #endif 272 /* 273 * The base clock for I2C depends on the actual SOC. Unfortunately, 274 * there is no pattern that can be used to determine the frequency, so 275 * the only choice is to look up the actual SOC number and use the value 276 * for that SOC. This information is taken from application note 277 * AN2919. 278 */ 279 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 280 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) 281 gd->i2c1_clk = sys_info.freqSystemBus; 282 #elif defined(CONFIG_MPC8544) 283 /* 284 * On the 8544, the I2C clock is the same as the SEC clock. This can be 285 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 286 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 287 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 288 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 289 */ 290 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 291 gd->i2c1_clk = sys_info.freqSystemBus / 3; 292 else 293 gd->i2c1_clk = sys_info.freqSystemBus / 2; 294 #else 295 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 296 gd->i2c1_clk = sys_info.freqSystemBus / 2; 297 #endif 298 gd->i2c2_clk = gd->i2c1_clk; 299 300 #if defined(CONFIG_FSL_ESDHC) 301 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 302 defined(CONFIG_P1014) 303 gd->sdhc_clk = gd->bus_clk; 304 #else 305 gd->sdhc_clk = gd->bus_clk / 2; 306 #endif 307 #endif /* defined(CONFIG_FSL_ESDHC) */ 308 309 #if defined(CONFIG_CPM2) 310 gd->vco_out = 2*sys_info.freqSystemBus; 311 gd->cpm_clk = gd->vco_out / 2; 312 gd->scc_clk = gd->vco_out / 4; 313 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); 314 #endif 315 316 if(gd->cpu_clk != 0) return (0); 317 else return (1); 318 } 319 320 321 /******************************************** 322 * get_bus_freq 323 * return system bus freq in Hz 324 *********************************************/ 325 ulong get_bus_freq (ulong dummy) 326 { 327 return gd->bus_clk; 328 } 329 330 /******************************************** 331 * get_ddr_freq 332 * return ddr bus freq in Hz 333 *********************************************/ 334 ulong get_ddr_freq (ulong dummy) 335 { 336 return gd->mem_clk; 337 } 338