xref: /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/release.S (revision 33eee330cc8a445ff05f39a58af3c87324798230) 
1/*
2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc85xx.h>
27#include <version.h>
28
29#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33
34#include <asm/cache.h>
35#include <asm/mmu.h>
36
37/* To boot secondary cpus, we need a place for them to start up.
38 * Normally, they start at 0xfffffffc, but that's usually the
39 * firmware, and we don't want to have to run the firmware again.
40 * Instead, the primary cpu will set the BPTR to point here to
41 * this page.  We then set up the core, and head to
42 * start_secondary.  Note that this means that the code below
43 * must never exceed 1023 instructions (the branch at the end
44 * would then be the 1024th).
45 */
46	.globl	__secondary_start_page
47	.align	12
48__secondary_start_page:
49/* First do some preliminary setup */
50	lis	r3, HID0_EMCP@h		/* enable machine check */
51#ifndef CONFIG_E500MC
52	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
53#endif
54#ifdef CONFIG_PHYS_64BIT
55	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
56#endif
57	mtspr	SPRN_HID0,r3
58
59#ifndef CONFIG_E500MC
60	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
61	mfspr   r0,PVR
62	andi.	r0,r0,0xff
63	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
64	blt 1f
65	/* Set MBDD bit also */
66	ori r3, r3, HID1_MBDD@l
671:
68	mtspr	SPRN_HID1,r3
69#endif
70
71#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
72	mfspr	r3,977
73	oris	r3,r3,0x0100
74	mtspr	977,r3
75#endif
76
77#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
78	mfspr	r3,SPRN_SVR
79	rlwinm	r3,r3,0,0xff
80	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
81	cmpw	r3,r4
82	beq	1f
83
84#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
85	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
86	cmpw	r3,r4
87	beq	1f
88#endif
89
90	/* Not a supported revision affected by erratum */
91	b	2f
92
931:	/* Erratum says set bits 55:60 to 001001 */
94	msync
95	isync
96	mfspr	r3,976
97	li	r4,0x48
98	rlwimi	r3,r4,0,0x1f8
99	mtspr	976,r3
100	isync
1012:
102#endif
103
104	/* Enable branch prediction */
105	lis	r3,BUCSR_ENABLE@h
106	ori	r3,r3,BUCSR_ENABLE@l
107	mtspr	SPRN_BUCSR,r3
108
109	/* Ensure TB is 0 */
110	li	r3,0
111	mttbl	r3
112	mttbu	r3
113
114	/* Enable/invalidate the I-Cache */
115	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
116	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
117	mtspr	SPRN_L1CSR1,r2
1181:
119	mfspr	r3,SPRN_L1CSR1
120	and.	r1,r3,r2
121	bne	1b
122
123	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
124	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
125	mtspr	SPRN_L1CSR1,r3
126	isync
1272:
128	mfspr	r3,SPRN_L1CSR1
129	andi.	r1,r3,L1CSR1_ICE@l
130	beq	2b
131
132	/* Enable/invalidate the D-Cache */
133	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
134	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
135	mtspr	SPRN_L1CSR0,r2
1361:
137	mfspr	r3,SPRN_L1CSR0
138	and.	r1,r3,r2
139	bne	1b
140
141	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
142	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
143	mtspr	SPRN_L1CSR0,r3
144	isync
1452:
146	mfspr	r3,SPRN_L1CSR0
147	andi.	r1,r3,L1CSR0_DCE@l
148	beq	2b
149
150#define toreset(x) (x - __secondary_start_page + 0xfffff000)
151
152	/* get our PIR to figure out our table entry */
153	lis	r3,toreset(__spin_table)@h
154	ori	r3,r3,toreset(__spin_table)@l
155
156	/* r10 has the base address for the entry */
157	mfspr	r0,SPRN_PIR
158#ifdef CONFIG_E500MC
159	rlwinm	r4,r0,27,27,31
160#else
161	mr	r4,r0
162#endif
163	slwi	r8,r4,5
164	add	r10,r3,r8
165
166#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
167	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
168	slwi	r8,r4,1
169	addi	r8,r8,32
170	mtspr	L1CSR2,r8
171#endif
172
173#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
174	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
175	/*
176	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
177	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
178	 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
179	 */
180	mfspr   r3,SPRN_SVR
181	rlwinm	r6,r3,24,~0x800		/* clear E bit */
182
183	lis	r5,SVR_P4080@h
184	ori	r5,r5,SVR_P4080@l
185	cmpw	r6,r5
186	bne	1f
187
188	rlwinm  r3,r3,0,0xf0
189	li      r5,0x30
190	cmpw    r3,r5
191	bge     2f
1921:
193#ifdef	CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
194	lis	r3,toreset(enable_cpu_a011_workaround)@ha
195	lwz	r3,toreset(enable_cpu_a011_workaround)@l(r3)
196	cmpwi	r3,0
197	beq	2f
198#endif
199	mfspr	r3,L1CSR2
200	oris	r3,r3,(L1CSR2_DCWS)@h
201	mtspr	L1CSR2,r3
2022:
203#endif
204
205#ifdef CONFIG_BACKSIDE_L2_CACHE
206	/* skip L2 setup on P2040/P2040E as they have no L2 */
207	mfspr	r3,SPRN_SVR
208	rlwinm	r6,r3,24,~0x800		/* clear E bit of SVR */
209
210	lis	r3,SVR_P2040@h
211	ori	r3,r3,SVR_P2040@l
212	cmpw	r6,r3
213	beq 3f
214
215	/* Enable/invalidate the L2 cache */
216	msync
217	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
218	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
219	mtspr	SPRN_L2CSR0,r2
2201:
221	mfspr	r3,SPRN_L2CSR0
222	and.	r1,r3,r2
223	bne	1b
224
225#ifdef CONFIG_SYS_CACHE_STASHING
226	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
227	addi	r3,r8,1
228	mtspr	SPRN_L2CSR1,r3
229#endif
230
231	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
232	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
233	mtspr	SPRN_L2CSR0,r3
234	isync
2352:
236	mfspr	r3,SPRN_L2CSR0
237	andis.	r1,r3,L2CSR0_L2E@h
238	beq	2b
239#endif
2403:
241
242#define EPAPR_MAGIC		(0x45504150)
243#define ENTRY_ADDR_UPPER	0
244#define ENTRY_ADDR_LOWER	4
245#define ENTRY_R3_UPPER		8
246#define ENTRY_R3_LOWER		12
247#define ENTRY_RESV		16
248#define ENTRY_PIR		20
249#define ENTRY_R6_UPPER		24
250#define ENTRY_R6_LOWER		28
251#define ENTRY_SIZE		32
252
253	/* setup the entry */
254	li	r3,0
255	li	r8,1
256	stw	r0,ENTRY_PIR(r10)
257	stw	r3,ENTRY_ADDR_UPPER(r10)
258	stw	r8,ENTRY_ADDR_LOWER(r10)
259	stw	r3,ENTRY_R3_UPPER(r10)
260	stw	r4,ENTRY_R3_LOWER(r10)
261	stw	r3,ENTRY_R6_UPPER(r10)
262	stw	r3,ENTRY_R6_LOWER(r10)
263
264	/* load r13 with the address of the 'bootpg' in SDRAM */
265	lis	r13,toreset(__bootpg_addr)@h
266	ori	r13,r13,toreset(__bootpg_addr)@l
267	lwz	r13,0(r13)
268
269	/* setup mapping for AS = 1, and jump there */
270	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
271	mtspr	SPRN_MAS0,r11
272	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
273	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
274	mtspr	SPRN_MAS1,r11
275	oris	r11,r13,(MAS2_I|MAS2_G)@h
276	ori	r11,r13,(MAS2_I|MAS2_G)@l
277	mtspr	SPRN_MAS2,r11
278	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
279	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
280	mtspr	SPRN_MAS3,r11
281	tlbwe
282
283	bl	1f
2841:	mflr	r11
285	/*
286	 * OR in 0xfff to create a mask of the bootpg SDRAM address.  We use
287	 * this mask to fixup the cpu spin table and the address that we want
288	 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
289	 * bootpg is at 0x7ffff000 in SDRAM.
290	 */
291	ori	r13,r13,0xfff
292	and	r11, r11, r13
293	and	r10, r10, r13
294
295	addi	r11,r11,(2f-1b)
296	mfmsr	r13
297	ori	r12,r13,MSR_IS|MSR_DS@l
298
299	mtspr	SPRN_SRR0,r11
300	mtspr	SPRN_SRR1,r12
301	rfi
302
303	/* spin waiting for addr */
3042:
305	lwz	r4,ENTRY_ADDR_LOWER(r10)
306	andi.	r11,r4,1
307	bne	2b
308	isync
309
310	/* setup IVORs to match fixed offsets */
311#include "fixed_ivor.S"
312
313	/* get the upper bits of the addr */
314	lwz	r11,ENTRY_ADDR_UPPER(r10)
315
316	/* setup branch addr */
317	mtspr	SPRN_SRR0,r4
318
319	/* mark the entry as released */
320	li	r8,3
321	stw	r8,ENTRY_ADDR_LOWER(r10)
322
323	/* mask by ~64M to setup our tlb we will jump to */
324	rlwinm	r12,r4,0,0,5
325
326	/* setup r3, r4, r5, r6, r7, r8, r9 */
327	lwz	r3,ENTRY_R3_LOWER(r10)
328	li	r4,0
329	li	r5,0
330	lwz	r6,ENTRY_R6_LOWER(r10)
331	lis	r7,(64*1024*1024)@h
332	li	r8,0
333	li	r9,0
334
335	/* load up the pir */
336	lwz	r0,ENTRY_PIR(r10)
337	mtspr	SPRN_PIR,r0
338	mfspr	r0,SPRN_PIR
339	stw	r0,ENTRY_PIR(r10)
340
341	mtspr	IVPR,r12
342/*
343 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
344 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
345 * second mapping that maps addr 1:1 for 64M, and then we jump to
346 * addr
347 */
348	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
349	mtspr	SPRN_MAS0,r10
350	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
351	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
352	mtspr	SPRN_MAS1,r10
353	/* WIMGE = 0b00000 for now */
354	mtspr	SPRN_MAS2,r12
355	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
356	mtspr	SPRN_MAS3,r12
357#ifdef CONFIG_ENABLE_36BIT_PHYS
358	mtspr	SPRN_MAS7,r11
359#endif
360	tlbwe
361
362/* Now we have another mapping for this page, so we jump to that
363 * mapping
364 */
365	mtspr	SPRN_SRR1,r13
366	rfi
367
368	/*
369	 * Allocate some space for the SDRAM address of the bootpg.
370	 * This variable has to be in the boot page so that it can
371	 * be accessed by secondary cores when they come out of reset.
372	 */
373	.globl __bootpg_addr
374__bootpg_addr:
375	.long	0
376
377	.align L1_CACHE_SHIFT
378	.globl __spin_table
379__spin_table:
380	.space CONFIG_MAX_CPUS*ENTRY_SIZE
381
382	/*
383	 * This variable is set by cpu_init_r() after parsing hwconfig
384	 * to enable workaround for erratum NMG_CPU_A011.
385	 */
386	.align L1_CACHE_SHIFT
387	.global enable_cpu_a011_workaround
388enable_cpu_a011_workaround:
389	.long	1
390
391	/* Fill in the empty space.  The actual reset vector is
392	 * the last word of the page */
393__secondary_start_code_end:
394	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
395__secondary_reset_vector:
396	b	__secondary_start_page
397